drivers/net/smc9194.h

   1 /*------------------------------------------------------------------------
   2  . smc9194.h
   3  . Copyright (C) 1996 by Erik Stahlman
   4  .
   5  . This software may be used and distributed according to the terms
   6  . of the GNU General Public License, incorporated herein by reference.
   7  .
   8  . This file contains register information and access macros for
   9  . the SMC91xxx chipset.
  10  .
  11  . Information contained in this file was obtained from the SMC91C94
  12  . manual from SMC.  To get a copy, if you really want one, you can find
  13  . information under www.smc.com in the components division.
  14  . ( this thanks to advice from Donald Becker ).
  15  .
  16  . Authors
  17  .      Erik Stahlman                           ( erik@vt.edu )
  18  .
  19  . History
  20  . 01/06/96              Erik Stahlman   moved definitions here from main .c file
  21  . 01/19/96              Erik Stahlman    polished this up some, and added better
  22  .                                                                                error handling
  23  .
  24  ---------------------------------------------------------------------------*/
  25 #ifndef _SMC9194_H_
  26 #define _SMC9194_H_
  27
  28 /* I want some simple types */
  29
  30 typedef unsigned char                   byte;
  31 typedef unsigned short                  word;
  32 typedef unsigned long int               dword;
  33
  34
  35 /* Because of bank switching, the SMC91xxx uses only 16 I/O ports */
  36
  37 #define SMC_IO_EXTENT   16
  38
  39
  40 /*---------------------------------------------------------------
  41  .
  42  . A description of the SMC registers is probably in order here,
  43  . although for details, the SMC datasheet is invaluable.
  44  .
  45  . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
  46  . are accessed by writing a number into the BANK_SELECT register
  47  . ( I also use a SMC_SELECT_BANK macro for this ).
  48  .
  49  . The banks are configured so that for most purposes, bank 2 is all
  50  . that is needed for simple run time tasks.
  51  -----------------------------------------------------------------------*/
  52
  53 /*
  54  . Bank Select Register:
  55  .
  56  .              yyyy yyyy 0000 00xx
  57  .              xx              = bank number
  58  .              yyyy yyyy       = 0x33, for identification purposes.
  59 */
  60 #define BANK_SELECT             14
  61
  62 /* BANK 0  */
  63
  64 #define TCR             0       /* transmit control register */
  65 #define TCR_ENABLE      0x0001  /* if this is 1, we can transmit */
  66 #define TCR_FDUPLX      0x0800  /* receive packets sent out */
  67 #define TCR_STP_SQET    0x1000  /* stop transmitting if Signal quality error */
  68 #define TCR_MON_CNS     0x0400  /* monitors the carrier status */
  69 #define TCR_PAD_ENABLE  0x0080  /* pads short packets to 64 bytes */
  70
  71 #define TCR_CLEAR       0       /* do NOTHING */
  72 /* the normal settings for the TCR register : */
  73 /* QUESTION: do I want to enable padding of short packets ? */
  74 #define TCR_NORMAL      TCR_ENABLE
  75
  76
  77 #define EPH_STATUS      2
  78 #define ES_LINK_OK      0x4000  /* is the link integrity ok ? */
  79
  80 #define RCR             4
  81 #define RCR_SOFTRESET   0x8000  /* resets the chip */
  82 #define RCR_STRIP_CRC   0x200   /* strips CRC */
  83 #define RCR_ENABLE      0x100   /* IFF this is set, we can receive packets */
  84 #define RCR_ALMUL       0x4     /* receive all multicast packets */
  85 #define RCR_PROMISC     0x2     /* enable promiscuous mode */
  86
  87 /* the normal settings for the RCR register : */
  88 #define RCR_NORMAL      (RCR_STRIP_CRC | RCR_ENABLE)
  89 #define RCR_CLEAR       0x0             /* set it to a base state */
  90
  91 #define COUNTER         6
  92 #define MIR             8
  93 #define MCR             10
  94 /* 12 is reserved */
  95
  96 /* BANK 1 */
  97 #define CONFIG                  0
  98 #define CFG_AUI_SELECT          0x100
  99 #define CFG_NO_WAIT             0x1000
 100 #define CFG_MII_SELECT          0x8000
 101 #define BASE                    2
 102 #define ADDR0                   4
 103 #define ADDR1                   6
 104 #define ADDR2                   8
 105 #define GENERAL                 10
 106 #define CONTROL                 12
 107 #define CTL_POWERDOWN           0x2000
 108 #define CTL_LE_ENABLE           0x80
 109 #define CTL_CR_ENABLE           0x40
 110 #define CTL_TE_ENABLE           0x0020
 111 #define CTL_AUTO_RELEASE        0x0800
 112 #define CTL_EPROM_ACCESS        0x0003 /* high if Eprom is being read */
 113
 114 /* BANK 2 */
 115 #define MMU_CMD         0
 116 #define MC_BUSY         1       /* only readable bit in the register */
 117 #define MC_NOP          0
 118 #define MC_ALLOC        0x20    /* or with number of 256 byte packets */
 119 #define MC_RESET        0x40
 120 #define MC_REMOVE       0x60    /* remove the current rx packet */
 121 #define MC_RELEASE      0x80    /* remove and release the current rx packet */
 122 #define MC_FREEPKT      0xA0    /* Release packet in PNR register */
 123 #define MC_ENQUEUE      0xC0    /* Enqueue the packet for transmit */
 124
 125 #define PNR_ARR         2
 126 #define FIFO_PORTS      4
 127
 128 #define FP_RXEMPTY  0x8000
 129 #define FP_TXEMPTY  0x80
 130
 131 #define POINTER         6
 132 #define PTR_READ        0x2000
 133 #define PTR_RCV         0x8000
 134 #define PTR_AUTOINC     0x4000
 135 #define PTR_AUTO_INC    0x0040
 136
 137 #define DATA_1          8
 138 #define DATA_2          10
 139 #define INTERRUPT       12
 140
 141 #define INT_MASK        13
 142 #define IM_RCV_INT      0x1
 143 #define IM_TX_INT       0x2
 144 #define IM_TX_EMPTY_INT 0x4
 145 #define IM_ALLOC_INT    0x8
 146 #define IM_RX_OVRN_INT  0x10
 147 #define IM_EPH_INT      0x20
 148 #define IM_ERCV_INT     0x40 /* not on SMC9192 */
 149
 150 /* BANK 3 */
 151 #define MULTICAST1      0
 152 #define MULTICAST2      2
 153 #define MULTICAST3      4
 154 #define MULTICAST4      6
 155 #define MGMT            8
 156 #define REVISION        10 /* ( hi: chip id   low: rev # ) */
 157
 158
 159 /* this is NOT on SMC9192 */
 160 #define ERCV            12
 161
 162 #define CHIP_9190       3
 163 #define CHIP_9194       4
 164 #define CHIP_9195       5
 165 #define CHIP_91100      7
 166
 167 static const char * chip_ids[ 15 ] =  {
 168         NULL, NULL, NULL,
 169         /* 3 */ "SMC91C90/91C92",
 170         /* 4 */ "SMC91C94",
 171         /* 5 */ "SMC91C95",
 172         NULL,
 173         /* 7 */ "SMC91C100",
 174         /* 8 */ "SMC91C100FD",
 175         NULL, NULL, NULL,
 176         NULL, NULL, NULL};
 177
 178 /*
 179  . Transmit status bits
 180 */
 181 #define TS_SUCCESS 0x0001
 182 #define TS_LOSTCAR 0x0400
 183 #define TS_LATCOL  0x0200
 184 #define TS_16COL   0x0010
 185
 186 /*
 187  . Receive status bits
 188 */
 189 #define RS_ALGNERR      0x8000
 190 #define RS_BADCRC       0x2000
 191 #define RS_ODDFRAME     0x1000
 192 #define RS_TOOLONG      0x0800
 193 #define RS_TOOSHORT     0x0400
 194 #define RS_MULTICAST    0x0001
 195 #define RS_ERRORS       (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
 196
 197 static const char * interfaces[ 2 ] = { "TP", "AUI" };
 198
 199 /*-------------------------------------------------------------------------
 200  .  I define some macros to make it easier to do somewhat common
 201  . or slightly complicated, repeated tasks.
 202  --------------------------------------------------------------------------*/
 203
 204 /* select a register bank, 0 to 3  */
 205
 206 #define SMC_SELECT_BANK(x)  { outw( x, ioaddr + BANK_SELECT ); }
 207
 208 /* define a small delay for the reset */
 209 #define SMC_DELAY() { inw( ioaddr + RCR );\
 210                         inw( ioaddr + RCR );\
 211                         inw( ioaddr + RCR );  }
 212
 213 #if defined(CONFIG_COLDFIRE) || defined(CONFIG_M68EZ328)
 214
 215 /* this enables an interrupt in the interrupt mask register */
 216 #define SMC_ENABLE_INT(x) {\
 217                 unsigned char mask;\
 218                 SMC_SELECT_BANK(2);\
 219                 mask = inb( ioaddr + INT_MASK );\
 220                 mask |= (x);\
 221                 outw( mask << 8, ioaddr + INTERRUPT ); \
 222 }
 223
 224 /* this disables an interrupt from the interrupt mask register */
 225
 226 #define SMC_DISABLE_INT(x) {\
 227                 unsigned char mask;\
 228                 SMC_SELECT_BANK(2);\
 229                 mask = inb( ioaddr + INT_MASK );\
 230                 mask &= ~(x);\
 231                 outw( mask << 8, ioaddr + INTERRUPT ); \
 232 }
 233
 234 /* set the interrupt mask register */
 235 #define SMC_SET_INT(x) {\
 236                 SMC_SELECT_BANK(2);\
 237                 outw( ((unsigned short) (x)) << 8, ioaddr + INTERRUPT );\
 238 }
 239
 240 /* acknowledge an interrupt */
 241 #define SMC_ACK_INT(x) {\
 242                 unsigned short val;\
 243                 /* assume BANK 2 selected */\
 244                 val = inb( ioaddr + INT_MASK );\
 245                 val = (val << 8) | (x);\
 246                 outw( val, ioaddr + INTERRUPT );\
 247 }
 248
 249 #else
 250
 251 /* this enables an interrupt in the interrupt mask register */
 252 #define SMC_ENABLE_INT(x) {\
 253                 unsigned char mask;\
 254                 SMC_SELECT_BANK(2);\
 255                 mask = inb( ioaddr + INT_MASK );\
 256                 mask |= (x);\
 257                 outb( mask, ioaddr + INT_MASK ); \
 258 }
 259
 260 /* this disables an interrupt from the interrupt mask register */
 261
 262 #define SMC_DISABLE_INT(x) {\
 263                 unsigned char mask;\
 264                 SMC_SELECT_BANK(2);\
 265                 mask = inb( ioaddr + INT_MASK );\
 266                 mask &= ~(x);\
 267                 outb( mask, ioaddr + INT_MASK ); \
 268 }
 269
 270 /* set the interrupt mask register */
 271 #define SMC_SET_INT(x) {\
 272                 SMC_SELECT_BANK(2);\
 273                 outb( (x), ioaddr + INT_MASK );\
 274 }
 275
 276 /* acknowledge an interrupt */
 277 #define SMC_ACK_INT(x)  outb( (x), ioaddr + INTERRUPT )
 278
 279 #endif
 280
 281 /*----------------------------------------------------------------------
 282  . Define the interrupts that I want to receive from the card
 283  .
 284  . I want:
 285  .  IM_EPH_INT, for nasty errors
 286  .  IM_RCV_INT, for happy received packets
 287  .  IM_RX_OVRN_INT, because I have to kick the receiver
 288  --------------------------------------------------------------------------*/
 289 #define SMC_INTERRUPT_MASK   (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT)
 290
 291 #endif  /* _SMC_9194_H_ */
 292