drivers/net/ns83865phy.h

   1 /*--------------------------------------------------------------------
   2
   3  * ns83865.h
   4
   5  *
   6
   7  * National NS83865 specific ethernet transceiver phy registers (09-31)
   8
   9  *
  10
  11  * Copyright (C) 2004   Microtronix Datacom Ltd
  12
  13  *
  14
  15  * This program is free software; you can redistribute it and/or modify
  16
  17  * it under the terms of the GNU General Public License as published by
  18
  19  * the Free Software Foundation; either version 2 of the License, or
  20
  21  * (at your option) any later version.
  22
  23  *
  24
  25  * This program is distributed in the hope that it will be useful,
  26
  27  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  28
  29  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30
  31  * GNU General Public License for more details.
  32
  33  *
  34
  35  * Apr2004      DGT Microtronix Datacom
  36
  37  *
  38
  39  ---------------------------------------------------------------------*/
  40
  41
  42
  43 #ifndef _NS883865PHY_H_
  44
  45     #define _NS883865PHY_H_
  46
  47
  48
  49 // Link Status Register
  50
  51 #define NS883865_LNKSTS_REG         0x11    // Phy Reg17
  52
  53 //
  54
  55 #define NS883865_LNKSTS_100_MASK       0x0008  // 100 Mbps
  56
  57 #define NS883865_LNKSTS_LNKUP_MASK     0x0004  // Link Up
  58
  59 #define NS883865_LNKSTS_FDUPLX_MASK    0x0002  // Full duplex
  60
  61
  62
  63 // Interrupt Status Register
  64
  65 #define NS883865_INTSTS_REG         0x14    // Phy Reg20
  66
  67 //
  68
  69 #define NS883865_INTSTS_LSCHG_MASK     0x4000 // Link status change
  70
  71 #define NS883865_INTSTS_ANEGDONE_MASK  0x0010 // Auto neg done
  72
  73
  74
  75 // Interrupt Enable Register
  76
  77 #define NS883865_INTIE_REG          0x15    // Phy Reg21
  78
  79 //
  80
  81 #define NS883865_INTIE_LSCHG_MASK      NS883865_INTSTS_LSCHG_MASK
  82
  83 #define NS883865_INTIE_ANEGDONE_MASK   NS883865_INTSTS_ANEGDONE_MASK
  84
  85
  86
  87 // Interrupt Ack Register
  88
  89 #define NS883865_INTACK_REG         0x17    // Phy Reg23
  90
  91 //
  92
  93 #define NS883865_INTACK_LSCHG_MASK     NS883865_INTSTS_LSCHG_MASK
  94
  95 #define NS883865_INTACK_ANEGDONE_MASK  NS883865_INTSTS_ANEGDONE_MASK
  96
  97 #endif  /* _NS883865PHY_H_ */
  98