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MOXA linux-2.6.x / linux-2.6.19-uc1 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz
[linux-2.6.19-moxart.git] / drivers / net / forcedeth.c
blobc5ed635bce36dc754416cb2f53827f82e5aabd3f
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
8 *
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
11 * countries.
12 *
13 * Copyright (C) 2003,4,5 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 *
33 * Changelog:
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
42 * irq mask updated
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
57 * open.
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
61 * the tx length.
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
69 * on close.
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
83 * capabilities.
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
91 * per-packet flags.
92 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
93 * 0.40: 19 Jul 2005: Add support for mac address change.
94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
95 * of nv_remove
96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
97 * in the second (and later) nv_open call
98 * 0.43: 10 Aug 2005: Add support for tx checksum.
99 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
101 * 0.46: 20 Oct 2005: Add irq optimization modes.
102 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
103 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
104 * 0.49: 10 Dec 2005: Fix tso for large buffers.
105 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
106 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
107 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
108 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
109 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
110 * 0.55: 22 Mar 2006: Add flow control (pause frame).
111 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
112 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
113 *
114 * Known bugs:
115 * We suspect that on some hardware no TX done interrupts are generated.
116 * This means recovery from netif_stop_queue only happens if the hw timer
117 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
118 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
119 * If your hardware reliably generates tx done interrupts, then you can remove
120 * DEV_NEED_TIMERIRQ from the driver_data flags.
121 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
122 * superfluous timer interrupts from the nic.
123 */
124 #ifdef CONFIG_FORCEDETH_NAPI
125 #define DRIVERNAPI "-NAPI"
126 #else
127 #define DRIVERNAPI
128 #endif
129 #define FORCEDETH_VERSION "0.57"
130 #define DRV_NAME "forcedeth"
131
132 #include <linux/module.h>
133 #include <linux/types.h>
134 #include <linux/pci.h>
135 #include <linux/interrupt.h>
136 #include <linux/netdevice.h>
137 #include <linux/etherdevice.h>
138 #include <linux/delay.h>
139 #include <linux/spinlock.h>
140 #include <linux/ethtool.h>
141 #include <linux/timer.h>
142 #include <linux/skbuff.h>
143 #include <linux/mii.h>
144 #include <linux/random.h>
145 #include <linux/init.h>
146 #include <linux/if_vlan.h>
147 #include <linux/dma-mapping.h>
148
149 #include <asm/irq.h>
150 #include <asm/io.h>
151 #include <asm/uaccess.h>
152 #include <asm/system.h>
153
154 #if 0
155 #define dprintk printk
156 #else
157 #define dprintk(x...) do { } while (0)
158 #endif
159
160
161 /*
162 * Hardware access:
163 */
164
165 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
166 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
167 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
168 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
169 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
170 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
171 #define DEV_HAS_MSI 0x0040 /* device supports MSI */
172 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
173 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
174 #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
175 #define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
176 #define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */
177
178 enum {
179 NvRegIrqStatus = 0x000,
180 #define NVREG_IRQSTAT_MIIEVENT 0x040
181 #define NVREG_IRQSTAT_MASK 0x1ff
182 NvRegIrqMask = 0x004,
183 #define NVREG_IRQ_RX_ERROR 0x0001
184 #define NVREG_IRQ_RX 0x0002
185 #define NVREG_IRQ_RX_NOBUF 0x0004
186 #define NVREG_IRQ_TX_ERR 0x0008
187 #define NVREG_IRQ_TX_OK 0x0010
188 #define NVREG_IRQ_TIMER 0x0020
189 #define NVREG_IRQ_LINK 0x0040
190 #define NVREG_IRQ_RX_FORCED 0x0080
191 #define NVREG_IRQ_TX_FORCED 0x0100
192 #define NVREG_IRQMASK_THROUGHPUT 0x00df
193 #define NVREG_IRQMASK_CPU 0x0040
194 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
195 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
196 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
197
198 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
199 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
200 NVREG_IRQ_TX_FORCED))
201
202 NvRegUnknownSetupReg6 = 0x008,
203 #define NVREG_UNKSETUP6_VAL 3
204
205 /*
206 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
207 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
208 */
209 NvRegPollingInterval = 0x00c,
210 #define NVREG_POLL_DEFAULT_THROUGHPUT 970
211 #define NVREG_POLL_DEFAULT_CPU 13
212 NvRegMSIMap0 = 0x020,
213 NvRegMSIMap1 = 0x024,
214 NvRegMSIIrqMask = 0x030,
215 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
216 NvRegMisc1 = 0x080,
217 #define NVREG_MISC1_PAUSE_TX 0x01
218 #define NVREG_MISC1_HD 0x02
219 #define NVREG_MISC1_FORCE 0x3b0f3c
220
221 NvRegMacReset = 0x3c,
222 #define NVREG_MAC_RESET_ASSERT 0x0F3
223 NvRegTransmitterControl = 0x084,
224 #define NVREG_XMITCTL_START 0x01
225 NvRegTransmitterStatus = 0x088,
226 #define NVREG_XMITSTAT_BUSY 0x01
227
228 NvRegPacketFilterFlags = 0x8c,
229 #define NVREG_PFF_PAUSE_RX 0x08
230 #define NVREG_PFF_ALWAYS 0x7F0000
231 #define NVREG_PFF_PROMISC 0x80
232 #define NVREG_PFF_MYADDR 0x20
233 #define NVREG_PFF_LOOPBACK 0x10
234
235 NvRegOffloadConfig = 0x90,
236 #define NVREG_OFFLOAD_HOMEPHY 0x601
237 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
238 NvRegReceiverControl = 0x094,
239 #define NVREG_RCVCTL_START 0x01
240 NvRegReceiverStatus = 0x98,
241 #define NVREG_RCVSTAT_BUSY 0x01
242
243 NvRegRandomSeed = 0x9c,
244 #define NVREG_RNDSEED_MASK 0x00ff
245 #define NVREG_RNDSEED_FORCE 0x7f00
246 #define NVREG_RNDSEED_FORCE2 0x2d00
247 #define NVREG_RNDSEED_FORCE3 0x7400
248
249 NvRegTxDeferral = 0xA0,
250 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
251 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
252 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
253 NvRegRxDeferral = 0xA4,
254 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
255 NvRegMacAddrA = 0xA8,
256 NvRegMacAddrB = 0xAC,
257 NvRegMulticastAddrA = 0xB0,
258 #define NVREG_MCASTADDRA_FORCE 0x01
259 NvRegMulticastAddrB = 0xB4,
260 NvRegMulticastMaskA = 0xB8,
261 NvRegMulticastMaskB = 0xBC,
262
263 NvRegPhyInterface = 0xC0,
264 #define PHY_RGMII 0x10000000
265
266 NvRegTxRingPhysAddr = 0x100,
267 NvRegRxRingPhysAddr = 0x104,
268 NvRegRingSizes = 0x108,
269 #define NVREG_RINGSZ_TXSHIFT 0
270 #define NVREG_RINGSZ_RXSHIFT 16
271 NvRegTransmitPoll = 0x10c,
272 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
273 NvRegLinkSpeed = 0x110,
274 #define NVREG_LINKSPEED_FORCE 0x10000
275 #define NVREG_LINKSPEED_10 1000
276 #define NVREG_LINKSPEED_100 100
277 #define NVREG_LINKSPEED_1000 50
278 #define NVREG_LINKSPEED_MASK (0xFFF)
279 NvRegUnknownSetupReg5 = 0x130,
280 #define NVREG_UNKSETUP5_BIT31 (1<<31)
281 NvRegTxWatermark = 0x13c,
282 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
283 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
284 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
285 NvRegTxRxControl = 0x144,
286 #define NVREG_TXRXCTL_KICK 0x0001
287 #define NVREG_TXRXCTL_BIT1 0x0002
288 #define NVREG_TXRXCTL_BIT2 0x0004
289 #define NVREG_TXRXCTL_IDLE 0x0008
290 #define NVREG_TXRXCTL_RESET 0x0010
291 #define NVREG_TXRXCTL_RXCHECK 0x0400
292 #define NVREG_TXRXCTL_DESC_1 0
293 #define NVREG_TXRXCTL_DESC_2 0x02100
294 #define NVREG_TXRXCTL_DESC_3 0x02200
295 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
296 #define NVREG_TXRXCTL_VLANINS 0x00080
297 NvRegTxRingPhysAddrHigh = 0x148,
298 NvRegRxRingPhysAddrHigh = 0x14C,
299 NvRegTxPauseFrame = 0x170,
300 #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080
301 #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030
302 NvRegMIIStatus = 0x180,
303 #define NVREG_MIISTAT_ERROR 0x0001
304 #define NVREG_MIISTAT_LINKCHANGE 0x0008
305 #define NVREG_MIISTAT_MASK 0x000f
306 #define NVREG_MIISTAT_MASK2 0x000f
307 NvRegUnknownSetupReg4 = 0x184,
308 #define NVREG_UNKSETUP4_VAL 8
309
310 NvRegAdapterControl = 0x188,
311 #define NVREG_ADAPTCTL_START 0x02
312 #define NVREG_ADAPTCTL_LINKUP 0x04
313 #define NVREG_ADAPTCTL_PHYVALID 0x40000
314 #define NVREG_ADAPTCTL_RUNNING 0x100000
315 #define NVREG_ADAPTCTL_PHYSHIFT 24
316 NvRegMIISpeed = 0x18c,
317 #define NVREG_MIISPEED_BIT8 (1<<8)
318 #define NVREG_MIIDELAY 5
319 NvRegMIIControl = 0x190,
320 #define NVREG_MIICTL_INUSE 0x08000
321 #define NVREG_MIICTL_WRITE 0x00400
322 #define NVREG_MIICTL_ADDRSHIFT 5
323 NvRegMIIData = 0x194,
324 NvRegWakeUpFlags = 0x200,
325 #define NVREG_WAKEUPFLAGS_VAL 0x7770
326 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
327 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
328 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
329 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
330 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
331 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
332 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
333 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
334 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
335 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
336
337 NvRegPatternCRC = 0x204,
338 NvRegPatternMask = 0x208,
339 NvRegPowerCap = 0x268,
340 #define NVREG_POWERCAP_D3SUPP (1<<30)
341 #define NVREG_POWERCAP_D2SUPP (1<<26)
342 #define NVREG_POWERCAP_D1SUPP (1<<25)
343 NvRegPowerState = 0x26c,
344 #define NVREG_POWERSTATE_POWEREDUP 0x8000
345 #define NVREG_POWERSTATE_VALID 0x0100
346 #define NVREG_POWERSTATE_MASK 0x0003
347 #define NVREG_POWERSTATE_D0 0x0000
348 #define NVREG_POWERSTATE_D1 0x0001
349 #define NVREG_POWERSTATE_D2 0x0002
350 #define NVREG_POWERSTATE_D3 0x0003
351 NvRegTxCnt = 0x280,
352 NvRegTxZeroReXmt = 0x284,
353 NvRegTxOneReXmt = 0x288,
354 NvRegTxManyReXmt = 0x28c,
355 NvRegTxLateCol = 0x290,
356 NvRegTxUnderflow = 0x294,
357 NvRegTxLossCarrier = 0x298,
358 NvRegTxExcessDef = 0x29c,
359 NvRegTxRetryErr = 0x2a0,
360 NvRegRxFrameErr = 0x2a4,
361 NvRegRxExtraByte = 0x2a8,
362 NvRegRxLateCol = 0x2ac,
363 NvRegRxRunt = 0x2b0,
364 NvRegRxFrameTooLong = 0x2b4,
365 NvRegRxOverflow = 0x2b8,
366 NvRegRxFCSErr = 0x2bc,
367 NvRegRxFrameAlignErr = 0x2c0,
368 NvRegRxLenErr = 0x2c4,
369 NvRegRxUnicast = 0x2c8,
370 NvRegRxMulticast = 0x2cc,
371 NvRegRxBroadcast = 0x2d0,
372 NvRegTxDef = 0x2d4,
373 NvRegTxFrame = 0x2d8,
374 NvRegRxCnt = 0x2dc,
375 NvRegTxPause = 0x2e0,
376 NvRegRxPause = 0x2e4,
377 NvRegRxDropFrame = 0x2e8,
378 NvRegVlanControl = 0x300,
379 #define NVREG_VLANCONTROL_ENABLE 0x2000
380 NvRegMSIXMap0 = 0x3e0,
381 NvRegMSIXMap1 = 0x3e4,
382 NvRegMSIXIrqStatus = 0x3f0,
383
384 NvRegPowerState2 = 0x600,
385 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
386 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
387 };
388
389 /* Big endian: should work, but is untested */
390 struct ring_desc {
391 __le32 buf;
392 __le32 flaglen;
393 };
394
395 struct ring_desc_ex {
396 __le32 bufhigh;
397 __le32 buflow;
398 __le32 txvlan;
399 __le32 flaglen;
400 };
401
402 union ring_type {
403 struct ring_desc* orig;
404 struct ring_desc_ex* ex;
405 };
406
407 #define FLAG_MASK_V1 0xffff0000
408 #define FLAG_MASK_V2 0xffffc000
409 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
410 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
411
412 #define NV_TX_LASTPACKET (1<<16)
413 #define NV_TX_RETRYERROR (1<<19)
414 #define NV_TX_FORCED_INTERRUPT (1<<24)
415 #define NV_TX_DEFERRED (1<<26)
416 #define NV_TX_CARRIERLOST (1<<27)
417 #define NV_TX_LATECOLLISION (1<<28)
418 #define NV_TX_UNDERFLOW (1<<29)
419 #define NV_TX_ERROR (1<<30)
420 #define NV_TX_VALID (1<<31)
421
422 #define NV_TX2_LASTPACKET (1<<29)
423 #define NV_TX2_RETRYERROR (1<<18)
424 #define NV_TX2_FORCED_INTERRUPT (1<<30)
425 #define NV_TX2_DEFERRED (1<<25)
426 #define NV_TX2_CARRIERLOST (1<<26)
427 #define NV_TX2_LATECOLLISION (1<<27)
428 #define NV_TX2_UNDERFLOW (1<<28)
429 /* error and valid are the same for both */
430 #define NV_TX2_ERROR (1<<30)
431 #define NV_TX2_VALID (1<<31)
432 #define NV_TX2_TSO (1<<28)
433 #define NV_TX2_TSO_SHIFT 14
434 #define NV_TX2_TSO_MAX_SHIFT 14
435 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
436 #define NV_TX2_CHECKSUM_L3 (1<<27)
437 #define NV_TX2_CHECKSUM_L4 (1<<26)
438
439 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
440
441 #define NV_RX_DESCRIPTORVALID (1<<16)
442 #define NV_RX_MISSEDFRAME (1<<17)
443 #define NV_RX_SUBSTRACT1 (1<<18)
444 #define NV_RX_ERROR1 (1<<23)
445 #define NV_RX_ERROR2 (1<<24)
446 #define NV_RX_ERROR3 (1<<25)
447 #define NV_RX_ERROR4 (1<<26)
448 #define NV_RX_CRCERR (1<<27)
449 #define NV_RX_OVERFLOW (1<<28)
450 #define NV_RX_FRAMINGERR (1<<29)
451 #define NV_RX_ERROR (1<<30)
452 #define NV_RX_AVAIL (1<<31)
453
454 #define NV_RX2_CHECKSUMMASK (0x1C000000)
455 #define NV_RX2_CHECKSUMOK1 (0x10000000)
456 #define NV_RX2_CHECKSUMOK2 (0x14000000)
457 #define NV_RX2_CHECKSUMOK3 (0x18000000)
458 #define NV_RX2_DESCRIPTORVALID (1<<29)
459 #define NV_RX2_SUBSTRACT1 (1<<25)
460 #define NV_RX2_ERROR1 (1<<18)
461 #define NV_RX2_ERROR2 (1<<19)
462 #define NV_RX2_ERROR3 (1<<20)
463 #define NV_RX2_ERROR4 (1<<21)
464 #define NV_RX2_CRCERR (1<<22)
465 #define NV_RX2_OVERFLOW (1<<23)
466 #define NV_RX2_FRAMINGERR (1<<24)
467 /* error and avail are the same for both */
468 #define NV_RX2_ERROR (1<<30)
469 #define NV_RX2_AVAIL (1<<31)
470
471 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
472 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
473
474 /* Miscelaneous hardware related defines: */
475 #define NV_PCI_REGSZ_VER1 0x270
476 #define NV_PCI_REGSZ_VER2 0x604
477
478 /* various timeout delays: all in usec */
479 #define NV_TXRX_RESET_DELAY 4
480 #define NV_TXSTOP_DELAY1 10
481 #define NV_TXSTOP_DELAY1MAX 500000
482 #define NV_TXSTOP_DELAY2 100
483 #define NV_RXSTOP_DELAY1 10
484 #define NV_RXSTOP_DELAY1MAX 500000
485 #define NV_RXSTOP_DELAY2 100
486 #define NV_SETUP5_DELAY 5
487 #define NV_SETUP5_DELAYMAX 50000
488 #define NV_POWERUP_DELAY 5
489 #define NV_POWERUP_DELAYMAX 5000
490 #define NV_MIIBUSY_DELAY 50
491 #define NV_MIIPHY_DELAY 10
492 #define NV_MIIPHY_DELAYMAX 10000
493 #define NV_MAC_RESET_DELAY 64
494
495 #define NV_WAKEUPPATTERNS 5
496 #define NV_WAKEUPMASKENTRIES 4
497
498 /* General driver defaults */
499 #define NV_WATCHDOG_TIMEO (5*HZ)
500
501 #define RX_RING_DEFAULT 128
502 #define TX_RING_DEFAULT 256
503 #define RX_RING_MIN 128
504 #define TX_RING_MIN 64
505 #define RING_MAX_DESC_VER_1 1024
506 #define RING_MAX_DESC_VER_2_3 16384
507 /*
508 * Difference between the get and put pointers for the tx ring.
509 * This is used to throttle the amount of data outstanding in the
510 * tx ring.
511 */
512 #define TX_LIMIT_DIFFERENCE 1
513
514 /* rx/tx mac addr + type + vlan + align + slack*/
515 #define NV_RX_HEADERS (64)
516 /* even more slack. */
517 #define NV_RX_ALLOC_PAD (64)
518
519 /* maximum mtu size */
520 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
521 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
522
523 #define OOM_REFILL (1+HZ/20)
524 #define POLL_WAIT (1+HZ/100)
525 #define LINK_TIMEOUT (3*HZ)
526 #define STATS_INTERVAL (10*HZ)
527
528 /*
529 * desc_ver values:
530 * The nic supports three different descriptor types:
531 * - DESC_VER_1: Original
532 * - DESC_VER_2: support for jumbo frames.
533 * - DESC_VER_3: 64-bit format.
534 */
535 #define DESC_VER_1 1
536 #define DESC_VER_2 2
537 #define DESC_VER_3 3
538
539 /* PHY defines */
540 #define PHY_OUI_MARVELL 0x5043
541 #define PHY_OUI_CICADA 0x03f1
542 #define PHYID1_OUI_MASK 0x03ff
543 #define PHYID1_OUI_SHFT 6
544 #define PHYID2_OUI_MASK 0xfc00
545 #define PHYID2_OUI_SHFT 10
546 #define PHYID2_MODEL_MASK 0x03f0
547 #define PHY_MODEL_MARVELL_E3016 0x220
548 #define PHY_MARVELL_E3016_INITMASK 0x0300
549 #define PHY_INIT1 0x0f000
550 #define PHY_INIT2 0x0e00
551 #define PHY_INIT3 0x01000
552 #define PHY_INIT4 0x0200
553 #define PHY_INIT5 0x0004
554 #define PHY_INIT6 0x02000
555 #define PHY_GIGABIT 0x0100
556
557 #define PHY_TIMEOUT 0x1
558 #define PHY_ERROR 0x2
559
560 #define PHY_100 0x1
561 #define PHY_1000 0x2
562 #define PHY_HALF 0x100
563
564 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
565 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
566 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
567 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
568 #define NV_PAUSEFRAME_RX_REQ 0x0010
569 #define NV_PAUSEFRAME_TX_REQ 0x0020
570 #define NV_PAUSEFRAME_AUTONEG 0x0040
571
572 /* MSI/MSI-X defines */
573 #define NV_MSI_X_MAX_VECTORS 8
574 #define NV_MSI_X_VECTORS_MASK 0x000f
575 #define NV_MSI_CAPABLE 0x0010
576 #define NV_MSI_X_CAPABLE 0x0020
577 #define NV_MSI_ENABLED 0x0040
578 #define NV_MSI_X_ENABLED 0x0080
579
580 #define NV_MSI_X_VECTOR_ALL 0x0
581 #define NV_MSI_X_VECTOR_RX 0x0
582 #define NV_MSI_X_VECTOR_TX 0x1
583 #define NV_MSI_X_VECTOR_OTHER 0x2
584
585 /* statistics */
586 struct nv_ethtool_str {
587 char name[ETH_GSTRING_LEN];
588 };
589
590 static const struct nv_ethtool_str nv_estats_str[] = {
591 { "tx_bytes" },
592 { "tx_zero_rexmt" },
593 { "tx_one_rexmt" },
594 { "tx_many_rexmt" },
595 { "tx_late_collision" },
596 { "tx_fifo_errors" },
597 { "tx_carrier_errors" },
598 { "tx_excess_deferral" },
599 { "tx_retry_error" },
600 { "tx_deferral" },
601 { "tx_packets" },
602 { "tx_pause" },
603 { "rx_frame_error" },
604 { "rx_extra_byte" },
605 { "rx_late_collision" },
606 { "rx_runt" },
607 { "rx_frame_too_long" },
608 { "rx_over_errors" },
609 { "rx_crc_errors" },
610 { "rx_frame_align_error" },
611 { "rx_length_error" },
612 { "rx_unicast" },
613 { "rx_multicast" },
614 { "rx_broadcast" },
615 { "rx_bytes" },
616 { "rx_pause" },
617 { "rx_drop_frame" },
618 { "rx_packets" },
619 { "rx_errors_total" }
620 };
621
622 struct nv_ethtool_stats {
623 u64 tx_bytes;
624 u64 tx_zero_rexmt;
625 u64 tx_one_rexmt;
626 u64 tx_many_rexmt;
627 u64 tx_late_collision;
628 u64 tx_fifo_errors;
629 u64 tx_carrier_errors;
630 u64 tx_excess_deferral;
631 u64 tx_retry_error;
632 u64 tx_deferral;
633 u64 tx_packets;
634 u64 tx_pause;
635 u64 rx_frame_error;
636 u64 rx_extra_byte;
637 u64 rx_late_collision;
638 u64 rx_runt;
639 u64 rx_frame_too_long;
640 u64 rx_over_errors;
641 u64 rx_crc_errors;
642 u64 rx_frame_align_error;
643 u64 rx_length_error;
644 u64 rx_unicast;
645 u64 rx_multicast;
646 u64 rx_broadcast;
647 u64 rx_bytes;
648 u64 rx_pause;
649 u64 rx_drop_frame;
650 u64 rx_packets;
651 u64 rx_errors_total;
652 };
653
654 /* diagnostics */
655 #define NV_TEST_COUNT_BASE 3
656 #define NV_TEST_COUNT_EXTENDED 4
657
658 static const struct nv_ethtool_str nv_etests_str[] = {
659 { "link (online/offline)" },
660 { "register (offline) " },
661 { "interrupt (offline) " },
662 { "loopback (offline) " }
663 };
664
665 struct register_test {
666 __le32 reg;
667 __le32 mask;
668 };
669
670 static const struct register_test nv_registers_test[] = {
671 { NvRegUnknownSetupReg6, 0x01 },
672 { NvRegMisc1, 0x03c },
673 { NvRegOffloadConfig, 0x03ff },
674 { NvRegMulticastAddrA, 0xffffffff },
675 { NvRegTxWatermark, 0x0ff },
676 { NvRegWakeUpFlags, 0x07777 },
677 { 0,0 }
678 };
679
680 /*
681 * SMP locking:
682 * All hardware access under dev->priv->lock, except the performance
683 * critical parts:
684 * - rx is (pseudo-) lockless: it relies on the single-threading provided
685 * by the arch code for interrupts.
686 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
687 * needs dev->priv->lock :-(
688 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
689 */
690
691 /* in dev: base, irq */
692 struct fe_priv {
693 spinlock_t lock;
694
695 /* General data:
696 * Locking: spin_lock(&np->lock); */
697 struct net_device_stats stats;
698 struct nv_ethtool_stats estats;
699 int in_shutdown;
700 u32 linkspeed;
701 int duplex;
702 int autoneg;
703 int fixed_mode;
704 int phyaddr;
705 int wolenabled;
706 unsigned int phy_oui;
707 unsigned int phy_model;
708 u16 gigabit;
709 int intr_test;
710
711 /* General data: RO fields */
712 dma_addr_t ring_addr;
713 struct pci_dev *pci_dev;
714 u32 orig_mac[2];
715 u32 irqmask;
716 u32 desc_ver;
717 u32 txrxctl_bits;
718 u32 vlanctl_bits;
719 u32 driver_data;
720 u32 register_size;
721 int rx_csum;
722
723 void __iomem *base;
724
725 /* rx specific fields.
726 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
727 */
728 union ring_type rx_ring;
729 unsigned int cur_rx, refill_rx;
730 struct sk_buff **rx_skbuff;
731 dma_addr_t *rx_dma;
732 unsigned int rx_buf_sz;
733 unsigned int pkt_limit;
734 struct timer_list oom_kick;
735 struct timer_list nic_poll;
736 struct timer_list stats_poll;
737 u32 nic_poll_irq;
738 int rx_ring_size;
739
740 /* media detection workaround.
741 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
742 */
743 int need_linktimer;
744 unsigned long link_timeout;
745 /*
746 * tx specific fields.
747 */
748 union ring_type tx_ring;
749 unsigned int next_tx, nic_tx;
750 struct sk_buff **tx_skbuff;
751 dma_addr_t *tx_dma;
752 unsigned int *tx_dma_len;
753 u32 tx_flags;
754 int tx_ring_size;
755 int tx_limit_start;
756 int tx_limit_stop;
757
758 /* vlan fields */
759 struct vlan_group *vlangrp;
760
761 /* msi/msi-x fields */
762 u32 msi_flags;
763 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
764
765 /* flow control */
766 u32 pause_flags;
767 };
768
769 /*
770 * Maximum number of loops until we assume that a bit in the irq mask
771 * is stuck. Overridable with module param.
772 */
773 static int max_interrupt_work = 5;
774
775 /*
776 * Optimization can be either throuput mode or cpu mode
777 *
778 * Throughput Mode: Every tx and rx packet will generate an interrupt.
779 * CPU Mode: Interrupts are controlled by a timer.
780 */
781 enum {
782 NV_OPTIMIZATION_MODE_THROUGHPUT,
783 NV_OPTIMIZATION_MODE_CPU
784 };
785 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
786
787 /*
788 * Poll interval for timer irq
789 *
790 * This interval determines how frequent an interrupt is generated.
791 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
792 * Min = 0, and Max = 65535
793 */
794 static int poll_interval = -1;
795
796 /*
797 * MSI interrupts
798 */
799 enum {
800 NV_MSI_INT_DISABLED,
801 NV_MSI_INT_ENABLED
802 };
803 static int msi = NV_MSI_INT_ENABLED;
804
805 /*
806 * MSIX interrupts
807 */
808 enum {
809 NV_MSIX_INT_DISABLED,
810 NV_MSIX_INT_ENABLED
811 };
812 static int msix = NV_MSIX_INT_ENABLED;
813
814 /*
815 * DMA 64bit
816 */
817 enum {
818 NV_DMA_64BIT_DISABLED,
819 NV_DMA_64BIT_ENABLED
820 };
821 static int dma_64bit = NV_DMA_64BIT_ENABLED;
822
823 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
824 {
825 return netdev_priv(dev);
826 }
827
828 static inline u8 __iomem *get_hwbase(struct net_device *dev)
829 {
830 return ((struct fe_priv *)netdev_priv(dev))->base;
831 }
832
833 static inline void pci_push(u8 __iomem *base)
834 {
835 /* force out pending posted writes */
836 readl(base);
837 }
838
839 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
840 {
841 return le32_to_cpu(prd->flaglen)
842 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
843 }
844
845 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
846 {
847 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
848 }
849
850 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
851 int delay, int delaymax, const char *msg)
852 {
853 u8 __iomem *base = get_hwbase(dev);
854
855 pci_push(base);
856 do {
857 udelay(delay);
858 delaymax -= delay;
859 if (delaymax < 0) {
860 if (msg)
861 printk(msg);
862 return 1;
863 }
864 } while ((readl(base + offset) & mask) != target);
865 return 0;
866 }
867
868 #define NV_SETUP_RX_RING 0x01
869 #define NV_SETUP_TX_RING 0x02
870
871 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
872 {
873 struct fe_priv *np = get_nvpriv(dev);
874 u8 __iomem *base = get_hwbase(dev);
875
876 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
877 if (rxtx_flags & NV_SETUP_RX_RING) {
878 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
879 }
880 if (rxtx_flags & NV_SETUP_TX_RING) {
881 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
882 }
883 } else {
884 if (rxtx_flags & NV_SETUP_RX_RING) {
885 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
886 writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
887 }
888 if (rxtx_flags & NV_SETUP_TX_RING) {
889 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
890 writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
891 }
892 }
893 }
894
895 static void free_rings(struct net_device *dev)
896 {
897 struct fe_priv *np = get_nvpriv(dev);
898
899 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
900 if (np->rx_ring.orig)
901 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
902 np->rx_ring.orig, np->ring_addr);
903 } else {
904 if (np->rx_ring.ex)
905 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
906 np->rx_ring.ex, np->ring_addr);
907 }
908 if (np->rx_skbuff)
909 kfree(np->rx_skbuff);
910 if (np->rx_dma)
911 kfree(np->rx_dma);
912 if (np->tx_skbuff)
913 kfree(np->tx_skbuff);
914 if (np->tx_dma)
915 kfree(np->tx_dma);
916 if (np->tx_dma_len)
917 kfree(np->tx_dma_len);
918 }
919
920 static int using_multi_irqs(struct net_device *dev)
921 {
922 struct fe_priv *np = get_nvpriv(dev);
923
924 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
925 ((np->msi_flags & NV_MSI_X_ENABLED) &&
926 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
927 return 0;
928 else
929 return 1;
930 }
931
932 static void nv_enable_irq(struct net_device *dev)
933 {
934 struct fe_priv *np = get_nvpriv(dev);
935
936 if (!using_multi_irqs(dev)) {
937 if (np->msi_flags & NV_MSI_X_ENABLED)
938 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
939 else
940 enable_irq(dev->irq);
941 } else {
942 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
943 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
944 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
945 }
946 }
947
948 static void nv_disable_irq(struct net_device *dev)
949 {
950 struct fe_priv *np = get_nvpriv(dev);
951
952 if (!using_multi_irqs(dev)) {
953 if (np->msi_flags & NV_MSI_X_ENABLED)
954 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
955 else
956 disable_irq(dev->irq);
957 } else {
958 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
959 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
960 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
961 }
962 }
963
964 /* In MSIX mode, a write to irqmask behaves as XOR */
965 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
966 {
967 u8 __iomem *base = get_hwbase(dev);
968
969 writel(mask, base + NvRegIrqMask);
970 }
971
972 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
973 {
974 struct fe_priv *np = get_nvpriv(dev);
975 u8 __iomem *base = get_hwbase(dev);
976
977 if (np->msi_flags & NV_MSI_X_ENABLED) {
978 writel(mask, base + NvRegIrqMask);
979 } else {
980 if (np->msi_flags & NV_MSI_ENABLED)
981 writel(0, base + NvRegMSIIrqMask);
982 writel(0, base + NvRegIrqMask);
983 }
984 }
985
986 #define MII_READ (-1)
987 /* mii_rw: read/write a register on the PHY.
988 *
989 * Caller must guarantee serialization
990 */
991 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
992 {
993 u8 __iomem *base = get_hwbase(dev);
994 u32 reg;
995 int retval;
996
997 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
998
999 reg = readl(base + NvRegMIIControl);
1000 if (reg & NVREG_MIICTL_INUSE) {
1001 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1002 udelay(NV_MIIBUSY_DELAY);
1003 }
1004
1005 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1006 if (value != MII_READ) {
1007 writel(value, base + NvRegMIIData);
1008 reg |= NVREG_MIICTL_WRITE;
1009 }
1010 writel(reg, base + NvRegMIIControl);
1011
1012 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1013 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1014 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1015 dev->name, miireg, addr);
1016 retval = -1;
1017 } else if (value != MII_READ) {
1018 /* it was a write operation - fewer failures are detectable */
1019 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1020 dev->name, value, miireg, addr);
1021 retval = 0;
1022 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1023 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1024 dev->name, miireg, addr);
1025 retval = -1;
1026 } else {
1027 retval = readl(base + NvRegMIIData);
1028 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1029 dev->name, miireg, addr, retval);
1030 }
1031
1032 return retval;
1033 }
1034
1035 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1036 {
1037 struct fe_priv *np = netdev_priv(dev);
1038 u32 miicontrol;
1039 unsigned int tries = 0;
1040
1041 miicontrol = BMCR_RESET | bmcr_setup;
1042 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1043 return -1;
1044 }
1045
1046 /* wait for 500ms */
1047 msleep(500);
1048
1049 /* must wait till reset is deasserted */
1050 while (miicontrol & BMCR_RESET) {
1051 msleep(10);
1052 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1053 /* FIXME: 100 tries seem excessive */
1054 if (tries++ > 100)
1055 return -1;
1056 }
1057 return 0;
1058 }
1059
1060 static int phy_init(struct net_device *dev)
1061 {
1062 struct fe_priv *np = get_nvpriv(dev);
1063 u8 __iomem *base = get_hwbase(dev);
1064 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1065
1066 /* phy errata for E3016 phy */
1067 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1068 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1069 reg &= ~PHY_MARVELL_E3016_INITMASK;
1070 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1071 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1072 return PHY_ERROR;
1073 }
1074 }
1075
1076 /* set advertise register */
1077 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1078 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1079 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1080 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1081 return PHY_ERROR;
1082 }
1083
1084 /* get phy interface type */
1085 phyinterface = readl(base + NvRegPhyInterface);
1086
1087 /* see if gigabit phy */
1088 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1089 if (mii_status & PHY_GIGABIT) {
1090 np->gigabit = PHY_GIGABIT;
1091 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1092 mii_control_1000 &= ~ADVERTISE_1000HALF;
1093 if (phyinterface & PHY_RGMII)
1094 mii_control_1000 |= ADVERTISE_1000FULL;
1095 else
1096 mii_control_1000 &= ~ADVERTISE_1000FULL;
1097
1098 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1099 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1100 return PHY_ERROR;
1101 }
1102 }
1103 else
1104 np->gigabit = 0;
1105
1106 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1107 mii_control |= BMCR_ANENABLE;
1108
1109 /* reset the phy
1110 * (certain phys need bmcr to be setup with reset)
1111 */
1112 if (phy_reset(dev, mii_control)) {
1113 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1114 return PHY_ERROR;
1115 }
1116
1117 /* phy vendor specific configuration */
1118 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1119 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1120 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1121 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1122 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1123 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1124 return PHY_ERROR;
1125 }
1126 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1127 phy_reserved |= PHY_INIT5;
1128 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1129 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1130 return PHY_ERROR;
1131 }
1132 }
1133 if (np->phy_oui == PHY_OUI_CICADA) {
1134 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1135 phy_reserved |= PHY_INIT6;
1136 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1137 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1138 return PHY_ERROR;
1139 }
1140 }
1141 /* some phys clear out pause advertisment on reset, set it back */
1142 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1143
1144 /* restart auto negotiation */
1145 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1146 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1147 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1148 return PHY_ERROR;
1149 }
1150
1151 return 0;
1152 }
1153
1154 static void nv_start_rx(struct net_device *dev)
1155 {
1156 struct fe_priv *np = netdev_priv(dev);
1157 u8 __iomem *base = get_hwbase(dev);
1158
1159 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1160 /* Already running? Stop it. */
1161 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
1162 writel(0, base + NvRegReceiverControl);
1163 pci_push(base);
1164 }
1165 writel(np->linkspeed, base + NvRegLinkSpeed);
1166 pci_push(base);
1167 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
1168 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1169 dev->name, np->duplex, np->linkspeed);
1170 pci_push(base);
1171 }
1172
1173 static void nv_stop_rx(struct net_device *dev)
1174 {
1175 u8 __iomem *base = get_hwbase(dev);
1176
1177 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1178 writel(0, base + NvRegReceiverControl);
1179 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1180 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1181 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1182
1183 udelay(NV_RXSTOP_DELAY2);
1184 writel(0, base + NvRegLinkSpeed);
1185 }
1186
1187 static void nv_start_tx(struct net_device *dev)
1188 {
1189 u8 __iomem *base = get_hwbase(dev);
1190
1191 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1192 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
1193 pci_push(base);
1194 }
1195
1196 static void nv_stop_tx(struct net_device *dev)
1197 {
1198 u8 __iomem *base = get_hwbase(dev);
1199
1200 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1201 writel(0, base + NvRegTransmitterControl);
1202 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1203 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1204 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1205
1206 udelay(NV_TXSTOP_DELAY2);
1207 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
1208 }
1209
1210 static void nv_txrx_reset(struct net_device *dev)
1211 {
1212 struct fe_priv *np = netdev_priv(dev);
1213 u8 __iomem *base = get_hwbase(dev);
1214
1215 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1216 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1217 pci_push(base);
1218 udelay(NV_TXRX_RESET_DELAY);
1219 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1220 pci_push(base);
1221 }
1222
1223 static void nv_mac_reset(struct net_device *dev)
1224 {
1225 struct fe_priv *np = netdev_priv(dev);
1226 u8 __iomem *base = get_hwbase(dev);
1227
1228 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1229 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1230 pci_push(base);
1231 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1232 pci_push(base);
1233 udelay(NV_MAC_RESET_DELAY);
1234 writel(0, base + NvRegMacReset);
1235 pci_push(base);
1236 udelay(NV_MAC_RESET_DELAY);
1237 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1238 pci_push(base);
1239 }
1240
1241 /*
1242 * nv_get_stats: dev->get_stats function
1243 * Get latest stats value from the nic.
1244 * Called with read_lock(&dev_base_lock) held for read -
1245 * only synchronized against unregister_netdevice.
1246 */
1247 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1248 {
1249 struct fe_priv *np = netdev_priv(dev);
1250
1251 /* It seems that the nic always generates interrupts and doesn't
1252 * accumulate errors internally. Thus the current values in np->stats
1253 * are already up to date.
1254 */
1255 return &np->stats;
1256 }
1257
1258 /*
1259 * nv_alloc_rx: fill rx ring entries.
1260 * Return 1 if the allocations for the skbs failed and the
1261 * rx engine is without Available descriptors
1262 */
1263 static int nv_alloc_rx(struct net_device *dev)
1264 {
1265 struct fe_priv *np = netdev_priv(dev);
1266 unsigned int refill_rx = np->refill_rx;
1267 int nr;
1268
1269 while (np->cur_rx != refill_rx) {
1270 struct sk_buff *skb;
1271
1272 nr = refill_rx % np->rx_ring_size;
1273 if (np->rx_skbuff[nr] == NULL) {
1274
1275 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1276 if (!skb)
1277 break;
1278
1279 skb->dev = dev;
1280 np->rx_skbuff[nr] = skb;
1281 } else {
1282 skb = np->rx_skbuff[nr];
1283 }
1284 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1285 skb->end-skb->data, PCI_DMA_FROMDEVICE);
1286 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1287 np->rx_ring.orig[nr].buf = cpu_to_le32(np->rx_dma[nr]);
1288 wmb();
1289 np->rx_ring.orig[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1290 } else {
1291 np->rx_ring.ex[nr].bufhigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1292 np->rx_ring.ex[nr].buflow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1293 wmb();
1294 np->rx_ring.ex[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1295 }
1296 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1297 dev->name, refill_rx);
1298 refill_rx++;
1299 }
1300 np->refill_rx = refill_rx;
1301 if (np->cur_rx - refill_rx == np->rx_ring_size)
1302 return 1;
1303 return 0;
1304 }
1305
1306 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1307 #ifdef CONFIG_FORCEDETH_NAPI
1308 static void nv_do_rx_refill(unsigned long data)
1309 {
1310 struct net_device *dev = (struct net_device *) data;
1311
1312 /* Just reschedule NAPI rx processing */
1313 netif_rx_schedule(dev);
1314 }
1315 #else
1316 static void nv_do_rx_refill(unsigned long data)
1317 {
1318 struct net_device *dev = (struct net_device *) data;
1319 struct fe_priv *np = netdev_priv(dev);
1320
1321 if (!using_multi_irqs(dev)) {
1322 if (np->msi_flags & NV_MSI_X_ENABLED)
1323 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1324 else
1325 disable_irq(dev->irq);
1326 } else {
1327 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1328 }
1329 if (nv_alloc_rx(dev)) {
1330 spin_lock_irq(&np->lock);
1331 if (!np->in_shutdown)
1332 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1333 spin_unlock_irq(&np->lock);
1334 }
1335 if (!using_multi_irqs(dev)) {
1336 if (np->msi_flags & NV_MSI_X_ENABLED)
1337 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1338 else
1339 enable_irq(dev->irq);
1340 } else {
1341 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1342 }
1343 }
1344 #endif
1345
1346 static void nv_init_rx(struct net_device *dev)
1347 {
1348 struct fe_priv *np = netdev_priv(dev);
1349 int i;
1350
1351 np->cur_rx = np->rx_ring_size;
1352 np->refill_rx = 0;
1353 for (i = 0; i < np->rx_ring_size; i++)
1354 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1355 np->rx_ring.orig[i].flaglen = 0;
1356 else
1357 np->rx_ring.ex[i].flaglen = 0;
1358 }
1359
1360 static void nv_init_tx(struct net_device *dev)
1361 {
1362 struct fe_priv *np = netdev_priv(dev);
1363 int i;
1364
1365 np->next_tx = np->nic_tx = 0;
1366 for (i = 0; i < np->tx_ring_size; i++) {
1367 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1368 np->tx_ring.orig[i].flaglen = 0;
1369 else
1370 np->tx_ring.ex[i].flaglen = 0;
1371 np->tx_skbuff[i] = NULL;
1372 np->tx_dma[i] = 0;
1373 }
1374 }
1375
1376 static int nv_init_ring(struct net_device *dev)
1377 {
1378 nv_init_tx(dev);
1379 nv_init_rx(dev);
1380 return nv_alloc_rx(dev);
1381 }
1382
1383 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1384 {
1385 struct fe_priv *np = netdev_priv(dev);
1386
1387 dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1388 dev->name, skbnr);
1389
1390 if (np->tx_dma[skbnr]) {
1391 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1392 np->tx_dma_len[skbnr],
1393 PCI_DMA_TODEVICE);
1394 np->tx_dma[skbnr] = 0;
1395 }
1396
1397 if (np->tx_skbuff[skbnr]) {
1398 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1399 np->tx_skbuff[skbnr] = NULL;
1400 return 1;
1401 } else {
1402 return 0;
1403 }
1404 }
1405
1406 static void nv_drain_tx(struct net_device *dev)
1407 {
1408 struct fe_priv *np = netdev_priv(dev);
1409 unsigned int i;
1410
1411 for (i = 0; i < np->tx_ring_size; i++) {
1412 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1413 np->tx_ring.orig[i].flaglen = 0;
1414 else
1415 np->tx_ring.ex[i].flaglen = 0;
1416 if (nv_release_txskb(dev, i))
1417 np->stats.tx_dropped++;
1418 }
1419 }
1420
1421 static void nv_drain_rx(struct net_device *dev)
1422 {
1423 struct fe_priv *np = netdev_priv(dev);
1424 int i;
1425 for (i = 0; i < np->rx_ring_size; i++) {
1426 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1427 np->rx_ring.orig[i].flaglen = 0;
1428 else
1429 np->rx_ring.ex[i].flaglen = 0;
1430 wmb();
1431 if (np->rx_skbuff[i]) {
1432 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1433 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1434 PCI_DMA_FROMDEVICE);
1435 dev_kfree_skb(np->rx_skbuff[i]);
1436 np->rx_skbuff[i] = NULL;
1437 }
1438 }
1439 }
1440
1441 static void drain_ring(struct net_device *dev)
1442 {
1443 nv_drain_tx(dev);
1444 nv_drain_rx(dev);
1445 }
1446
1447 /*
1448 * nv_start_xmit: dev->hard_start_xmit function
1449 * Called with netif_tx_lock held.
1450 */
1451 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1452 {
1453 struct fe_priv *np = netdev_priv(dev);
1454 u32 tx_flags = 0;
1455 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1456 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1457 unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1458 unsigned int start_nr = np->next_tx % np->tx_ring_size;
1459 unsigned int i;
1460 u32 offset = 0;
1461 u32 bcnt;
1462 u32 size = skb->len-skb->data_len;
1463 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1464 u32 tx_flags_vlan = 0;
1465
1466 /* add fragments to entries count */
1467 for (i = 0; i < fragments; i++) {
1468 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1469 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1470 }
1471
1472 spin_lock_irq(&np->lock);
1473
1474 if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1475 spin_unlock_irq(&np->lock);
1476 netif_stop_queue(dev);
1477 return NETDEV_TX_BUSY;
1478 }
1479
1480 /* setup the header buffer */
1481 do {
1482 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1483 nr = (nr + 1) % np->tx_ring_size;
1484
1485 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1486 PCI_DMA_TODEVICE);
1487 np->tx_dma_len[nr] = bcnt;
1488
1489 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1490 np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1491 np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1492 } else {
1493 np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1494 np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1495 np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1496 }
1497 tx_flags = np->tx_flags;
1498 offset += bcnt;
1499 size -= bcnt;
1500 } while (size);
1501
1502 /* setup the fragments */
1503 for (i = 0; i < fragments; i++) {
1504 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1505 u32 size = frag->size;
1506 offset = 0;
1507
1508 do {
1509 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1510 nr = (nr + 1) % np->tx_ring_size;
1511
1512 np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1513 PCI_DMA_TODEVICE);
1514 np->tx_dma_len[nr] = bcnt;
1515
1516 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1517 np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1518 np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1519 } else {
1520 np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1521 np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1522 np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1523 }
1524 offset += bcnt;
1525 size -= bcnt;
1526 } while (size);
1527 }
1528
1529 /* set last fragment flag */
1530 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1531 np->tx_ring.orig[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1532 } else {
1533 np->tx_ring.ex[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1534 }
1535
1536 np->tx_skbuff[nr] = skb;
1537
1538 #ifdef NETIF_F_TSO
1539 if (skb_is_gso(skb))
1540 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1541 else
1542 #endif
1543 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1544 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1545
1546 /* vlan tag */
1547 if (np->vlangrp && vlan_tx_tag_present(skb)) {
1548 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1549 }
1550
1551 /* set tx flags */
1552 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1553 np->tx_ring.orig[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1554 } else {
1555 np->tx_ring.ex[start_nr].txvlan = cpu_to_le32(tx_flags_vlan);
1556 np->tx_ring.ex[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1557 }
1558
1559 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1560 dev->name, np->next_tx, entries, tx_flags_extra);
1561 {
1562 int j;
1563 for (j=0; j<64; j++) {
1564 if ((j%16) == 0)
1565 dprintk("\n%03x:", j);
1566 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1567 }
1568 dprintk("\n");
1569 }
1570
1571 np->next_tx += entries;
1572
1573 dev->trans_start = jiffies;
1574 spin_unlock_irq(&np->lock);
1575 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1576 pci_push(get_hwbase(dev));
1577 return NETDEV_TX_OK;
1578 }
1579
1580 /*
1581 * nv_tx_done: check for completed packets, release the skbs.
1582 *
1583 * Caller must own np->lock.
1584 */
1585 static void nv_tx_done(struct net_device *dev)
1586 {
1587 struct fe_priv *np = netdev_priv(dev);
1588 u32 flags;
1589 unsigned int i;
1590 struct sk_buff *skb;
1591
1592 while (np->nic_tx != np->next_tx) {
1593 i = np->nic_tx % np->tx_ring_size;
1594
1595 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1596 flags = le32_to_cpu(np->tx_ring.orig[i].flaglen);
1597 else
1598 flags = le32_to_cpu(np->tx_ring.ex[i].flaglen);
1599
1600 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, flags 0x%x.\n",
1601 dev->name, np->nic_tx, flags);
1602 if (flags & NV_TX_VALID)
1603 break;
1604 if (np->desc_ver == DESC_VER_1) {
1605 if (flags & NV_TX_LASTPACKET) {
1606 skb = np->tx_skbuff[i];
1607 if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1608 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1609 if (flags & NV_TX_UNDERFLOW)
1610 np->stats.tx_fifo_errors++;
1611 if (flags & NV_TX_CARRIERLOST)
1612 np->stats.tx_carrier_errors++;
1613 np->stats.tx_errors++;
1614 } else {
1615 np->stats.tx_packets++;
1616 np->stats.tx_bytes += skb->len;
1617 }
1618 }
1619 } else {
1620 if (flags & NV_TX2_LASTPACKET) {
1621 skb = np->tx_skbuff[i];
1622 if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1623 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1624 if (flags & NV_TX2_UNDERFLOW)
1625 np->stats.tx_fifo_errors++;
1626 if (flags & NV_TX2_CARRIERLOST)
1627 np->stats.tx_carrier_errors++;
1628 np->stats.tx_errors++;
1629 } else {
1630 np->stats.tx_packets++;
1631 np->stats.tx_bytes += skb->len;
1632 }
1633 }
1634 }
1635 nv_release_txskb(dev, i);
1636 np->nic_tx++;
1637 }
1638 if (np->next_tx - np->nic_tx < np->tx_limit_start)
1639 netif_wake_queue(dev);
1640 }
1641
1642 /*
1643 * nv_tx_timeout: dev->tx_timeout function
1644 * Called with netif_tx_lock held.
1645 */
1646 static void nv_tx_timeout(struct net_device *dev)
1647 {
1648 struct fe_priv *np = netdev_priv(dev);
1649 u8 __iomem *base = get_hwbase(dev);
1650 u32 status;
1651
1652 if (np->msi_flags & NV_MSI_X_ENABLED)
1653 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1654 else
1655 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1656
1657 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1658
1659 {
1660 int i;
1661
1662 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1663 dev->name, (unsigned long)np->ring_addr,
1664 np->next_tx, np->nic_tx);
1665 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1666 for (i=0;i<=np->register_size;i+= 32) {
1667 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1668 i,
1669 readl(base + i + 0), readl(base + i + 4),
1670 readl(base + i + 8), readl(base + i + 12),
1671 readl(base + i + 16), readl(base + i + 20),
1672 readl(base + i + 24), readl(base + i + 28));
1673 }
1674 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1675 for (i=0;i<np->tx_ring_size;i+= 4) {
1676 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1677 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1678 i,
1679 le32_to_cpu(np->tx_ring.orig[i].buf),
1680 le32_to_cpu(np->tx_ring.orig[i].flaglen),
1681 le32_to_cpu(np->tx_ring.orig[i+1].buf),
1682 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1683 le32_to_cpu(np->tx_ring.orig[i+2].buf),
1684 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1685 le32_to_cpu(np->tx_ring.orig[i+3].buf),
1686 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1687 } else {
1688 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1689 i,
1690 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1691 le32_to_cpu(np->tx_ring.ex[i].buflow),
1692 le32_to_cpu(np->tx_ring.ex[i].flaglen),
1693 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1694 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1695 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1696 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1697 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1698 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1699 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1700 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1701 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1702 }
1703 }
1704 }
1705
1706 spin_lock_irq(&np->lock);
1707
1708 /* 1) stop tx engine */
1709 nv_stop_tx(dev);
1710
1711 /* 2) check that the packets were not sent already: */
1712 nv_tx_done(dev);
1713
1714 /* 3) if there are dead entries: clear everything */
1715 if (np->next_tx != np->nic_tx) {
1716 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1717 nv_drain_tx(dev);
1718 np->next_tx = np->nic_tx = 0;
1719 setup_hw_rings(dev, NV_SETUP_TX_RING);
1720 netif_wake_queue(dev);
1721 }
1722
1723 /* 4) restart tx engine */
1724 nv_start_tx(dev);
1725 spin_unlock_irq(&np->lock);
1726 }
1727
1728 /*
1729 * Called when the nic notices a mismatch between the actual data len on the
1730 * wire and the len indicated in the 802 header
1731 */
1732 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1733 {
1734 int hdrlen; /* length of the 802 header */
1735 int protolen; /* length as stored in the proto field */
1736
1737 /* 1) calculate len according to header */
1738 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
1739 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1740 hdrlen = VLAN_HLEN;
1741 } else {
1742 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1743 hdrlen = ETH_HLEN;
1744 }
1745 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1746 dev->name, datalen, protolen, hdrlen);
1747 if (protolen > ETH_DATA_LEN)
1748 return datalen; /* Value in proto field not a len, no checks possible */
1749
1750 protolen += hdrlen;
1751 /* consistency checks: */
1752 if (datalen > ETH_ZLEN) {
1753 if (datalen >= protolen) {
1754 /* more data on wire than in 802 header, trim of
1755 * additional data.
1756 */
1757 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1758 dev->name, protolen);
1759 return protolen;
1760 } else {
1761 /* less data on wire than mentioned in header.
1762 * Discard the packet.
1763 */
1764 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1765 dev->name);
1766 return -1;
1767 }
1768 } else {
1769 /* short packet. Accept only if 802 values are also short */
1770 if (protolen > ETH_ZLEN) {
1771 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1772 dev->name);
1773 return -1;
1774 }
1775 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1776 dev->name, datalen);
1777 return datalen;
1778 }
1779 }
1780
1781 static int nv_rx_process(struct net_device *dev, int limit)
1782 {
1783 struct fe_priv *np = netdev_priv(dev);
1784 u32 flags;
1785 u32 vlanflags = 0;
1786 int count;
1787
1788 for (count = 0; count < limit; ++count) {
1789 struct sk_buff *skb;
1790 int len;
1791 int i;
1792 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1793 break; /* we scanned the whole ring - do not continue */
1794
1795 i = np->cur_rx % np->rx_ring_size;
1796 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1797 flags = le32_to_cpu(np->rx_ring.orig[i].flaglen);
1798 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1799 } else {
1800 flags = le32_to_cpu(np->rx_ring.ex[i].flaglen);
1801 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1802 vlanflags = le32_to_cpu(np->rx_ring.ex[i].buflow);
1803 }
1804
1805 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, flags 0x%x.\n",
1806 dev->name, np->cur_rx, flags);
1807
1808 if (flags & NV_RX_AVAIL)
1809 break; /* still owned by hardware, */
1810
1811 /*
1812 * the packet is for us - immediately tear down the pci mapping.
1813 * TODO: check if a prefetch of the first cacheline improves
1814 * the performance.
1815 */
1816 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1817 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1818 PCI_DMA_FROMDEVICE);
1819
1820 {
1821 int j;
1822 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
1823 for (j=0; j<64; j++) {
1824 if ((j%16) == 0)
1825 dprintk("\n%03x:", j);
1826 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1827 }
1828 dprintk("\n");
1829 }
1830 /* look at what we actually got: */
1831 if (np->desc_ver == DESC_VER_1) {
1832 if (!(flags & NV_RX_DESCRIPTORVALID))
1833 goto next_pkt;
1834
1835 if (flags & NV_RX_ERROR) {
1836 if (flags & NV_RX_MISSEDFRAME) {
1837 np->stats.rx_missed_errors++;
1838 np->stats.rx_errors++;
1839 goto next_pkt;
1840 }
1841 if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1842 np->stats.rx_errors++;
1843 goto next_pkt;
1844 }
1845 if (flags & NV_RX_CRCERR) {
1846 np->stats.rx_crc_errors++;
1847 np->stats.rx_errors++;
1848 goto next_pkt;
1849 }
1850 if (flags & NV_RX_OVERFLOW) {
1851 np->stats.rx_over_errors++;
1852 np->stats.rx_errors++;
1853 goto next_pkt;
1854 }
1855 if (flags & NV_RX_ERROR4) {
1856 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1857 if (len < 0) {
1858 np->stats.rx_errors++;
1859 goto next_pkt;
1860 }
1861 }
1862 /* framing errors are soft errors. */
1863 if (flags & NV_RX_FRAMINGERR) {
1864 if (flags & NV_RX_SUBSTRACT1) {
1865 len--;
1866 }
1867 }
1868 }
1869 } else {
1870 if (!(flags & NV_RX2_DESCRIPTORVALID))
1871 goto next_pkt;
1872
1873 if (flags & NV_RX2_ERROR) {
1874 if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1875 np->stats.rx_errors++;
1876 goto next_pkt;
1877 }
1878 if (flags & NV_RX2_CRCERR) {
1879 np->stats.rx_crc_errors++;
1880 np->stats.rx_errors++;
1881 goto next_pkt;
1882 }
1883 if (flags & NV_RX2_OVERFLOW) {
1884 np->stats.rx_over_errors++;
1885 np->stats.rx_errors++;
1886 goto next_pkt;
1887 }
1888 if (flags & NV_RX2_ERROR4) {
1889 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1890 if (len < 0) {
1891 np->stats.rx_errors++;
1892 goto next_pkt;
1893 }
1894 }
1895 /* framing errors are soft errors */
1896 if (flags & NV_RX2_FRAMINGERR) {
1897 if (flags & NV_RX2_SUBSTRACT1) {
1898 len--;
1899 }
1900 }
1901 }
1902 if (np->rx_csum) {
1903 flags &= NV_RX2_CHECKSUMMASK;
1904 if (flags == NV_RX2_CHECKSUMOK1 ||
1905 flags == NV_RX2_CHECKSUMOK2 ||
1906 flags == NV_RX2_CHECKSUMOK3) {
1907 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1908 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1909 } else {
1910 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1911 }
1912 }
1913 }
1914 /* got a valid packet - forward it to the network core */
1915 skb = np->rx_skbuff[i];
1916 np->rx_skbuff[i] = NULL;
1917
1918 skb_put(skb, len);
1919 skb->protocol = eth_type_trans(skb, dev);
1920 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1921 dev->name, np->cur_rx, len, skb->protocol);
1922 #ifdef CONFIG_FORCEDETH_NAPI
1923 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1924 vlan_hwaccel_receive_skb(skb, np->vlangrp,
1925 vlanflags & NV_RX3_VLAN_TAG_MASK);
1926 else
1927 netif_receive_skb(skb);
1928 #else
1929 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1930 vlan_hwaccel_rx(skb, np->vlangrp,
1931 vlanflags & NV_RX3_VLAN_TAG_MASK);
1932 else
1933 netif_rx(skb);
1934 #endif
1935 dev->last_rx = jiffies;
1936 np->stats.rx_packets++;
1937 np->stats.rx_bytes += len;
1938 next_pkt:
1939 np->cur_rx++;
1940 }
1941
1942 return count;
1943 }
1944
1945 static void set_bufsize(struct net_device *dev)
1946 {
1947 struct fe_priv *np = netdev_priv(dev);
1948
1949 if (dev->mtu <= ETH_DATA_LEN)
1950 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1951 else
1952 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1953 }
1954
1955 /*
1956 * nv_change_mtu: dev->change_mtu function
1957 * Called with dev_base_lock held for read.
1958 */
1959 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1960 {
1961 struct fe_priv *np = netdev_priv(dev);
1962 int old_mtu;
1963
1964 if (new_mtu < 64 || new_mtu > np->pkt_limit)
1965 return -EINVAL;
1966
1967 old_mtu = dev->mtu;
1968 dev->mtu = new_mtu;
1969
1970 /* return early if the buffer sizes will not change */
1971 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1972 return 0;
1973 if (old_mtu == new_mtu)
1974 return 0;
1975
1976 /* synchronized against open : rtnl_lock() held by caller */
1977 if (netif_running(dev)) {
1978 u8 __iomem *base = get_hwbase(dev);
1979 /*
1980 * It seems that the nic preloads valid ring entries into an
1981 * internal buffer. The procedure for flushing everything is
1982 * guessed, there is probably a simpler approach.
1983 * Changing the MTU is a rare event, it shouldn't matter.
1984 */
1985 nv_disable_irq(dev);
1986 netif_tx_lock_bh(dev);
1987 spin_lock(&np->lock);
1988 /* stop engines */
1989 nv_stop_rx(dev);
1990 nv_stop_tx(dev);
1991 nv_txrx_reset(dev);
1992 /* drain rx queue */
1993 nv_drain_rx(dev);
1994 nv_drain_tx(dev);
1995 /* reinit driver view of the rx queue */
1996 set_bufsize(dev);
1997 if (nv_init_ring(dev)) {
1998 if (!np->in_shutdown)
1999 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2000 }
2001 /* reinit nic view of the rx queue */
2002 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2003 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2004 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2005 base + NvRegRingSizes);
2006 pci_push(base);
2007 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2008 pci_push(base);
2009
2010 /* restart rx engine */
2011 nv_start_rx(dev);
2012 nv_start_tx(dev);
2013 spin_unlock(&np->lock);
2014 netif_tx_unlock_bh(dev);
2015 nv_enable_irq(dev);
2016 }
2017 return 0;
2018 }
2019
2020 static void nv_copy_mac_to_hw(struct net_device *dev)
2021 {
2022 u8 __iomem *base = get_hwbase(dev);
2023 u32 mac[2];
2024
2025 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2026 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2027 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2028
2029 writel(mac[0], base + NvRegMacAddrA);
2030 writel(mac[1], base + NvRegMacAddrB);
2031 }
2032
2033 /*
2034 * nv_set_mac_address: dev->set_mac_address function
2035 * Called with rtnl_lock() held.
2036 */
2037 static int nv_set_mac_address(struct net_device *dev, void *addr)
2038 {
2039 struct fe_priv *np = netdev_priv(dev);
2040 struct sockaddr *macaddr = (struct sockaddr*)addr;
2041
2042 if (!is_valid_ether_addr(macaddr->sa_data))
2043 return -EADDRNOTAVAIL;
2044
2045 /* synchronized against open : rtnl_lock() held by caller */
2046 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2047
2048 if (netif_running(dev)) {
2049 netif_tx_lock_bh(dev);
2050 spin_lock_irq(&np->lock);
2051
2052 /* stop rx engine */
2053 nv_stop_rx(dev);
2054
2055 /* set mac address */
2056 nv_copy_mac_to_hw(dev);
2057
2058 /* restart rx engine */
2059 nv_start_rx(dev);
2060 spin_unlock_irq(&np->lock);
2061 netif_tx_unlock_bh(dev);
2062 } else {
2063 nv_copy_mac_to_hw(dev);
2064 }
2065 return 0;
2066 }
2067
2068 /*
2069 * nv_set_multicast: dev->set_multicast function
2070 * Called with netif_tx_lock held.
2071 */
2072 static void nv_set_multicast(struct net_device *dev)
2073 {
2074 struct fe_priv *np = netdev_priv(dev);
2075 u8 __iomem *base = get_hwbase(dev);
2076 u32 addr[2];
2077 u32 mask[2];
2078 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2079
2080 memset(addr, 0, sizeof(addr));
2081 memset(mask, 0, sizeof(mask));
2082
2083 if (dev->flags & IFF_PROMISC) {
2084 pff |= NVREG_PFF_PROMISC;
2085 } else {
2086 pff |= NVREG_PFF_MYADDR;
2087
2088 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2089 u32 alwaysOff[2];
2090 u32 alwaysOn[2];
2091
2092 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2093 if (dev->flags & IFF_ALLMULTI) {
2094 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2095 } else {
2096 struct dev_mc_list *walk;
2097
2098 walk = dev->mc_list;
2099 while (walk != NULL) {
2100 u32 a, b;
2101 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2102 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2103 alwaysOn[0] &= a;
2104 alwaysOff[0] &= ~a;
2105 alwaysOn[1] &= b;
2106 alwaysOff[1] &= ~b;
2107 walk = walk->next;
2108 }
2109 }
2110 addr[0] = alwaysOn[0];
2111 addr[1] = alwaysOn[1];
2112 mask[0] = alwaysOn[0] | alwaysOff[0];
2113 mask[1] = alwaysOn[1] | alwaysOff[1];
2114 }
2115 }
2116 addr[0] |= NVREG_MCASTADDRA_FORCE;
2117 pff |= NVREG_PFF_ALWAYS;
2118 spin_lock_irq(&np->lock);
2119 nv_stop_rx(dev);
2120 writel(addr[0], base + NvRegMulticastAddrA);
2121 writel(addr[1], base + NvRegMulticastAddrB);
2122 writel(mask[0], base + NvRegMulticastMaskA);
2123 writel(mask[1], base + NvRegMulticastMaskB);
2124 writel(pff, base + NvRegPacketFilterFlags);
2125 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2126 dev->name);
2127 nv_start_rx(dev);
2128 spin_unlock_irq(&np->lock);
2129 }
2130
2131 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2132 {
2133 struct fe_priv *np = netdev_priv(dev);
2134 u8 __iomem *base = get_hwbase(dev);
2135
2136 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2137
2138 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2139 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2140 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2141 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2142 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2143 } else {
2144 writel(pff, base + NvRegPacketFilterFlags);
2145 }
2146 }
2147 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2148 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2149 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2150 writel(NVREG_TX_PAUSEFRAME_ENABLE, base + NvRegTxPauseFrame);
2151 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2152 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2153 } else {
2154 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
2155 writel(regmisc, base + NvRegMisc1);
2156 }
2157 }
2158 }
2159
2160 /**
2161 * nv_update_linkspeed: Setup the MAC according to the link partner
2162 * @dev: Network device to be configured
2163 *
2164 * The function queries the PHY and checks if there is a link partner.
2165 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2166 * set to 10 MBit HD.
2167 *
2168 * The function returns 0 if there is no link partner and 1 if there is
2169 * a good link partner.
2170 */
2171 static int nv_update_linkspeed(struct net_device *dev)
2172 {
2173 struct fe_priv *np = netdev_priv(dev);
2174 u8 __iomem *base = get_hwbase(dev);
2175 int adv = 0;
2176 int lpa = 0;
2177 int adv_lpa, adv_pause, lpa_pause;
2178 int newls = np->linkspeed;
2179 int newdup = np->duplex;
2180 int mii_status;
2181 int retval = 0;
2182 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2183
2184 /* BMSR_LSTATUS is latched, read it twice:
2185 * we want the current value.
2186 */
2187 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2188 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2189
2190 if (!(mii_status & BMSR_LSTATUS)) {
2191 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2192 dev->name);
2193 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2194 newdup = 0;
2195 retval = 0;
2196 goto set_speed;
2197 }
2198
2199 if (np->autoneg == 0) {
2200 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2201 dev->name, np->fixed_mode);
2202 if (np->fixed_mode & LPA_100FULL) {
2203 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2204 newdup = 1;
2205 } else if (np->fixed_mode & LPA_100HALF) {
2206 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2207 newdup = 0;
2208 } else if (np->fixed_mode & LPA_10FULL) {
2209 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2210 newdup = 1;
2211 } else {
2212 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2213 newdup = 0;
2214 }
2215 retval = 1;
2216 goto set_speed;
2217 }
2218 /* check auto negotiation is complete */
2219 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2220 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2221 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2222 newdup = 0;
2223 retval = 0;
2224 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2225 goto set_speed;
2226 }
2227
2228 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2229 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2230 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2231 dev->name, adv, lpa);
2232
2233 retval = 1;
2234 if (np->gigabit == PHY_GIGABIT) {
2235 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2236 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2237
2238 if ((control_1000 & ADVERTISE_1000FULL) &&
2239 (status_1000 & LPA_1000FULL)) {
2240 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2241 dev->name);
2242 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2243 newdup = 1;
2244 goto set_speed;
2245 }
2246 }
2247
2248 /* FIXME: handle parallel detection properly */
2249 adv_lpa = lpa & adv;
2250 if (adv_lpa & LPA_100FULL) {
2251 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2252 newdup = 1;
2253 } else if (adv_lpa & LPA_100HALF) {
2254 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2255 newdup = 0;
2256 } else if (adv_lpa & LPA_10FULL) {
2257 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2258 newdup = 1;
2259 } else if (adv_lpa & LPA_10HALF) {
2260 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2261 newdup = 0;
2262 } else {
2263 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2264 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2265 newdup = 0;
2266 }
2267
2268 set_speed:
2269 if (np->duplex == newdup && np->linkspeed == newls)
2270 return retval;
2271
2272 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2273 dev->name, np->linkspeed, np->duplex, newls, newdup);
2274
2275 np->duplex = newdup;
2276 np->linkspeed = newls;
2277
2278 if (np->gigabit == PHY_GIGABIT) {
2279 phyreg = readl(base + NvRegRandomSeed);
2280 phyreg &= ~(0x3FF00);
2281 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2282 phyreg |= NVREG_RNDSEED_FORCE3;
2283 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2284 phyreg |= NVREG_RNDSEED_FORCE2;
2285 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2286 phyreg |= NVREG_RNDSEED_FORCE;
2287 writel(phyreg, base + NvRegRandomSeed);
2288 }
2289
2290 phyreg = readl(base + NvRegPhyInterface);
2291 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2292 if (np->duplex == 0)
2293 phyreg |= PHY_HALF;
2294 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2295 phyreg |= PHY_100;
2296 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2297 phyreg |= PHY_1000;
2298 writel(phyreg, base + NvRegPhyInterface);
2299
2300 if (phyreg & PHY_RGMII) {
2301 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2302 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2303 else
2304 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2305 } else {
2306 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2307 }
2308 writel(txreg, base + NvRegTxDeferral);
2309
2310 if (np->desc_ver == DESC_VER_1) {
2311 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2312 } else {
2313 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2314 txreg = NVREG_TX_WM_DESC2_3_1000;
2315 else
2316 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2317 }
2318 writel(txreg, base + NvRegTxWatermark);
2319
2320 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2321 base + NvRegMisc1);
2322 pci_push(base);
2323 writel(np->linkspeed, base + NvRegLinkSpeed);
2324 pci_push(base);
2325
2326 pause_flags = 0;
2327 /* setup pause frame */
2328 if (np->duplex != 0) {
2329 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2330 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2331 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2332
2333 switch (adv_pause) {
2334 case ADVERTISE_PAUSE_CAP:
2335 if (lpa_pause & LPA_PAUSE_CAP) {
2336 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2337 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2338 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2339 }
2340 break;
2341 case ADVERTISE_PAUSE_ASYM:
2342 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2343 {
2344 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2345 }
2346 break;
2347 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2348 if (lpa_pause & LPA_PAUSE_CAP)
2349 {
2350 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2351 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2352 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2353 }
2354 if (lpa_pause == LPA_PAUSE_ASYM)
2355 {
2356 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2357 }
2358 break;
2359 }
2360 } else {
2361 pause_flags = np->pause_flags;
2362 }
2363 }
2364 nv_update_pause(dev, pause_flags);
2365
2366 return retval;
2367 }
2368
2369 static void nv_linkchange(struct net_device *dev)
2370 {
2371 if (nv_update_linkspeed(dev)) {
2372 if (!netif_carrier_ok(dev)) {
2373 netif_carrier_on(dev);
2374 printk(KERN_INFO "%s: link up.\n", dev->name);
2375 nv_start_rx(dev);
2376 }
2377 } else {
2378 if (netif_carrier_ok(dev)) {
2379 netif_carrier_off(dev);
2380 printk(KERN_INFO "%s: link down.\n", dev->name);
2381 nv_stop_rx(dev);
2382 }
2383 }
2384 }
2385
2386 static void nv_link_irq(struct net_device *dev)
2387 {
2388 u8 __iomem *base = get_hwbase(dev);
2389 u32 miistat;
2390
2391 miistat = readl(base + NvRegMIIStatus);
2392 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2393 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2394
2395 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2396 nv_linkchange(dev);
2397 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2398 }
2399
2400 static irqreturn_t nv_nic_irq(int foo, void *data)
2401 {
2402 struct net_device *dev = (struct net_device *) data;
2403 struct fe_priv *np = netdev_priv(dev);
2404 u8 __iomem *base = get_hwbase(dev);
2405 u32 events;
2406 int i;
2407
2408 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2409
2410 for (i=0; ; i++) {
2411 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2412 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2413 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2414 } else {
2415 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2416 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2417 }
2418 pci_push(base);
2419 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2420 if (!(events & np->irqmask))
2421 break;
2422
2423 spin_lock(&np->lock);
2424 nv_tx_done(dev);
2425 spin_unlock(&np->lock);
2426
2427 if (events & NVREG_IRQ_LINK) {
2428 spin_lock(&np->lock);
2429 nv_link_irq(dev);
2430 spin_unlock(&np->lock);
2431 }
2432 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2433 spin_lock(&np->lock);
2434 nv_linkchange(dev);
2435 spin_unlock(&np->lock);
2436 np->link_timeout = jiffies + LINK_TIMEOUT;
2437 }
2438 if (events & (NVREG_IRQ_TX_ERR)) {
2439 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2440 dev->name, events);
2441 }
2442 if (events & (NVREG_IRQ_UNKNOWN)) {
2443 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2444 dev->name, events);
2445 }
2446 #ifdef CONFIG_FORCEDETH_NAPI
2447 if (events & NVREG_IRQ_RX_ALL) {
2448 netif_rx_schedule(dev);
2449
2450 /* Disable furthur receive irq's */
2451 spin_lock(&np->lock);
2452 np->irqmask &= ~NVREG_IRQ_RX_ALL;
2453
2454 if (np->msi_flags & NV_MSI_X_ENABLED)
2455 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2456 else
2457 writel(np->irqmask, base + NvRegIrqMask);
2458 spin_unlock(&np->lock);
2459 }
2460 #else
2461 nv_rx_process(dev, dev->weight);
2462 if (nv_alloc_rx(dev)) {
2463 spin_lock(&np->lock);
2464 if (!np->in_shutdown)
2465 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2466 spin_unlock(&np->lock);
2467 }
2468 #endif
2469 if (i > max_interrupt_work) {
2470 spin_lock(&np->lock);
2471 /* disable interrupts on the nic */
2472 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2473 writel(0, base + NvRegIrqMask);
2474 else
2475 writel(np->irqmask, base + NvRegIrqMask);
2476 pci_push(base);
2477
2478 if (!np->in_shutdown) {
2479 np->nic_poll_irq = np->irqmask;
2480 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2481 }
2482 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2483 spin_unlock(&np->lock);
2484 break;
2485 }
2486
2487 }
2488 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2489
2490 return IRQ_RETVAL(i);
2491 }
2492
2493 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
2494 {
2495 struct net_device *dev = (struct net_device *) data;
2496 struct fe_priv *np = netdev_priv(dev);
2497 u8 __iomem *base = get_hwbase(dev);
2498 u32 events;
2499 int i;
2500 unsigned long flags;
2501
2502 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2503
2504 for (i=0; ; i++) {
2505 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2506 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2507 pci_push(base);
2508 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2509 if (!(events & np->irqmask))
2510 break;
2511
2512 spin_lock_irqsave(&np->lock, flags);
2513 nv_tx_done(dev);
2514 spin_unlock_irqrestore(&np->lock, flags);
2515
2516 if (events & (NVREG_IRQ_TX_ERR)) {
2517 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2518 dev->name, events);
2519 }
2520 if (i > max_interrupt_work) {
2521 spin_lock_irqsave(&np->lock, flags);
2522 /* disable interrupts on the nic */
2523 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2524 pci_push(base);
2525
2526 if (!np->in_shutdown) {
2527 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2528 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2529 }
2530 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2531 spin_unlock_irqrestore(&np->lock, flags);
2532 break;
2533 }
2534
2535 }
2536 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2537
2538 return IRQ_RETVAL(i);
2539 }
2540
2541 #ifdef CONFIG_FORCEDETH_NAPI
2542 static int nv_napi_poll(struct net_device *dev, int *budget)
2543 {
2544 int pkts, limit = min(*budget, dev->quota);
2545 struct fe_priv *np = netdev_priv(dev);
2546 u8 __iomem *base = get_hwbase(dev);
2547
2548 pkts = nv_rx_process(dev, limit);
2549
2550 if (nv_alloc_rx(dev)) {
2551 spin_lock_irq(&np->lock);
2552 if (!np->in_shutdown)
2553 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2554 spin_unlock_irq(&np->lock);
2555 }
2556
2557 if (pkts < limit) {
2558 /* all done, no more packets present */
2559 netif_rx_complete(dev);
2560
2561 /* re-enable receive interrupts */
2562 spin_lock_irq(&np->lock);
2563 np->irqmask |= NVREG_IRQ_RX_ALL;
2564 if (np->msi_flags & NV_MSI_X_ENABLED)
2565 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2566 else
2567 writel(np->irqmask, base + NvRegIrqMask);
2568 spin_unlock_irq(&np->lock);
2569 return 0;
2570 } else {
2571 /* used up our quantum, so reschedule */
2572 dev->quota -= pkts;
2573 *budget -= pkts;
2574 return 1;
2575 }
2576 }
2577 #endif
2578
2579 #ifdef CONFIG_FORCEDETH_NAPI
2580 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2581 {
2582 struct net_device *dev = (struct net_device *) data;
2583 u8 __iomem *base = get_hwbase(dev);
2584 u32 events;
2585
2586 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2587 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2588
2589 if (events) {
2590 netif_rx_schedule(dev);
2591 /* disable receive interrupts on the nic */
2592 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2593 pci_push(base);
2594 }
2595 return IRQ_HANDLED;
2596 }
2597 #else
2598 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2599 {
2600 struct net_device *dev = (struct net_device *) data;
2601 struct fe_priv *np = netdev_priv(dev);
2602 u8 __iomem *base = get_hwbase(dev);
2603 u32 events;
2604 int i;
2605 unsigned long flags;
2606
2607 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2608
2609 for (i=0; ; i++) {
2610 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2611 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2612 pci_push(base);
2613 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2614 if (!(events & np->irqmask))
2615 break;
2616
2617 nv_rx_process(dev, dev->weight);
2618 if (nv_alloc_rx(dev)) {
2619 spin_lock_irqsave(&np->lock, flags);
2620 if (!np->in_shutdown)
2621 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2622 spin_unlock_irqrestore(&np->lock, flags);
2623 }
2624
2625 if (i > max_interrupt_work) {
2626 spin_lock_irqsave(&np->lock, flags);
2627 /* disable interrupts on the nic */
2628 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2629 pci_push(base);
2630
2631 if (!np->in_shutdown) {
2632 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2633 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2634 }
2635 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2636 spin_unlock_irqrestore(&np->lock, flags);
2637 break;
2638 }
2639 }
2640 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2641
2642 return IRQ_RETVAL(i);
2643 }
2644 #endif
2645
2646 static irqreturn_t nv_nic_irq_other(int foo, void *data)
2647 {
2648 struct net_device *dev = (struct net_device *) data;
2649 struct fe_priv *np = netdev_priv(dev);
2650 u8 __iomem *base = get_hwbase(dev);
2651 u32 events;
2652 int i;
2653 unsigned long flags;
2654
2655 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2656
2657 for (i=0; ; i++) {
2658 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2659 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2660 pci_push(base);
2661 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2662 if (!(events & np->irqmask))
2663 break;
2664
2665 if (events & NVREG_IRQ_LINK) {
2666 spin_lock_irqsave(&np->lock, flags);
2667 nv_link_irq(dev);
2668 spin_unlock_irqrestore(&np->lock, flags);
2669 }
2670 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2671 spin_lock_irqsave(&np->lock, flags);
2672 nv_linkchange(dev);
2673 spin_unlock_irqrestore(&np->lock, flags);
2674 np->link_timeout = jiffies + LINK_TIMEOUT;
2675 }
2676 if (events & (NVREG_IRQ_UNKNOWN)) {
2677 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2678 dev->name, events);
2679 }
2680 if (i > max_interrupt_work) {
2681 spin_lock_irqsave(&np->lock, flags);
2682 /* disable interrupts on the nic */
2683 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2684 pci_push(base);
2685
2686 if (!np->in_shutdown) {
2687 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2688 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2689 }
2690 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2691 spin_unlock_irqrestore(&np->lock, flags);
2692 break;
2693 }
2694
2695 }
2696 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2697
2698 return IRQ_RETVAL(i);
2699 }
2700
2701 static irqreturn_t nv_nic_irq_test(int foo, void *data)
2702 {
2703 struct net_device *dev = (struct net_device *) data;
2704 struct fe_priv *np = netdev_priv(dev);
2705 u8 __iomem *base = get_hwbase(dev);
2706 u32 events;
2707
2708 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2709
2710 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2711 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2712 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2713 } else {
2714 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2715 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2716 }
2717 pci_push(base);
2718 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2719 if (!(events & NVREG_IRQ_TIMER))
2720 return IRQ_RETVAL(0);
2721
2722 spin_lock(&np->lock);
2723 np->intr_test = 1;
2724 spin_unlock(&np->lock);
2725
2726 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2727
2728 return IRQ_RETVAL(1);
2729 }
2730
2731 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2732 {
2733 u8 __iomem *base = get_hwbase(dev);
2734 int i;
2735 u32 msixmap = 0;
2736
2737 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2738 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2739 * the remaining 8 interrupts.
2740 */
2741 for (i = 0; i < 8; i++) {
2742 if ((irqmask >> i) & 0x1) {
2743 msixmap |= vector << (i << 2);
2744 }
2745 }
2746 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2747
2748 msixmap = 0;
2749 for (i = 0; i < 8; i++) {
2750 if ((irqmask >> (i + 8)) & 0x1) {
2751 msixmap |= vector << (i << 2);
2752 }
2753 }
2754 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2755 }
2756
2757 static int nv_request_irq(struct net_device *dev, int intr_test)
2758 {
2759 struct fe_priv *np = get_nvpriv(dev);
2760 u8 __iomem *base = get_hwbase(dev);
2761 int ret = 1;
2762 int i;
2763
2764 if (np->msi_flags & NV_MSI_X_CAPABLE) {
2765 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2766 np->msi_x_entry[i].entry = i;
2767 }
2768 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2769 np->msi_flags |= NV_MSI_X_ENABLED;
2770 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2771 /* Request irq for rx handling */
2772 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2773 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2774 pci_disable_msix(np->pci_dev);
2775 np->msi_flags &= ~NV_MSI_X_ENABLED;
2776 goto out_err;
2777 }
2778 /* Request irq for tx handling */
2779 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2780 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2781 pci_disable_msix(np->pci_dev);
2782 np->msi_flags &= ~NV_MSI_X_ENABLED;
2783 goto out_free_rx;
2784 }
2785 /* Request irq for link and timer handling */
2786 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2787 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2788 pci_disable_msix(np->pci_dev);
2789 np->msi_flags &= ~NV_MSI_X_ENABLED;
2790 goto out_free_tx;
2791 }
2792 /* map interrupts to their respective vector */
2793 writel(0, base + NvRegMSIXMap0);
2794 writel(0, base + NvRegMSIXMap1);
2795 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2796 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2797 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2798 } else {
2799 /* Request irq for all interrupts */
2800 if ((!intr_test &&
2801 request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2802 (intr_test &&
2803 request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2804 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2805 pci_disable_msix(np->pci_dev);
2806 np->msi_flags &= ~NV_MSI_X_ENABLED;
2807 goto out_err;
2808 }
2809
2810 /* map interrupts to vector 0 */
2811 writel(0, base + NvRegMSIXMap0);
2812 writel(0, base + NvRegMSIXMap1);
2813 }
2814 }
2815 }
2816 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2817 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2818 np->msi_flags |= NV_MSI_ENABLED;
2819 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2820 (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2821 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2822 pci_disable_msi(np->pci_dev);
2823 np->msi_flags &= ~NV_MSI_ENABLED;
2824 goto out_err;
2825 }
2826
2827 /* map interrupts to vector 0 */
2828 writel(0, base + NvRegMSIMap0);
2829 writel(0, base + NvRegMSIMap1);
2830 /* enable msi vector 0 */
2831 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2832 }
2833 }
2834 if (ret != 0) {
2835 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2836 (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
2837 goto out_err;
2838
2839 }
2840
2841 return 0;
2842 out_free_tx:
2843 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2844 out_free_rx:
2845 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
2846 out_err:
2847 return 1;
2848 }
2849
2850 static void nv_free_irq(struct net_device *dev)
2851 {
2852 struct fe_priv *np = get_nvpriv(dev);
2853 int i;
2854
2855 if (np->msi_flags & NV_MSI_X_ENABLED) {
2856 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2857 free_irq(np->msi_x_entry[i].vector, dev);
2858 }
2859 pci_disable_msix(np->pci_dev);
2860 np->msi_flags &= ~NV_MSI_X_ENABLED;
2861 } else {
2862 free_irq(np->pci_dev->irq, dev);
2863 if (np->msi_flags & NV_MSI_ENABLED) {
2864 pci_disable_msi(np->pci_dev);
2865 np->msi_flags &= ~NV_MSI_ENABLED;
2866 }
2867 }
2868 }
2869
2870 static void nv_do_nic_poll(unsigned long data)
2871 {
2872 struct net_device *dev = (struct net_device *) data;
2873 struct fe_priv *np = netdev_priv(dev);
2874 u8 __iomem *base = get_hwbase(dev);
2875 u32 mask = 0;
2876
2877 /*
2878 * First disable irq(s) and then
2879 * reenable interrupts on the nic, we have to do this before calling
2880 * nv_nic_irq because that may decide to do otherwise
2881 */
2882
2883 if (!using_multi_irqs(dev)) {
2884 if (np->msi_flags & NV_MSI_X_ENABLED)
2885 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2886 else
2887 disable_irq_lockdep(dev->irq);
2888 mask = np->irqmask;
2889 } else {
2890 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2891 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2892 mask |= NVREG_IRQ_RX_ALL;
2893 }
2894 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2895 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2896 mask |= NVREG_IRQ_TX_ALL;
2897 }
2898 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2899 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2900 mask |= NVREG_IRQ_OTHER;
2901 }
2902 }
2903 np->nic_poll_irq = 0;
2904
2905 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2906
2907 writel(mask, base + NvRegIrqMask);
2908 pci_push(base);
2909
2910 if (!using_multi_irqs(dev)) {
2911 nv_nic_irq(0, dev);
2912 if (np->msi_flags & NV_MSI_X_ENABLED)
2913 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2914 else
2915 enable_irq_lockdep(dev->irq);
2916 } else {
2917 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2918 nv_nic_irq_rx(0, dev);
2919 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2920 }
2921 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2922 nv_nic_irq_tx(0, dev);
2923 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2924 }
2925 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2926 nv_nic_irq_other(0, dev);
2927 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2928 }
2929 }
2930 }
2931
2932 #ifdef CONFIG_NET_POLL_CONTROLLER
2933 static void nv_poll_controller(struct net_device *dev)
2934 {
2935 nv_do_nic_poll((unsigned long) dev);
2936 }
2937 #endif
2938
2939 static void nv_do_stats_poll(unsigned long data)
2940 {
2941 struct net_device *dev = (struct net_device *) data;
2942 struct fe_priv *np = netdev_priv(dev);
2943 u8 __iomem *base = get_hwbase(dev);
2944
2945 np->estats.tx_bytes += readl(base + NvRegTxCnt);
2946 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
2947 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
2948 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
2949 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
2950 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
2951 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
2952 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
2953 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
2954 np->estats.tx_deferral += readl(base + NvRegTxDef);
2955 np->estats.tx_packets += readl(base + NvRegTxFrame);
2956 np->estats.tx_pause += readl(base + NvRegTxPause);
2957 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
2958 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
2959 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
2960 np->estats.rx_runt += readl(base + NvRegRxRunt);
2961 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
2962 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
2963 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
2964 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
2965 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
2966 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
2967 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
2968 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
2969 np->estats.rx_bytes += readl(base + NvRegRxCnt);
2970 np->estats.rx_pause += readl(base + NvRegRxPause);
2971 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
2972 np->estats.rx_packets =
2973 np->estats.rx_unicast +
2974 np->estats.rx_multicast +
2975 np->estats.rx_broadcast;
2976 np->estats.rx_errors_total =
2977 np->estats.rx_crc_errors +
2978 np->estats.rx_over_errors +
2979 np->estats.rx_frame_error +
2980 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
2981 np->estats.rx_late_collision +
2982 np->estats.rx_runt +
2983 np->estats.rx_frame_too_long;
2984
2985 if (!np->in_shutdown)
2986 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
2987 }
2988
2989 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2990 {
2991 struct fe_priv *np = netdev_priv(dev);
2992 strcpy(info->driver, "forcedeth");
2993 strcpy(info->version, FORCEDETH_VERSION);
2994 strcpy(info->bus_info, pci_name(np->pci_dev));
2995 }
2996
2997 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2998 {
2999 struct fe_priv *np = netdev_priv(dev);
3000 wolinfo->supported = WAKE_MAGIC;
3001
3002 spin_lock_irq(&np->lock);
3003 if (np->wolenabled)
3004 wolinfo->wolopts = WAKE_MAGIC;
3005 spin_unlock_irq(&np->lock);
3006 }
3007
3008 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3009 {
3010 struct fe_priv *np = netdev_priv(dev);
3011 u8 __iomem *base = get_hwbase(dev);
3012 u32 flags = 0;
3013
3014 if (wolinfo->wolopts == 0) {
3015 np->wolenabled = 0;
3016 } else if (wolinfo->wolopts & WAKE_MAGIC) {
3017 np->wolenabled = 1;
3018 flags = NVREG_WAKEUPFLAGS_ENABLE;
3019 }
3020 if (netif_running(dev)) {
3021 spin_lock_irq(&np->lock);
3022 writel(flags, base + NvRegWakeUpFlags);
3023 spin_unlock_irq(&np->lock);
3024 }
3025 return 0;
3026 }
3027
3028 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3029 {
3030 struct fe_priv *np = netdev_priv(dev);
3031 int adv;
3032
3033 spin_lock_irq(&np->lock);
3034 ecmd->port = PORT_MII;
3035 if (!netif_running(dev)) {
3036 /* We do not track link speed / duplex setting if the
3037 * interface is disabled. Force a link check */
3038 if (nv_update_linkspeed(dev)) {
3039 if (!netif_carrier_ok(dev))
3040 netif_carrier_on(dev);
3041 } else {
3042 if (netif_carrier_ok(dev))
3043 netif_carrier_off(dev);
3044 }
3045 }
3046
3047 if (netif_carrier_ok(dev)) {
3048 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3049 case NVREG_LINKSPEED_10:
3050 ecmd->speed = SPEED_10;
3051 break;
3052 case NVREG_LINKSPEED_100:
3053 ecmd->speed = SPEED_100;
3054 break;
3055 case NVREG_LINKSPEED_1000:
3056 ecmd->speed = SPEED_1000;
3057 break;
3058 }
3059 ecmd->duplex = DUPLEX_HALF;
3060 if (np->duplex)
3061 ecmd->duplex = DUPLEX_FULL;
3062 } else {
3063 ecmd->speed = -1;
3064 ecmd->duplex = -1;
3065 }
3066
3067 ecmd->autoneg = np->autoneg;
3068
3069 ecmd->advertising = ADVERTISED_MII;
3070 if (np->autoneg) {
3071 ecmd->advertising |= ADVERTISED_Autoneg;
3072 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3073 if (adv & ADVERTISE_10HALF)
3074 ecmd->advertising |= ADVERTISED_10baseT_Half;
3075 if (adv & ADVERTISE_10FULL)
3076 ecmd->advertising |= ADVERTISED_10baseT_Full;
3077 if (adv & ADVERTISE_100HALF)
3078 ecmd->advertising |= ADVERTISED_100baseT_Half;
3079 if (adv & ADVERTISE_100FULL)
3080 ecmd->advertising |= ADVERTISED_100baseT_Full;
3081 if (np->gigabit == PHY_GIGABIT) {
3082 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3083 if (adv & ADVERTISE_1000FULL)
3084 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3085 }
3086 }
3087 ecmd->supported = (SUPPORTED_Autoneg |
3088 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3089 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3090 SUPPORTED_MII);
3091 if (np->gigabit == PHY_GIGABIT)
3092 ecmd->supported |= SUPPORTED_1000baseT_Full;
3093
3094 ecmd->phy_address = np->phyaddr;
3095 ecmd->transceiver = XCVR_EXTERNAL;
3096
3097 /* ignore maxtxpkt, maxrxpkt for now */
3098 spin_unlock_irq(&np->lock);
3099 return 0;
3100 }
3101
3102 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3103 {
3104 struct fe_priv *np = netdev_priv(dev);
3105
3106 if (ecmd->port != PORT_MII)
3107 return -EINVAL;
3108 if (ecmd->transceiver != XCVR_EXTERNAL)
3109 return -EINVAL;
3110 if (ecmd->phy_address != np->phyaddr) {
3111 /* TODO: support switching between multiple phys. Should be
3112 * trivial, but not enabled due to lack of test hardware. */
3113 return -EINVAL;
3114 }
3115 if (ecmd->autoneg == AUTONEG_ENABLE) {
3116 u32 mask;
3117
3118 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3119 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3120 if (np->gigabit == PHY_GIGABIT)
3121 mask |= ADVERTISED_1000baseT_Full;
3122
3123 if ((ecmd->advertising & mask) == 0)
3124 return -EINVAL;
3125
3126 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3127 /* Note: autonegotiation disable, speed 1000 intentionally
3128 * forbidden - noone should need that. */
3129
3130 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3131 return -EINVAL;
3132 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3133 return -EINVAL;
3134 } else {
3135 return -EINVAL;
3136 }
3137
3138 netif_carrier_off(dev);
3139 if (netif_running(dev)) {
3140 nv_disable_irq(dev);
3141 netif_tx_lock_bh(dev);
3142 spin_lock(&np->lock);
3143 /* stop engines */
3144 nv_stop_rx(dev);
3145 nv_stop_tx(dev);
3146 spin_unlock(&np->lock);
3147 netif_tx_unlock_bh(dev);
3148 }
3149
3150 if (ecmd->autoneg == AUTONEG_ENABLE) {
3151 int adv, bmcr;
3152
3153 np->autoneg = 1;
3154
3155 /* advertise only what has been requested */
3156 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3157 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3158 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3159 adv |= ADVERTISE_10HALF;
3160 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3161 adv |= ADVERTISE_10FULL;
3162 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3163 adv |= ADVERTISE_100HALF;
3164 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3165 adv |= ADVERTISE_100FULL;
3166 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3167 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3168 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3169 adv |= ADVERTISE_PAUSE_ASYM;
3170 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3171
3172 if (np->gigabit == PHY_GIGABIT) {
3173 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3174 adv &= ~ADVERTISE_1000FULL;
3175 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3176 adv |= ADVERTISE_1000FULL;
3177 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3178 }
3179
3180 if (netif_running(dev))
3181 printk(KERN_INFO "%s: link down.\n", dev->name);
3182 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3183 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3184 bmcr |= BMCR_ANENABLE;
3185 /* reset the phy in order for settings to stick,
3186 * and cause autoneg to start */
3187 if (phy_reset(dev, bmcr)) {
3188 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3189 return -EINVAL;
3190 }
3191 } else {
3192 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3193 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3194 }
3195 } else {
3196 int adv, bmcr;
3197
3198 np->autoneg = 0;
3199
3200 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3201 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3202 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3203 adv |= ADVERTISE_10HALF;
3204 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3205 adv |= ADVERTISE_10FULL;
3206 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3207 adv |= ADVERTISE_100HALF;
3208 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3209 adv |= ADVERTISE_100FULL;
3210 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3211 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3212 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3213 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3214 }
3215 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3216 adv |= ADVERTISE_PAUSE_ASYM;
3217 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3218 }
3219 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3220 np->fixed_mode = adv;
3221
3222 if (np->gigabit == PHY_GIGABIT) {
3223 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3224 adv &= ~ADVERTISE_1000FULL;
3225 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3226 }
3227
3228 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3229 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3230 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3231 bmcr |= BMCR_FULLDPLX;
3232 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3233 bmcr |= BMCR_SPEED100;
3234 if (np->phy_oui == PHY_OUI_MARVELL) {
3235 /* reset the phy in order for forced mode settings to stick */
3236 if (phy_reset(dev, bmcr)) {
3237 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3238 return -EINVAL;
3239 }
3240 } else {
3241 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3242 if (netif_running(dev)) {
3243 /* Wait a bit and then reconfigure the nic. */
3244 udelay(10);
3245 nv_linkchange(dev);
3246 }
3247 }
3248 }
3249
3250 if (netif_running(dev)) {
3251 nv_start_rx(dev);
3252 nv_start_tx(dev);
3253 nv_enable_irq(dev);
3254 }
3255
3256 return 0;
3257 }
3258
3259 #define FORCEDETH_REGS_VER 1
3260
3261 static int nv_get_regs_len(struct net_device *dev)
3262 {
3263 struct fe_priv *np = netdev_priv(dev);
3264 return np->register_size;
3265 }
3266
3267 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3268 {
3269 struct fe_priv *np = netdev_priv(dev);
3270 u8 __iomem *base = get_hwbase(dev);
3271 u32 *rbuf = buf;
3272 int i;
3273
3274 regs->version = FORCEDETH_REGS_VER;
3275 spin_lock_irq(&np->lock);
3276 for (i = 0;i <= np->register_size/sizeof(u32); i++)
3277 rbuf[i] = readl(base + i*sizeof(u32));
3278 spin_unlock_irq(&np->lock);
3279 }
3280
3281 static int nv_nway_reset(struct net_device *dev)
3282 {
3283 struct fe_priv *np = netdev_priv(dev);
3284 int ret;
3285
3286 if (np->autoneg) {
3287 int bmcr;
3288
3289 netif_carrier_off(dev);
3290 if (netif_running(dev)) {
3291 nv_disable_irq(dev);
3292 netif_tx_lock_bh(dev);
3293 spin_lock(&np->lock);
3294 /* stop engines */
3295 nv_stop_rx(dev);
3296 nv_stop_tx(dev);
3297 spin_unlock(&np->lock);
3298 netif_tx_unlock_bh(dev);
3299 printk(KERN_INFO "%s: link down.\n", dev->name);
3300 }
3301
3302 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3303 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3304 bmcr |= BMCR_ANENABLE;
3305 /* reset the phy in order for settings to stick*/
3306 if (phy_reset(dev, bmcr)) {
3307 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3308 return -EINVAL;
3309 }
3310 } else {
3311 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3312 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3313 }
3314
3315 if (netif_running(dev)) {
3316 nv_start_rx(dev);
3317 nv_start_tx(dev);
3318 nv_enable_irq(dev);
3319 }
3320 ret = 0;
3321 } else {
3322 ret = -EINVAL;
3323 }
3324
3325 return ret;
3326 }
3327
3328 static int nv_set_tso(struct net_device *dev, u32 value)
3329 {
3330 struct fe_priv *np = netdev_priv(dev);
3331
3332 if ((np->driver_data & DEV_HAS_CHECKSUM))
3333 return ethtool_op_set_tso(dev, value);
3334 else
3335 return -EOPNOTSUPP;
3336 }
3337
3338 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3339 {
3340 struct fe_priv *np = netdev_priv(dev);
3341
3342 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3343 ring->rx_mini_max_pending = 0;
3344 ring->rx_jumbo_max_pending = 0;
3345 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3346
3347 ring->rx_pending = np->rx_ring_size;
3348 ring->rx_mini_pending = 0;
3349 ring->rx_jumbo_pending = 0;
3350 ring->tx_pending = np->tx_ring_size;
3351 }
3352
3353 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3354 {
3355 struct fe_priv *np = netdev_priv(dev);
3356 u8 __iomem *base = get_hwbase(dev);
3357 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
3358 dma_addr_t ring_addr;
3359
3360 if (ring->rx_pending < RX_RING_MIN ||
3361 ring->tx_pending < TX_RING_MIN ||
3362 ring->rx_mini_pending != 0 ||
3363 ring->rx_jumbo_pending != 0 ||
3364 (np->desc_ver == DESC_VER_1 &&
3365 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3366 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3367 (np->desc_ver != DESC_VER_1 &&
3368 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3369 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3370 return -EINVAL;
3371 }
3372
3373 /* allocate new rings */
3374 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3375 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3376 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3377 &ring_addr);
3378 } else {
3379 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3380 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3381 &ring_addr);
3382 }
3383 rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
3384 rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
3385 tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
3386 tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
3387 tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3388 if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3389 /* fall back to old rings */
3390 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3391 if (rxtx_ring)
3392 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3393 rxtx_ring, ring_addr);
3394 } else {
3395 if (rxtx_ring)
3396 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3397 rxtx_ring, ring_addr);
3398 }
3399 if (rx_skbuff)
3400 kfree(rx_skbuff);
3401 if (rx_dma)
3402 kfree(rx_dma);
3403 if (tx_skbuff)
3404 kfree(tx_skbuff);
3405 if (tx_dma)
3406 kfree(tx_dma);
3407 if (tx_dma_len)
3408 kfree(tx_dma_len);
3409 goto exit;
3410 }
3411
3412 if (netif_running(dev)) {
3413 nv_disable_irq(dev);
3414 netif_tx_lock_bh(dev);
3415 spin_lock(&np->lock);
3416 /* stop engines */
3417 nv_stop_rx(dev);
3418 nv_stop_tx(dev);
3419 nv_txrx_reset(dev);
3420 /* drain queues */
3421 nv_drain_rx(dev);
3422 nv_drain_tx(dev);
3423 /* delete queues */
3424 free_rings(dev);
3425 }
3426
3427 /* set new values */
3428 np->rx_ring_size = ring->rx_pending;
3429 np->tx_ring_size = ring->tx_pending;
3430 np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
3431 np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
3432 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3433 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3434 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3435 } else {
3436 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3437 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3438 }
3439 np->rx_skbuff = (struct sk_buff**)rx_skbuff;
3440 np->rx_dma = (dma_addr_t*)rx_dma;
3441 np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3442 np->tx_dma = (dma_addr_t*)tx_dma;
3443 np->tx_dma_len = (unsigned int*)tx_dma_len;
3444 np->ring_addr = ring_addr;
3445
3446 memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3447 memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3448 memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3449 memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3450 memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3451
3452 if (netif_running(dev)) {
3453 /* reinit driver view of the queues */
3454 set_bufsize(dev);
3455 if (nv_init_ring(dev)) {
3456 if (!np->in_shutdown)
3457 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3458 }
3459
3460 /* reinit nic view of the queues */
3461 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3462 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3463 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3464 base + NvRegRingSizes);
3465 pci_push(base);
3466 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3467 pci_push(base);
3468
3469 /* restart engines */
3470 nv_start_rx(dev);
3471 nv_start_tx(dev);
3472 spin_unlock(&np->lock);
3473 netif_tx_unlock_bh(dev);
3474 nv_enable_irq(dev);
3475 }
3476 return 0;
3477 exit:
3478 return -ENOMEM;
3479 }
3480
3481 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3482 {
3483 struct fe_priv *np = netdev_priv(dev);
3484
3485 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3486 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3487 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3488 }
3489
3490 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3491 {
3492 struct fe_priv *np = netdev_priv(dev);
3493 int adv, bmcr;
3494
3495 if ((!np->autoneg && np->duplex == 0) ||
3496 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3497 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3498 dev->name);
3499 return -EINVAL;
3500 }
3501 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3502 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3503 return -EINVAL;
3504 }
3505
3506 netif_carrier_off(dev);
3507 if (netif_running(dev)) {
3508 nv_disable_irq(dev);
3509 netif_tx_lock_bh(dev);
3510 spin_lock(&np->lock);
3511 /* stop engines */
3512 nv_stop_rx(dev);
3513 nv_stop_tx(dev);
3514 spin_unlock(&np->lock);
3515 netif_tx_unlock_bh(dev);
3516 }
3517
3518 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3519 if (pause->rx_pause)
3520 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3521 if (pause->tx_pause)
3522 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3523
3524 if (np->autoneg && pause->autoneg) {
3525 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3526
3527 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3528 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3529 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3530 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3531 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3532 adv |= ADVERTISE_PAUSE_ASYM;
3533 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3534
3535 if (netif_running(dev))
3536 printk(KERN_INFO "%s: link down.\n", dev->name);
3537 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3538 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3539 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3540 } else {
3541 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3542 if (pause->rx_pause)
3543 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3544 if (pause->tx_pause)
3545 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3546
3547 if (!netif_running(dev))
3548 nv_update_linkspeed(dev);
3549 else
3550 nv_update_pause(dev, np->pause_flags);
3551 }
3552
3553 if (netif_running(dev)) {
3554 nv_start_rx(dev);
3555 nv_start_tx(dev);
3556 nv_enable_irq(dev);
3557 }
3558 return 0;
3559 }
3560
3561 static u32 nv_get_rx_csum(struct net_device *dev)
3562 {
3563 struct fe_priv *np = netdev_priv(dev);
3564 return (np->rx_csum) != 0;
3565 }
3566
3567 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3568 {
3569 struct fe_priv *np = netdev_priv(dev);
3570 u8 __iomem *base = get_hwbase(dev);
3571 int retcode = 0;
3572
3573 if (np->driver_data & DEV_HAS_CHECKSUM) {
3574 if (data) {
3575 np->rx_csum = 1;
3576 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3577 } else {
3578 np->rx_csum = 0;
3579 /* vlan is dependent on rx checksum offload */
3580 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
3581 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3582 }
3583 if (netif_running(dev)) {
3584 spin_lock_irq(&np->lock);
3585 writel(np->txrxctl_bits, base + NvRegTxRxControl);
3586 spin_unlock_irq(&np->lock);
3587 }
3588 } else {
3589 return -EINVAL;
3590 }
3591
3592 return retcode;
3593 }
3594
3595 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3596 {
3597 struct fe_priv *np = netdev_priv(dev);
3598
3599 if (np->driver_data & DEV_HAS_CHECKSUM)
3600 return ethtool_op_set_tx_hw_csum(dev, data);
3601 else
3602 return -EOPNOTSUPP;
3603 }
3604
3605 static int nv_set_sg(struct net_device *dev, u32 data)
3606 {
3607 struct fe_priv *np = netdev_priv(dev);
3608
3609 if (np->driver_data & DEV_HAS_CHECKSUM)
3610 return ethtool_op_set_sg(dev, data);
3611 else
3612 return -EOPNOTSUPP;
3613 }
3614
3615 static int nv_get_stats_count(struct net_device *dev)
3616 {
3617 struct fe_priv *np = netdev_priv(dev);
3618
3619 if (np->driver_data & DEV_HAS_STATISTICS)
3620 return sizeof(struct nv_ethtool_stats)/sizeof(u64);
3621 else
3622 return 0;
3623 }
3624
3625 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3626 {
3627 struct fe_priv *np = netdev_priv(dev);
3628
3629 /* update stats */
3630 nv_do_stats_poll((unsigned long)dev);
3631
3632 memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3633 }
3634
3635 static int nv_self_test_count(struct net_device *dev)
3636 {
3637 struct fe_priv *np = netdev_priv(dev);
3638
3639 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3640 return NV_TEST_COUNT_EXTENDED;
3641 else
3642 return NV_TEST_COUNT_BASE;
3643 }
3644
3645 static int nv_link_test(struct net_device *dev)
3646 {
3647 struct fe_priv *np = netdev_priv(dev);
3648 int mii_status;
3649
3650 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3651 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3652
3653 /* check phy link status */
3654 if (!(mii_status & BMSR_LSTATUS))
3655 return 0;
3656 else
3657 return 1;
3658 }
3659
3660 static int nv_register_test(struct net_device *dev)
3661 {
3662 u8 __iomem *base = get_hwbase(dev);
3663 int i = 0;
3664 u32 orig_read, new_read;
3665
3666 do {
3667 orig_read = readl(base + nv_registers_test[i].reg);
3668
3669 /* xor with mask to toggle bits */
3670 orig_read ^= nv_registers_test[i].mask;
3671
3672 writel(orig_read, base + nv_registers_test[i].reg);
3673
3674 new_read = readl(base + nv_registers_test[i].reg);
3675
3676 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3677 return 0;
3678
3679 /* restore original value */
3680 orig_read ^= nv_registers_test[i].mask;
3681 writel(orig_read, base + nv_registers_test[i].reg);
3682
3683 } while (nv_registers_test[++i].reg != 0);
3684
3685 return 1;
3686 }
3687
3688 static int nv_interrupt_test(struct net_device *dev)
3689 {
3690 struct fe_priv *np = netdev_priv(dev);
3691 u8 __iomem *base = get_hwbase(dev);
3692 int ret = 1;
3693 int testcnt;
3694 u32 save_msi_flags, save_poll_interval = 0;
3695
3696 if (netif_running(dev)) {
3697 /* free current irq */
3698 nv_free_irq(dev);
3699 save_poll_interval = readl(base+NvRegPollingInterval);
3700 }
3701
3702 /* flag to test interrupt handler */
3703 np->intr_test = 0;
3704
3705 /* setup test irq */
3706 save_msi_flags = np->msi_flags;
3707 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3708 np->msi_flags |= 0x001; /* setup 1 vector */
3709 if (nv_request_irq(dev, 1))
3710 return 0;
3711
3712 /* setup timer interrupt */
3713 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3714 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3715
3716 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3717
3718 /* wait for at least one interrupt */
3719 msleep(100);
3720
3721 spin_lock_irq(&np->lock);
3722
3723 /* flag should be set within ISR */
3724 testcnt = np->intr_test;
3725 if (!testcnt)
3726 ret = 2;
3727
3728 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3729 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3730 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3731 else
3732 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3733
3734 spin_unlock_irq(&np->lock);
3735
3736 nv_free_irq(dev);
3737
3738 np->msi_flags = save_msi_flags;
3739
3740 if (netif_running(dev)) {
3741 writel(save_poll_interval, base + NvRegPollingInterval);
3742 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3743 /* restore original irq */
3744 if (nv_request_irq(dev, 0))
3745 return 0;
3746 }
3747
3748 return ret;
3749 }
3750
3751 static int nv_loopback_test(struct net_device *dev)
3752 {
3753 struct fe_priv *np = netdev_priv(dev);
3754 u8 __iomem *base = get_hwbase(dev);
3755 struct sk_buff *tx_skb, *rx_skb;
3756 dma_addr_t test_dma_addr;
3757 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3758 u32 flags;
3759 int len, i, pkt_len;
3760 u8 *pkt_data;
3761 u32 filter_flags = 0;
3762 u32 misc1_flags = 0;
3763 int ret = 1;
3764
3765 if (netif_running(dev)) {
3766 nv_disable_irq(dev);
3767 filter_flags = readl(base + NvRegPacketFilterFlags);
3768 misc1_flags = readl(base + NvRegMisc1);
3769 } else {
3770 nv_txrx_reset(dev);
3771 }
3772
3773 /* reinit driver view of the rx queue */
3774 set_bufsize(dev);
3775 nv_init_ring(dev);
3776
3777 /* setup hardware for loopback */
3778 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3779 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3780
3781 /* reinit nic view of the rx queue */
3782 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3783 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3784 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3785 base + NvRegRingSizes);
3786 pci_push(base);
3787
3788 /* restart rx engine */
3789 nv_start_rx(dev);
3790 nv_start_tx(dev);
3791
3792 /* setup packet for tx */
3793 pkt_len = ETH_DATA_LEN;
3794 tx_skb = dev_alloc_skb(pkt_len);
3795 if (!tx_skb) {
3796 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
3797 " of %s\n", dev->name);
3798 ret = 0;
3799 goto out;
3800 }
3801 pkt_data = skb_put(tx_skb, pkt_len);
3802 for (i = 0; i < pkt_len; i++)
3803 pkt_data[i] = (u8)(i & 0xff);
3804 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
3805 tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
3806
3807 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3808 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
3809 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3810 } else {
3811 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
3812 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
3813 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3814 }
3815 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3816 pci_push(get_hwbase(dev));
3817
3818 msleep(500);
3819
3820 /* check for rx of the packet */
3821 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3822 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
3823 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
3824
3825 } else {
3826 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
3827 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
3828 }
3829
3830 if (flags & NV_RX_AVAIL) {
3831 ret = 0;
3832 } else if (np->desc_ver == DESC_VER_1) {
3833 if (flags & NV_RX_ERROR)
3834 ret = 0;
3835 } else {
3836 if (flags & NV_RX2_ERROR) {
3837 ret = 0;
3838 }
3839 }
3840
3841 if (ret) {
3842 if (len != pkt_len) {
3843 ret = 0;
3844 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
3845 dev->name, len, pkt_len);
3846 } else {
3847 rx_skb = np->rx_skbuff[0];
3848 for (i = 0; i < pkt_len; i++) {
3849 if (rx_skb->data[i] != (u8)(i & 0xff)) {
3850 ret = 0;
3851 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
3852 dev->name, i);
3853 break;
3854 }
3855 }
3856 }
3857 } else {
3858 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
3859 }
3860
3861 pci_unmap_page(np->pci_dev, test_dma_addr,
3862 tx_skb->end-tx_skb->data,
3863 PCI_DMA_TODEVICE);
3864 dev_kfree_skb_any(tx_skb);
3865 out:
3866 /* stop engines */
3867 nv_stop_rx(dev);
3868 nv_stop_tx(dev);
3869 nv_txrx_reset(dev);
3870 /* drain rx queue */
3871 nv_drain_rx(dev);
3872 nv_drain_tx(dev);
3873
3874 if (netif_running(dev)) {
3875 writel(misc1_flags, base + NvRegMisc1);
3876 writel(filter_flags, base + NvRegPacketFilterFlags);
3877 nv_enable_irq(dev);
3878 }
3879
3880 return ret;
3881 }
3882
3883 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
3884 {
3885 struct fe_priv *np = netdev_priv(dev);
3886 u8 __iomem *base = get_hwbase(dev);
3887 int result;
3888 memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
3889
3890 if (!nv_link_test(dev)) {
3891 test->flags |= ETH_TEST_FL_FAILED;
3892 buffer[0] = 1;
3893 }
3894
3895 if (test->flags & ETH_TEST_FL_OFFLINE) {
3896 if (netif_running(dev)) {
3897 netif_stop_queue(dev);
3898 netif_poll_disable(dev);
3899 netif_tx_lock_bh(dev);
3900 spin_lock_irq(&np->lock);
3901 nv_disable_hw_interrupts(dev, np->irqmask);
3902 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3903 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3904 } else {
3905 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3906 }
3907 /* stop engines */
3908 nv_stop_rx(dev);
3909 nv_stop_tx(dev);
3910 nv_txrx_reset(dev);
3911 /* drain rx queue */
3912 nv_drain_rx(dev);
3913 nv_drain_tx(dev);
3914 spin_unlock_irq(&np->lock);
3915 netif_tx_unlock_bh(dev);
3916 }
3917
3918 if (!nv_register_test(dev)) {
3919 test->flags |= ETH_TEST_FL_FAILED;
3920 buffer[1] = 1;
3921 }
3922
3923 result = nv_interrupt_test(dev);
3924 if (result != 1) {
3925 test->flags |= ETH_TEST_FL_FAILED;
3926 buffer[2] = 1;
3927 }
3928 if (result == 0) {
3929 /* bail out */
3930 return;
3931 }
3932
3933 if (!nv_loopback_test(dev)) {
3934 test->flags |= ETH_TEST_FL_FAILED;
3935 buffer[3] = 1;
3936 }
3937
3938 if (netif_running(dev)) {
3939 /* reinit driver view of the rx queue */
3940 set_bufsize(dev);
3941 if (nv_init_ring(dev)) {
3942 if (!np->in_shutdown)
3943 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3944 }
3945 /* reinit nic view of the rx queue */
3946 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3947 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3948 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3949 base + NvRegRingSizes);
3950 pci_push(base);
3951 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3952 pci_push(base);
3953 /* restart rx engine */
3954 nv_start_rx(dev);
3955 nv_start_tx(dev);
3956 netif_start_queue(dev);
3957 netif_poll_enable(dev);
3958 nv_enable_hw_interrupts(dev, np->irqmask);
3959 }
3960 }
3961 }
3962
3963 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
3964 {
3965 switch (stringset) {
3966 case ETH_SS_STATS:
3967 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
3968 break;
3969 case ETH_SS_TEST:
3970 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
3971 break;
3972 }
3973 }
3974
3975 static const struct ethtool_ops ops = {
3976 .get_drvinfo = nv_get_drvinfo,
3977 .get_link = ethtool_op_get_link,
3978 .get_wol = nv_get_wol,
3979 .set_wol = nv_set_wol,
3980 .get_settings = nv_get_settings,
3981 .set_settings = nv_set_settings,
3982 .get_regs_len = nv_get_regs_len,
3983 .get_regs = nv_get_regs,
3984 .nway_reset = nv_nway_reset,
3985 .get_perm_addr = ethtool_op_get_perm_addr,
3986 .get_tso = ethtool_op_get_tso,
3987 .set_tso = nv_set_tso,
3988 .get_ringparam = nv_get_ringparam,
3989 .set_ringparam = nv_set_ringparam,
3990 .get_pauseparam = nv_get_pauseparam,
3991 .set_pauseparam = nv_set_pauseparam,
3992 .get_rx_csum = nv_get_rx_csum,
3993 .set_rx_csum = nv_set_rx_csum,
3994 .get_tx_csum = ethtool_op_get_tx_csum,
3995 .set_tx_csum = nv_set_tx_csum,
3996 .get_sg = ethtool_op_get_sg,
3997 .set_sg = nv_set_sg,
3998 .get_strings = nv_get_strings,
3999 .get_stats_count = nv_get_stats_count,
4000 .get_ethtool_stats = nv_get_ethtool_stats,
4001 .self_test_count = nv_self_test_count,
4002 .self_test = nv_self_test,
4003 };
4004
4005 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4006 {
4007 struct fe_priv *np = get_nvpriv(dev);
4008
4009 spin_lock_irq(&np->lock);
4010
4011 /* save vlan group */
4012 np->vlangrp = grp;
4013
4014 if (grp) {
4015 /* enable vlan on MAC */
4016 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4017 } else {
4018 /* disable vlan on MAC */
4019 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4020 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4021 }
4022
4023 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4024
4025 spin_unlock_irq(&np->lock);
4026 };
4027
4028 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4029 {
4030 /* nothing to do */
4031 };
4032
4033 static int nv_open(struct net_device *dev)
4034 {
4035 struct fe_priv *np = netdev_priv(dev);
4036 u8 __iomem *base = get_hwbase(dev);
4037 int ret = 1;
4038 int oom, i;
4039
4040 dprintk(KERN_DEBUG "nv_open: begin\n");
4041
4042 /* erase previous misconfiguration */
4043 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4044 nv_mac_reset(dev);
4045 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4046 writel(0, base + NvRegMulticastAddrB);
4047 writel(0, base + NvRegMulticastMaskA);
4048 writel(0, base + NvRegMulticastMaskB);
4049 writel(0, base + NvRegPacketFilterFlags);
4050
4051 writel(0, base + NvRegTransmitterControl);
4052 writel(0, base + NvRegReceiverControl);
4053
4054 writel(0, base + NvRegAdapterControl);
4055
4056 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4057 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
4058
4059 /* initialize descriptor rings */
4060 set_bufsize(dev);
4061 oom = nv_init_ring(dev);
4062
4063 writel(0, base + NvRegLinkSpeed);
4064 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4065 nv_txrx_reset(dev);
4066 writel(0, base + NvRegUnknownSetupReg6);
4067
4068 np->in_shutdown = 0;
4069
4070 /* give hw rings */
4071 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4072 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4073 base + NvRegRingSizes);
4074
4075 writel(np->linkspeed, base + NvRegLinkSpeed);
4076 if (np->desc_ver == DESC_VER_1)
4077 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4078 else
4079 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4080 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4081 writel(np->vlanctl_bits, base + NvRegVlanControl);
4082 pci_push(base);
4083 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4084 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4085 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4086 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4087
4088 writel(0, base + NvRegUnknownSetupReg4);
4089 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4090 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4091
4092 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4093 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4094 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4095 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4096
4097 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4098 get_random_bytes(&i, sizeof(i));
4099 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4100 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4101 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4102 if (poll_interval == -1) {
4103 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4104 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4105 else
4106 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4107 }
4108 else
4109 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4110 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4111 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4112 base + NvRegAdapterControl);
4113 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4114 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
4115 if (np->wolenabled)
4116 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4117
4118 i = readl(base + NvRegPowerState);
4119 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4120 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4121
4122 pci_push(base);
4123 udelay(10);
4124 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4125
4126 nv_disable_hw_interrupts(dev, np->irqmask);
4127 pci_push(base);
4128 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4129 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4130 pci_push(base);
4131
4132 if (nv_request_irq(dev, 0)) {
4133 goto out_drain;
4134 }
4135
4136 /* ask for interrupts */
4137 nv_enable_hw_interrupts(dev, np->irqmask);
4138
4139 spin_lock_irq(&np->lock);
4140 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4141 writel(0, base + NvRegMulticastAddrB);
4142 writel(0, base + NvRegMulticastMaskA);
4143 writel(0, base + NvRegMulticastMaskB);
4144 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4145 /* One manual link speed update: Interrupts are enabled, future link
4146 * speed changes cause interrupts and are handled by nv_link_irq().
4147 */
4148 {
4149 u32 miistat;
4150 miistat = readl(base + NvRegMIIStatus);
4151 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4152 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4153 }
4154 /* set linkspeed to invalid value, thus force nv_update_linkspeed
4155 * to init hw */
4156 np->linkspeed = 0;
4157 ret = nv_update_linkspeed(dev);
4158 nv_start_rx(dev);
4159 nv_start_tx(dev);
4160 netif_start_queue(dev);
4161 netif_poll_enable(dev);
4162
4163 if (ret) {
4164 netif_carrier_on(dev);
4165 } else {
4166 printk("%s: no link during initialization.\n", dev->name);
4167 netif_carrier_off(dev);
4168 }
4169 if (oom)
4170 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4171
4172 /* start statistics timer */
4173 if (np->driver_data & DEV_HAS_STATISTICS)
4174 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4175
4176 spin_unlock_irq(&np->lock);
4177
4178 return 0;
4179 out_drain:
4180 drain_ring(dev);
4181 return ret;
4182 }
4183
4184 static int nv_close(struct net_device *dev)
4185 {
4186 struct fe_priv *np = netdev_priv(dev);
4187 u8 __iomem *base;
4188
4189 spin_lock_irq(&np->lock);
4190 np->in_shutdown = 1;
4191 spin_unlock_irq(&np->lock);
4192 netif_poll_disable(dev);
4193 synchronize_irq(dev->irq);
4194
4195 del_timer_sync(&np->oom_kick);
4196 del_timer_sync(&np->nic_poll);
4197 del_timer_sync(&np->stats_poll);
4198
4199 netif_stop_queue(dev);
4200 spin_lock_irq(&np->lock);
4201 nv_stop_tx(dev);
4202 nv_stop_rx(dev);
4203 nv_txrx_reset(dev);
4204
4205 /* disable interrupts on the nic or we will lock up */
4206 base = get_hwbase(dev);
4207 nv_disable_hw_interrupts(dev, np->irqmask);
4208 pci_push(base);
4209 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4210
4211 spin_unlock_irq(&np->lock);
4212
4213 nv_free_irq(dev);
4214
4215 drain_ring(dev);
4216
4217 if (np->wolenabled)
4218 nv_start_rx(dev);
4219
4220 /* FIXME: power down nic */
4221
4222 return 0;
4223 }
4224
4225 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4226 {
4227 struct net_device *dev;
4228 struct fe_priv *np;
4229 unsigned long addr;
4230 u8 __iomem *base;
4231 int err, i;
4232 u32 powerstate, txreg;
4233
4234 dev = alloc_etherdev(sizeof(struct fe_priv));
4235 err = -ENOMEM;
4236 if (!dev)
4237 goto out;
4238
4239 np = netdev_priv(dev);
4240 np->pci_dev = pci_dev;
4241 spin_lock_init(&np->lock);
4242 SET_MODULE_OWNER(dev);
4243 SET_NETDEV_DEV(dev, &pci_dev->dev);
4244
4245 init_timer(&np->oom_kick);
4246 np->oom_kick.data = (unsigned long) dev;
4247 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
4248 init_timer(&np->nic_poll);
4249 np->nic_poll.data = (unsigned long) dev;
4250 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
4251 init_timer(&np->stats_poll);
4252 np->stats_poll.data = (unsigned long) dev;
4253 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
4254
4255 err = pci_enable_device(pci_dev);
4256 if (err) {
4257 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4258 err, pci_name(pci_dev));
4259 goto out_free;
4260 }
4261
4262 pci_set_master(pci_dev);
4263
4264 err = pci_request_regions(pci_dev, DRV_NAME);
4265 if (err < 0)
4266 goto out_disable;
4267
4268 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4269 np->register_size = NV_PCI_REGSZ_VER2;
4270 else
4271 np->register_size = NV_PCI_REGSZ_VER1;
4272
4273 err = -EINVAL;
4274 addr = 0;
4275 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4276 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4277 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4278 pci_resource_len(pci_dev, i),
4279 pci_resource_flags(pci_dev, i));
4280 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4281 pci_resource_len(pci_dev, i) >= np->register_size) {
4282 addr = pci_resource_start(pci_dev, i);
4283 break;
4284 }
4285 }
4286 if (i == DEVICE_COUNT_RESOURCE) {
4287 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4288 pci_name(pci_dev));
4289 goto out_relreg;
4290 }
4291
4292 /* copy of driver data */
4293 np->driver_data = id->driver_data;
4294
4295 /* handle different descriptor versions */
4296 if (id->driver_data & DEV_HAS_HIGH_DMA) {
4297 /* packet format 3: supports 40-bit addressing */
4298 np->desc_ver = DESC_VER_3;
4299 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4300 if (dma_64bit) {
4301 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4302 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4303 pci_name(pci_dev));
4304 } else {
4305 dev->features |= NETIF_F_HIGHDMA;
4306 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4307 }
4308 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4309 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4310 pci_name(pci_dev));
4311 }
4312 }
4313 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4314 /* packet format 2: supports jumbo frames */
4315 np->desc_ver = DESC_VER_2;
4316 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4317 } else {
4318 /* original packet format */
4319 np->desc_ver = DESC_VER_1;
4320 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4321 }
4322
4323 np->pkt_limit = NV_PKTLIMIT_1;
4324 if (id->driver_data & DEV_HAS_LARGEDESC)
4325 np->pkt_limit = NV_PKTLIMIT_2;
4326
4327 if (id->driver_data & DEV_HAS_CHECKSUM) {
4328 np->rx_csum = 1;
4329 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4330 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4331 #ifdef NETIF_F_TSO
4332 dev->features |= NETIF_F_TSO;
4333 #endif
4334 }
4335
4336 np->vlanctl_bits = 0;
4337 if (id->driver_data & DEV_HAS_VLAN) {
4338 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4339 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4340 dev->vlan_rx_register = nv_vlan_rx_register;
4341 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4342 }
4343
4344 np->msi_flags = 0;
4345 if ((id->driver_data & DEV_HAS_MSI) && msi) {
4346 np->msi_flags |= NV_MSI_CAPABLE;
4347 }
4348 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4349 np->msi_flags |= NV_MSI_X_CAPABLE;
4350 }
4351
4352 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4353 if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4354 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4355 }
4356
4357
4358 err = -ENOMEM;
4359 np->base = ioremap(addr, np->register_size);
4360 if (!np->base)
4361 goto out_relreg;
4362 dev->base_addr = (unsigned long)np->base;
4363
4364 dev->irq = pci_dev->irq;
4365
4366 np->rx_ring_size = RX_RING_DEFAULT;
4367 np->tx_ring_size = TX_RING_DEFAULT;
4368 np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
4369 np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
4370
4371 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4372 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4373 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4374 &np->ring_addr);
4375 if (!np->rx_ring.orig)
4376 goto out_unmap;
4377 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4378 } else {
4379 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4380 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4381 &np->ring_addr);
4382 if (!np->rx_ring.ex)
4383 goto out_unmap;
4384 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4385 }
4386 np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
4387 np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
4388 np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
4389 np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
4390 np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
4391 if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
4392 goto out_freering;
4393 memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
4394 memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
4395 memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
4396 memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
4397 memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
4398
4399 dev->open = nv_open;
4400 dev->stop = nv_close;
4401 dev->hard_start_xmit = nv_start_xmit;
4402 dev->get_stats = nv_get_stats;
4403 dev->change_mtu = nv_change_mtu;
4404 dev->set_mac_address = nv_set_mac_address;
4405 dev->set_multicast_list = nv_set_multicast;
4406 #ifdef CONFIG_NET_POLL_CONTROLLER
4407 dev->poll_controller = nv_poll_controller;
4408 #endif
4409 dev->weight = 64;
4410 #ifdef CONFIG_FORCEDETH_NAPI
4411 dev->poll = nv_napi_poll;
4412 #endif
4413 SET_ETHTOOL_OPS(dev, &ops);
4414 dev->tx_timeout = nv_tx_timeout;
4415 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4416
4417 pci_set_drvdata(pci_dev, dev);
4418
4419 /* read the mac address */
4420 base = get_hwbase(dev);
4421 np->orig_mac[0] = readl(base + NvRegMacAddrA);
4422 np->orig_mac[1] = readl(base + NvRegMacAddrB);
4423
4424 /* check the workaround bit for correct mac address order */
4425 txreg = readl(base + NvRegTransmitPoll);
4426 if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
4427 /* mac address is already in correct order */
4428 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
4429 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
4430 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
4431 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
4432 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
4433 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
4434 } else {
4435 /* need to reverse mac address to correct order */
4436 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
4437 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
4438 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4439 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4440 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
4441 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
4442 /* set permanent address to be correct aswell */
4443 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
4444 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
4445 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
4446 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4447 }
4448 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4449
4450 if (!is_valid_ether_addr(dev->perm_addr)) {
4451 /*
4452 * Bad mac address. At least one bios sets the mac address
4453 * to 01:23:45:67:89:ab
4454 */
4455 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4456 pci_name(pci_dev),
4457 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4458 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4459 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4460 dev->dev_addr[0] = 0x00;
4461 dev->dev_addr[1] = 0x00;
4462 dev->dev_addr[2] = 0x6c;
4463 get_random_bytes(&dev->dev_addr[3], 3);
4464 }
4465
4466 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4467 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4468 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4469
4470 /* set mac address */
4471 nv_copy_mac_to_hw(dev);
4472
4473 /* disable WOL */
4474 writel(0, base + NvRegWakeUpFlags);
4475 np->wolenabled = 0;
4476
4477 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4478 u8 revision_id;
4479 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4480
4481 /* take phy and nic out of low power mode */
4482 powerstate = readl(base + NvRegPowerState2);
4483 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4484 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4485 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4486 revision_id >= 0xA3)
4487 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4488 writel(powerstate, base + NvRegPowerState2);
4489 }
4490
4491 if (np->desc_ver == DESC_VER_1) {
4492 np->tx_flags = NV_TX_VALID;
4493 } else {
4494 np->tx_flags = NV_TX2_VALID;
4495 }
4496 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4497 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4498 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4499 np->msi_flags |= 0x0003;
4500 } else {
4501 np->irqmask = NVREG_IRQMASK_CPU;
4502 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4503 np->msi_flags |= 0x0001;
4504 }
4505
4506 if (id->driver_data & DEV_NEED_TIMERIRQ)
4507 np->irqmask |= NVREG_IRQ_TIMER;
4508 if (id->driver_data & DEV_NEED_LINKTIMER) {
4509 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4510 np->need_linktimer = 1;
4511 np->link_timeout = jiffies + LINK_TIMEOUT;
4512 } else {
4513 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4514 np->need_linktimer = 0;
4515 }
4516
4517 /* find a suitable phy */
4518 for (i = 1; i <= 32; i++) {
4519 int id1, id2;
4520 int phyaddr = i & 0x1F;
4521
4522 spin_lock_irq(&np->lock);
4523 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4524 spin_unlock_irq(&np->lock);
4525 if (id1 < 0 || id1 == 0xffff)
4526 continue;
4527 spin_lock_irq(&np->lock);
4528 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4529 spin_unlock_irq(&np->lock);
4530 if (id2 < 0 || id2 == 0xffff)
4531 continue;
4532
4533 np->phy_model = id2 & PHYID2_MODEL_MASK;
4534 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4535 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4536 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4537 pci_name(pci_dev), id1, id2, phyaddr);
4538 np->phyaddr = phyaddr;
4539 np->phy_oui = id1 | id2;
4540 break;
4541 }
4542 if (i == 33) {
4543 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4544 pci_name(pci_dev));
4545 goto out_error;
4546 }
4547
4548 /* reset it */
4549 phy_init(dev);
4550
4551 /* set default link speed settings */
4552 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4553 np->duplex = 0;
4554 np->autoneg = 1;
4555
4556 err = register_netdev(dev);
4557 if (err) {
4558 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4559 goto out_error;
4560 }
4561 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4562 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4563 pci_name(pci_dev));
4564
4565 return 0;
4566
4567 out_error:
4568 pci_set_drvdata(pci_dev, NULL);
4569 out_freering:
4570 free_rings(dev);
4571 out_unmap:
4572 iounmap(get_hwbase(dev));
4573 out_relreg:
4574 pci_release_regions(pci_dev);
4575 out_disable:
4576 pci_disable_device(pci_dev);
4577 out_free:
4578 free_netdev(dev);
4579 out:
4580 return err;
4581 }
4582
4583 static void __devexit nv_remove(struct pci_dev *pci_dev)
4584 {
4585 struct net_device *dev = pci_get_drvdata(pci_dev);
4586 struct fe_priv *np = netdev_priv(dev);
4587 u8 __iomem *base = get_hwbase(dev);
4588
4589 unregister_netdev(dev);
4590
4591 /* special op: write back the misordered MAC address - otherwise
4592 * the next nv_probe would see a wrong address.
4593 */
4594 writel(np->orig_mac[0], base + NvRegMacAddrA);
4595 writel(np->orig_mac[1], base + NvRegMacAddrB);
4596
4597 /* free all structures */
4598 free_rings(dev);
4599 iounmap(get_hwbase(dev));
4600 pci_release_regions(pci_dev);
4601 pci_disable_device(pci_dev);
4602 free_netdev(dev);
4603 pci_set_drvdata(pci_dev, NULL);
4604 }
4605
4606 static struct pci_device_id pci_tbl[] = {
4607 { /* nForce Ethernet Controller */
4608 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4609 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4610 },
4611 { /* nForce2 Ethernet Controller */
4612 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4613 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4614 },
4615 { /* nForce3 Ethernet Controller */
4616 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4617 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4618 },
4619 { /* nForce3 Ethernet Controller */
4620 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4621 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4622 },
4623 { /* nForce3 Ethernet Controller */
4624 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4625 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4626 },
4627 { /* nForce3 Ethernet Controller */
4628 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4629 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4630 },
4631 { /* nForce3 Ethernet Controller */
4632 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4633 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4634 },
4635 { /* CK804 Ethernet Controller */
4636 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4637 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4638 },
4639 { /* CK804 Ethernet Controller */
4640 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4641 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4642 },
4643 { /* MCP04 Ethernet Controller */
4644 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4645 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4646 },
4647 { /* MCP04 Ethernet Controller */
4648 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4649 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4650 },
4651 { /* MCP51 Ethernet Controller */
4652 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4653 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4654 },
4655 { /* MCP51 Ethernet Controller */
4656 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4657 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4658 },
4659 { /* MCP55 Ethernet Controller */
4660 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4661 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4662 },
4663 { /* MCP55 Ethernet Controller */
4664 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4665 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4666 },
4667 { /* MCP61 Ethernet Controller */
4668 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4669 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4670 },
4671 { /* MCP61 Ethernet Controller */
4672 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4673 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4674 },
4675 { /* MCP61 Ethernet Controller */
4676 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4677 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4678 },
4679 { /* MCP61 Ethernet Controller */
4680 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4681 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4682 },
4683 { /* MCP65 Ethernet Controller */
4684 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
4685 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4686 },
4687 { /* MCP65 Ethernet Controller */
4688 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
4689 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4690 },
4691 { /* MCP65 Ethernet Controller */
4692 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
4693 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4694 },
4695 { /* MCP65 Ethernet Controller */
4696 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
4697 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4698 },
4699 {0,},
4700 };
4701
4702 static struct pci_driver driver = {
4703 .name = "forcedeth",
4704 .id_table = pci_tbl,
4705 .probe = nv_probe,
4706 .remove = __devexit_p(nv_remove),
4707 };
4708
4709
4710 static int __init init_nic(void)
4711 {
4712 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
4713 return pci_register_driver(&driver);
4714 }
4715
4716 static void __exit exit_nic(void)
4717 {
4718 pci_unregister_driver(&driver);
4719 }
4720
4721 module_param(max_interrupt_work, int, 0);
4722 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
4723 module_param(optimization_mode, int, 0);
4724 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4725 module_param(poll_interval, int, 0);
4726 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4727 module_param(msi, int, 0);
4728 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4729 module_param(msix, int, 0);
4730 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
4731 module_param(dma_64bit, int, 0);
4732 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4733
4734 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4735 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4736 MODULE_LICENSE("GPL");
4737
4738 MODULE_DEVICE_TABLE(pci, pci_tbl);
4739
4740 module_init(init_nic);
4741 module_exit(exit_nic);
MOXA 2.6.19 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz