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MOXA linux-2.6.x / linux-2.6.19-uc1 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz
[linux-2.6.19-moxart.git] / drivers / net / amd8111e.c
blobef65e5917c8fcf7014ca97f7b72b796233d9e330
1
2 /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
3 * Copyright (C) 2004 Advanced Micro Devices
4 *
5 *
6 * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
7 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
8 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
9 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
10 * Copyright 1993 United States Government as represented by the
11 * Director, National Security Agency.[ pcnet32.c ]
12 * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
13 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
14 *
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
29 * USA
30
31 Module Name:
32
33 amd8111e.c
34
35 Abstract:
36
37 AMD8111 based 10/100 Ethernet Controller Driver.
38
39 Environment:
40
41 Kernel Mode
42
43 Revision History:
44 3.0.0
45 Initial Revision.
46 3.0.1
47 1. Dynamic interrupt coalescing.
48 2. Removed prev_stats.
49 3. MII support.
50 4. Dynamic IPG support
51 3.0.2 05/29/2003
52 1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
53 2. Bug fix: Fixed VLAN support failure.
54 3. Bug fix: Fixed receive interrupt coalescing bug.
55 4. Dynamic IPG support is disabled by default.
56 3.0.3 06/05/2003
57 1. Bug fix: Fixed failure to close the interface if SMP is enabled.
58 3.0.4 12/09/2003
59 1. Added set_mac_address routine for bonding driver support.
60 2. Tested the driver for bonding support
61 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
62 indicated to the h/w.
63 4. Modified amd8111e_rx() routine to receive all the received packets
64 in the first interrupt.
65 5. Bug fix: Corrected rx_errors reported in get_stats() function.
66 3.0.5 03/22/2004
67 1. Added NAPI support
68
69 */
70
71
72 #include <linux/module.h>
73 #include <linux/kernel.h>
74 #include <linux/types.h>
75 #include <linux/compiler.h>
76 #include <linux/slab.h>
77 #include <linux/delay.h>
78 #include <linux/init.h>
79 #include <linux/ioport.h>
80 #include <linux/pci.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/skbuff.h>
84 #include <linux/ethtool.h>
85 #include <linux/mii.h>
86 #include <linux/if_vlan.h>
87 #include <linux/ctype.h>
88 #include <linux/crc32.h>
89 #include <linux/dma-mapping.h>
90
91 #include <asm/system.h>
92 #include <asm/io.h>
93 #include <asm/byteorder.h>
94 #include <asm/uaccess.h>
95
96 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
97 #define AMD8111E_VLAN_TAG_USED 1
98 #else
99 #define AMD8111E_VLAN_TAG_USED 0
100 #endif
101
102 #include "amd8111e.h"
103 #define MODULE_NAME "amd8111e"
104 #define MODULE_VERS "3.0.6"
105 MODULE_AUTHOR("Advanced Micro Devices, Inc.");
106 MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version 3.0.6");
107 MODULE_LICENSE("GPL");
108 MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
109 module_param_array(speed_duplex, int, NULL, 0);
110 MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
111 module_param_array(coalesce, bool, NULL, 0);
112 MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
113 module_param_array(dynamic_ipg, bool, NULL, 0);
114 MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
115
116 static struct pci_device_id amd8111e_pci_tbl[] = {
117
118 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
120 { 0, }
121
122 };
123 /*
124 This function will read the PHY registers.
125 */
126 static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
127 {
128 void __iomem *mmio = lp->mmio;
129 unsigned int reg_val;
130 unsigned int repeat= REPEAT_CNT;
131
132 reg_val = readl(mmio + PHY_ACCESS);
133 while (reg_val & PHY_CMD_ACTIVE)
134 reg_val = readl( mmio + PHY_ACCESS );
135
136 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
137 ((reg & 0x1f) << 16), mmio +PHY_ACCESS);
138 do{
139 reg_val = readl(mmio + PHY_ACCESS);
140 udelay(30); /* It takes 30 us to read/write data */
141 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
142 if(reg_val & PHY_RD_ERR)
143 goto err_phy_read;
144
145 *val = reg_val & 0xffff;
146 return 0;
147 err_phy_read:
148 *val = 0;
149 return -EINVAL;
150
151 }
152
153 /*
154 This function will write into PHY registers.
155 */
156 static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
157 {
158 unsigned int repeat = REPEAT_CNT
159 void __iomem *mmio = lp->mmio;
160 unsigned int reg_val;
161
162 reg_val = readl(mmio + PHY_ACCESS);
163 while (reg_val & PHY_CMD_ACTIVE)
164 reg_val = readl( mmio + PHY_ACCESS );
165
166 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
167 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
168
169 do{
170 reg_val = readl(mmio + PHY_ACCESS);
171 udelay(30); /* It takes 30 us to read/write the data */
172 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
173
174 if(reg_val & PHY_RD_ERR)
175 goto err_phy_write;
176
177 return 0;
178
179 err_phy_write:
180 return -EINVAL;
181
182 }
183 /*
184 This is the mii register read function provided to the mii interface.
185 */
186 static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
187 {
188 struct amd8111e_priv* lp = netdev_priv(dev);
189 unsigned int reg_val;
190
191 amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
192 return reg_val;
193
194 }
195
196 /*
197 This is the mii register write function provided to the mii interface.
198 */
199 static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
200 {
201 struct amd8111e_priv* lp = netdev_priv(dev);
202
203 amd8111e_write_phy(lp, phy_id, reg_num, val);
204 }
205
206 /*
207 This function will set PHY speed. During initialization sets the original speed to 100 full.
208 */
209 static void amd8111e_set_ext_phy(struct net_device *dev)
210 {
211 struct amd8111e_priv *lp = netdev_priv(dev);
212 u32 bmcr,advert,tmp;
213
214 /* Determine mii register values to set the speed */
215 advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
216 tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
217 switch (lp->ext_phy_option){
218
219 default:
220 case SPEED_AUTONEG: /* advertise all values */
221 tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
222 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
223 break;
224 case SPEED10_HALF:
225 tmp |= ADVERTISE_10HALF;
226 break;
227 case SPEED10_FULL:
228 tmp |= ADVERTISE_10FULL;
229 break;
230 case SPEED100_HALF:
231 tmp |= ADVERTISE_100HALF;
232 break;
233 case SPEED100_FULL:
234 tmp |= ADVERTISE_100FULL;
235 break;
236 }
237
238 if(advert != tmp)
239 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
240 /* Restart auto negotiation */
241 bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
242 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
243 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
244
245 }
246
247 /*
248 This function will unmap skb->data space and will free
249 all transmit and receive skbuffs.
250 */
251 static int amd8111e_free_skbs(struct net_device *dev)
252 {
253 struct amd8111e_priv *lp = netdev_priv(dev);
254 struct sk_buff* rx_skbuff;
255 int i;
256
257 /* Freeing transmit skbs */
258 for(i = 0; i < NUM_TX_BUFFERS; i++){
259 if(lp->tx_skbuff[i]){
260 pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
261 dev_kfree_skb (lp->tx_skbuff[i]);
262 lp->tx_skbuff[i] = NULL;
263 lp->tx_dma_addr[i] = 0;
264 }
265 }
266 /* Freeing previously allocated receive buffers */
267 for (i = 0; i < NUM_RX_BUFFERS; i++){
268 rx_skbuff = lp->rx_skbuff[i];
269 if(rx_skbuff != NULL){
270 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
271 lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
272 dev_kfree_skb(lp->rx_skbuff[i]);
273 lp->rx_skbuff[i] = NULL;
274 lp->rx_dma_addr[i] = 0;
275 }
276 }
277
278 return 0;
279 }
280
281 /*
282 This will set the receive buffer length corresponding to the mtu size of networkinterface.
283 */
284 static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
285 {
286 struct amd8111e_priv* lp = netdev_priv(dev);
287 unsigned int mtu = dev->mtu;
288
289 if (mtu > ETH_DATA_LEN){
290 /* MTU + ethernet header + FCS
291 + optional VLAN tag + skb reserve space 2 */
292
293 lp->rx_buff_len = mtu + ETH_HLEN + 10;
294 lp->options |= OPTION_JUMBO_ENABLE;
295 } else{
296 lp->rx_buff_len = PKT_BUFF_SZ;
297 lp->options &= ~OPTION_JUMBO_ENABLE;
298 }
299 }
300
301 /*
302 This function will free all the previously allocated buffers, determine new receive buffer length and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
303 */
304 static int amd8111e_init_ring(struct net_device *dev)
305 {
306 struct amd8111e_priv *lp = netdev_priv(dev);
307 int i;
308
309 lp->rx_idx = lp->tx_idx = 0;
310 lp->tx_complete_idx = 0;
311 lp->tx_ring_idx = 0;
312
313
314 if(lp->opened)
315 /* Free previously allocated transmit and receive skbs */
316 amd8111e_free_skbs(dev);
317
318 else{
319 /* allocate the tx and rx descriptors */
320 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
321 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
322 &lp->tx_ring_dma_addr)) == NULL)
323
324 goto err_no_mem;
325
326 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
327 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
328 &lp->rx_ring_dma_addr)) == NULL)
329
330 goto err_free_tx_ring;
331
332 }
333 /* Set new receive buff size */
334 amd8111e_set_rx_buff_len(dev);
335
336 /* Allocating receive skbs */
337 for (i = 0; i < NUM_RX_BUFFERS; i++) {
338
339 if (!(lp->rx_skbuff[i] = dev_alloc_skb(lp->rx_buff_len))) {
340 /* Release previos allocated skbs */
341 for(--i; i >= 0 ;i--)
342 dev_kfree_skb(lp->rx_skbuff[i]);
343 goto err_free_rx_ring;
344 }
345 skb_reserve(lp->rx_skbuff[i],2);
346 }
347 /* Initilaizing receive descriptors */
348 for (i = 0; i < NUM_RX_BUFFERS; i++) {
349 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
350 lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
351
352 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
353 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
354 wmb();
355 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
356 }
357
358 /* Initializing transmit descriptors */
359 for (i = 0; i < NUM_TX_RING_DR; i++) {
360 lp->tx_ring[i].buff_phy_addr = 0;
361 lp->tx_ring[i].tx_flags = 0;
362 lp->tx_ring[i].buff_count = 0;
363 }
364
365 return 0;
366
367 err_free_rx_ring:
368
369 pci_free_consistent(lp->pci_dev,
370 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
371 lp->rx_ring_dma_addr);
372
373 err_free_tx_ring:
374
375 pci_free_consistent(lp->pci_dev,
376 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
377 lp->tx_ring_dma_addr);
378
379 err_no_mem:
380 return -ENOMEM;
381 }
382 /* This function will set the interrupt coalescing according to the input arguments */
383 static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
384 {
385 unsigned int timeout;
386 unsigned int event_count;
387
388 struct amd8111e_priv *lp = netdev_priv(dev);
389 void __iomem *mmio = lp->mmio;
390 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
391
392
393 switch(cmod)
394 {
395 case RX_INTR_COAL :
396 timeout = coal_conf->rx_timeout;
397 event_count = coal_conf->rx_event_count;
398 if( timeout > MAX_TIMEOUT ||
399 event_count > MAX_EVENT_COUNT )
400 return -EINVAL;
401
402 timeout = timeout * DELAY_TIMER_CONV;
403 writel(VAL0|STINTEN, mmio+INTEN0);
404 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
405 mmio+DLY_INT_A);
406 break;
407
408 case TX_INTR_COAL :
409 timeout = coal_conf->tx_timeout;
410 event_count = coal_conf->tx_event_count;
411 if( timeout > MAX_TIMEOUT ||
412 event_count > MAX_EVENT_COUNT )
413 return -EINVAL;
414
415
416 timeout = timeout * DELAY_TIMER_CONV;
417 writel(VAL0|STINTEN,mmio+INTEN0);
418 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
419 mmio+DLY_INT_B);
420 break;
421
422 case DISABLE_COAL:
423 writel(0,mmio+STVAL);
424 writel(STINTEN, mmio+INTEN0);
425 writel(0, mmio +DLY_INT_B);
426 writel(0, mmio+DLY_INT_A);
427 break;
428 case ENABLE_COAL:
429 /* Start the timer */
430 writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */
431 writel(VAL0|STINTEN, mmio+INTEN0);
432 break;
433 default:
434 break;
435
436 }
437 return 0;
438
439 }
440
441 /*
442 This function initializes the device registers and starts the device.
443 */
444 static int amd8111e_restart(struct net_device *dev)
445 {
446 struct amd8111e_priv *lp = netdev_priv(dev);
447 void __iomem *mmio = lp->mmio;
448 int i,reg_val;
449
450 /* stop the chip */
451 writel(RUN, mmio + CMD0);
452
453 if(amd8111e_init_ring(dev))
454 return -ENOMEM;
455
456 /* enable the port manager and set auto negotiation always */
457 writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
458 writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
459
460 amd8111e_set_ext_phy(dev);
461
462 /* set control registers */
463 reg_val = readl(mmio + CTRL1);
464 reg_val &= ~XMTSP_MASK;
465 writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
466
467 /* enable interrupt */
468 writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
469 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
470 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
471
472 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
473
474 /* initialize tx and rx ring base addresses */
475 writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
476 writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
477
478 writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
479 writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
480
481 /* set default IPG to 96 */
482 writew((u32)DEFAULT_IPG,mmio+IPG);
483 writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
484
485 if(lp->options & OPTION_JUMBO_ENABLE){
486 writel((u32)VAL2|JUMBO, mmio + CMD3);
487 /* Reset REX_UFLO */
488 writel( REX_UFLO, mmio + CMD2);
489 /* Should not set REX_UFLO for jumbo frames */
490 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
491 }else{
492 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
493 writel((u32)JUMBO, mmio + CMD3);
494 }
495
496 #if AMD8111E_VLAN_TAG_USED
497 writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
498 #endif
499 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
500
501 /* Setting the MAC address to the device */
502 for(i = 0; i < ETH_ADDR_LEN; i++)
503 writeb( dev->dev_addr[i], mmio + PADR + i );
504
505 /* Enable interrupt coalesce */
506 if(lp->options & OPTION_INTR_COAL_ENABLE){
507 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
508 dev->name);
509 amd8111e_set_coalesce(dev,ENABLE_COAL);
510 }
511
512 /* set RUN bit to start the chip */
513 writel(VAL2 | RDMD0, mmio + CMD0);
514 writel(VAL0 | INTREN | RUN, mmio + CMD0);
515
516 /* To avoid PCI posting bug */
517 readl(mmio+CMD0);
518 return 0;
519 }
520 /*
521 This function clears necessary the device registers.
522 */
523 static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
524 {
525 unsigned int reg_val;
526 unsigned int logic_filter[2] ={0,};
527 void __iomem *mmio = lp->mmio;
528
529
530 /* stop the chip */
531 writel(RUN, mmio + CMD0);
532
533 /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
534 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
535
536 /* Clear RCV_RING_BASE_ADDR */
537 writel(0, mmio + RCV_RING_BASE_ADDR0);
538
539 /* Clear XMT_RING_BASE_ADDR */
540 writel(0, mmio + XMT_RING_BASE_ADDR0);
541 writel(0, mmio + XMT_RING_BASE_ADDR1);
542 writel(0, mmio + XMT_RING_BASE_ADDR2);
543 writel(0, mmio + XMT_RING_BASE_ADDR3);
544
545 /* Clear CMD0 */
546 writel(CMD0_CLEAR,mmio + CMD0);
547
548 /* Clear CMD2 */
549 writel(CMD2_CLEAR, mmio +CMD2);
550
551 /* Clear CMD7 */
552 writel(CMD7_CLEAR , mmio + CMD7);
553
554 /* Clear DLY_INT_A and DLY_INT_B */
555 writel(0x0, mmio + DLY_INT_A);
556 writel(0x0, mmio + DLY_INT_B);
557
558 /* Clear FLOW_CONTROL */
559 writel(0x0, mmio + FLOW_CONTROL);
560
561 /* Clear INT0 write 1 to clear register */
562 reg_val = readl(mmio + INT0);
563 writel(reg_val, mmio + INT0);
564
565 /* Clear STVAL */
566 writel(0x0, mmio + STVAL);
567
568 /* Clear INTEN0 */
569 writel( INTEN0_CLEAR, mmio + INTEN0);
570
571 /* Clear LADRF */
572 writel(0x0 , mmio + LADRF);
573
574 /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
575 writel( 0x80010,mmio + SRAM_SIZE);
576
577 /* Clear RCV_RING0_LEN */
578 writel(0x0, mmio + RCV_RING_LEN0);
579
580 /* Clear XMT_RING0/1/2/3_LEN */
581 writel(0x0, mmio + XMT_RING_LEN0);
582 writel(0x0, mmio + XMT_RING_LEN1);
583 writel(0x0, mmio + XMT_RING_LEN2);
584 writel(0x0, mmio + XMT_RING_LEN3);
585
586 /* Clear XMT_RING_LIMIT */
587 writel(0x0, mmio + XMT_RING_LIMIT);
588
589 /* Clear MIB */
590 writew(MIB_CLEAR, mmio + MIB_ADDR);
591
592 /* Clear LARF */
593 amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
594
595 /* SRAM_SIZE register */
596 reg_val = readl(mmio + SRAM_SIZE);
597
598 if(lp->options & OPTION_JUMBO_ENABLE)
599 writel( VAL2|JUMBO, mmio + CMD3);
600 #if AMD8111E_VLAN_TAG_USED
601 writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
602 #endif
603 /* Set default value to CTRL1 Register */
604 writel(CTRL1_DEFAULT, mmio + CTRL1);
605
606 /* To avoid PCI posting bug */
607 readl(mmio + CMD2);
608
609 }
610
611 /*
612 This function disables the interrupt and clears all the pending
613 interrupts in INT0
614 */
615 static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
616 {
617 u32 intr0;
618
619 /* Disable interrupt */
620 writel(INTREN, lp->mmio + CMD0);
621
622 /* Clear INT0 */
623 intr0 = readl(lp->mmio + INT0);
624 writel(intr0, lp->mmio + INT0);
625
626 /* To avoid PCI posting bug */
627 readl(lp->mmio + INT0);
628
629 }
630
631 /*
632 This function stops the chip.
633 */
634 static void amd8111e_stop_chip(struct amd8111e_priv* lp)
635 {
636 writel(RUN, lp->mmio + CMD0);
637
638 /* To avoid PCI posting bug */
639 readl(lp->mmio + CMD0);
640 }
641
642 /*
643 This function frees the transmiter and receiver descriptor rings.
644 */
645 static void amd8111e_free_ring(struct amd8111e_priv* lp)
646 {
647
648 /* Free transmit and receive skbs */
649 amd8111e_free_skbs(lp->amd8111e_net_dev);
650
651 /* Free transmit and receive descriptor rings */
652 if(lp->rx_ring){
653 pci_free_consistent(lp->pci_dev,
654 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
655 lp->rx_ring, lp->rx_ring_dma_addr);
656 lp->rx_ring = NULL;
657 }
658
659 if(lp->tx_ring){
660 pci_free_consistent(lp->pci_dev,
661 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
662 lp->tx_ring, lp->tx_ring_dma_addr);
663
664 lp->tx_ring = NULL;
665 }
666
667 }
668 #if AMD8111E_VLAN_TAG_USED
669 /*
670 This is the receive indication function for packets with vlan tag.
671 */
672 static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag)
673 {
674 #ifdef CONFIG_AMD8111E_NAPI
675 return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag);
676 #else
677 return vlan_hwaccel_rx(skb, lp->vlgrp, vlan_tag);
678 #endif /* CONFIG_AMD8111E_NAPI */
679 }
680 #endif
681
682 /*
683 This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb.
684 */
685 static int amd8111e_tx(struct net_device *dev)
686 {
687 struct amd8111e_priv* lp = netdev_priv(dev);
688 int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
689 int status;
690 /* Complete all the transmit packet */
691 while (lp->tx_complete_idx != lp->tx_idx){
692 tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
693 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
694
695 if(status & OWN_BIT)
696 break; /* It still hasn't been Txed */
697
698 lp->tx_ring[tx_index].buff_phy_addr = 0;
699
700 /* We must free the original skb */
701 if (lp->tx_skbuff[tx_index]) {
702 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
703 lp->tx_skbuff[tx_index]->len,
704 PCI_DMA_TODEVICE);
705 dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
706 lp->tx_skbuff[tx_index] = NULL;
707 lp->tx_dma_addr[tx_index] = 0;
708 }
709 lp->tx_complete_idx++;
710 /*COAL update tx coalescing parameters */
711 lp->coal_conf.tx_packets++;
712 lp->coal_conf.tx_bytes += lp->tx_ring[tx_index].buff_count;
713
714 if (netif_queue_stopped(dev) &&
715 lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
716 /* The ring is no longer full, clear tbusy. */
717 /* lp->tx_full = 0; */
718 netif_wake_queue (dev);
719 }
720 }
721 return 0;
722 }
723
724 #ifdef CONFIG_AMD8111E_NAPI
725 /* This function handles the driver receive operation in polling mode */
726 static int amd8111e_rx_poll(struct net_device *dev, int * budget)
727 {
728 struct amd8111e_priv *lp = netdev_priv(dev);
729 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
730 void __iomem *mmio = lp->mmio;
731 struct sk_buff *skb,*new_skb;
732 int min_pkt_len, status;
733 unsigned int intr0;
734 int num_rx_pkt = 0;
735 /*int max_rx_pkt = NUM_RX_BUFFERS;*/
736 short pkt_len;
737 #if AMD8111E_VLAN_TAG_USED
738 short vtag;
739 #endif
740 int rx_pkt_limit = dev->quota;
741 unsigned long flags;
742
743 do{
744 /* process receive packets until we use the quota*/
745 /* If we own the next entry, it's a new packet. Send it up. */
746 while(1) {
747 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
748 if (status & OWN_BIT)
749 break;
750
751 /*
752 * There is a tricky error noted by John Murphy,
753 * <murf@perftech.com> to Russ Nelson: Even with
754 * full-sized * buffers it's possible for a
755 * jabber packet to use two buffers, with only
756 * the last correctly noting the error.
757 */
758
759 if(status & ERR_BIT) {
760 /* reseting flags */
761 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
762 goto err_next_pkt;
763 }
764 /* check for STP and ENP */
765 if(!((status & STP_BIT) && (status & ENP_BIT))){
766 /* reseting flags */
767 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
768 goto err_next_pkt;
769 }
770 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
771
772 #if AMD8111E_VLAN_TAG_USED
773 vtag = status & TT_MASK;
774 /*MAC will strip vlan tag*/
775 if(lp->vlgrp != NULL && vtag !=0)
776 min_pkt_len =MIN_PKT_LEN - 4;
777 else
778 #endif
779 min_pkt_len =MIN_PKT_LEN;
780
781 if (pkt_len < min_pkt_len) {
782 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
783 lp->drv_rx_errors++;
784 goto err_next_pkt;
785 }
786 if(--rx_pkt_limit < 0)
787 goto rx_not_empty;
788 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
789 /* if allocation fail,
790 ignore that pkt and go to next one */
791 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
792 lp->drv_rx_errors++;
793 goto err_next_pkt;
794 }
795
796 skb_reserve(new_skb, 2);
797 skb = lp->rx_skbuff[rx_index];
798 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
799 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
800 skb_put(skb, pkt_len);
801 skb->dev = dev;
802 lp->rx_skbuff[rx_index] = new_skb;
803 new_skb->dev = dev;
804 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
805 new_skb->data,
806 lp->rx_buff_len-2,
807 PCI_DMA_FROMDEVICE);
808
809 skb->protocol = eth_type_trans(skb, dev);
810
811 #if AMD8111E_VLAN_TAG_USED
812 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
813 amd8111e_vlan_rx(lp, skb,
814 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
815 } else
816 #endif
817 netif_receive_skb(skb);
818 /*COAL update rx coalescing parameters*/
819 lp->coal_conf.rx_packets++;
820 lp->coal_conf.rx_bytes += pkt_len;
821 num_rx_pkt++;
822 dev->last_rx = jiffies;
823
824 err_next_pkt:
825 lp->rx_ring[rx_index].buff_phy_addr
826 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
827 lp->rx_ring[rx_index].buff_count =
828 cpu_to_le16(lp->rx_buff_len-2);
829 wmb();
830 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
831 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
832 }
833 /* Check the interrupt status register for more packets in the
834 mean time. Process them since we have not used up our quota.*/
835
836 intr0 = readl(mmio + INT0);
837 /*Ack receive packets */
838 writel(intr0 & RINT0,mmio + INT0);
839
840 } while(intr0 & RINT0);
841
842 /* Receive descriptor is empty now */
843 dev->quota -= num_rx_pkt;
844 *budget -= num_rx_pkt;
845
846 spin_lock_irqsave(&lp->lock, flags);
847 netif_rx_complete(dev);
848 writel(VAL0|RINTEN0, mmio + INTEN0);
849 writel(VAL2 | RDMD0, mmio + CMD0);
850 spin_unlock_irqrestore(&lp->lock, flags);
851 return 0;
852
853 rx_not_empty:
854 /* Do not call a netif_rx_complete */
855 dev->quota -= num_rx_pkt;
856 *budget -= num_rx_pkt;
857 return 1;
858 }
859
860 #else
861 /*
862 This function will check the ownership of receive buffers and descriptors. It will indicate to kernel up to half the number of maximum receive buffers in the descriptor ring, in a single receive interrupt. It will also replenish the descriptors with new skbs.
863 */
864 static int amd8111e_rx(struct net_device *dev)
865 {
866 struct amd8111e_priv *lp = netdev_priv(dev);
867 struct sk_buff *skb,*new_skb;
868 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
869 int min_pkt_len, status;
870 int num_rx_pkt = 0;
871 int max_rx_pkt = NUM_RX_BUFFERS;
872 short pkt_len;
873 #if AMD8111E_VLAN_TAG_USED
874 short vtag;
875 #endif
876
877 /* If we own the next entry, it's a new packet. Send it up. */
878 while(++num_rx_pkt <= max_rx_pkt){
879 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
880 if(status & OWN_BIT)
881 return 0;
882
883 /* check if err summary bit is set */
884 if(status & ERR_BIT){
885 /*
886 * There is a tricky error noted by John Murphy,
887 * <murf@perftech.com> to Russ Nelson: Even with full-sized
888 * buffers it's possible for a jabber packet to use two
889 * buffers, with only the last correctly noting the error. */
890 /* reseting flags */
891 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
892 goto err_next_pkt;
893 }
894 /* check for STP and ENP */
895 if(!((status & STP_BIT) && (status & ENP_BIT))){
896 /* reseting flags */
897 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
898 goto err_next_pkt;
899 }
900 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
901
902 #if AMD8111E_VLAN_TAG_USED
903 vtag = status & TT_MASK;
904 /*MAC will strip vlan tag*/
905 if(lp->vlgrp != NULL && vtag !=0)
906 min_pkt_len =MIN_PKT_LEN - 4;
907 else
908 #endif
909 min_pkt_len =MIN_PKT_LEN;
910
911 if (pkt_len < min_pkt_len) {
912 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
913 lp->drv_rx_errors++;
914 goto err_next_pkt;
915 }
916 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
917 /* if allocation fail,
918 ignore that pkt and go to next one */
919 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
920 lp->drv_rx_errors++;
921 goto err_next_pkt;
922 }
923
924 skb_reserve(new_skb, 2);
925 skb = lp->rx_skbuff[rx_index];
926 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
927 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
928 skb_put(skb, pkt_len);
929 skb->dev = dev;
930 lp->rx_skbuff[rx_index] = new_skb;
931 new_skb->dev = dev;
932 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
933 new_skb->data, lp->rx_buff_len-2,PCI_DMA_FROMDEVICE);
934
935 skb->protocol = eth_type_trans(skb, dev);
936
937 #if AMD8111E_VLAN_TAG_USED
938 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
939 amd8111e_vlan_rx(lp, skb,
940 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
941 } else
942 #endif
943
944 netif_rx (skb);
945 /*COAL update rx coalescing parameters*/
946 lp->coal_conf.rx_packets++;
947 lp->coal_conf.rx_bytes += pkt_len;
948
949 dev->last_rx = jiffies;
950
951 err_next_pkt:
952 lp->rx_ring[rx_index].buff_phy_addr
953 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
954 lp->rx_ring[rx_index].buff_count =
955 cpu_to_le16(lp->rx_buff_len-2);
956 wmb();
957 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
958 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
959 }
960
961 return 0;
962 }
963 #endif /* CONFIG_AMD8111E_NAPI */
964 /*
965 This function will indicate the link status to the kernel.
966 */
967 static int amd8111e_link_change(struct net_device* dev)
968 {
969 struct amd8111e_priv *lp = netdev_priv(dev);
970 int status0,speed;
971
972 /* read the link change */
973 status0 = readl(lp->mmio + STAT0);
974
975 if(status0 & LINK_STATS){
976 if(status0 & AUTONEG_COMPLETE)
977 lp->link_config.autoneg = AUTONEG_ENABLE;
978 else
979 lp->link_config.autoneg = AUTONEG_DISABLE;
980
981 if(status0 & FULL_DPLX)
982 lp->link_config.duplex = DUPLEX_FULL;
983 else
984 lp->link_config.duplex = DUPLEX_HALF;
985 speed = (status0 & SPEED_MASK) >> 7;
986 if(speed == PHY_SPEED_10)
987 lp->link_config.speed = SPEED_10;
988 else if(speed == PHY_SPEED_100)
989 lp->link_config.speed = SPEED_100;
990
991 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n", dev->name,
992 (lp->link_config.speed == SPEED_100) ? "100": "10",
993 (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half");
994 netif_carrier_on(dev);
995 }
996 else{
997 lp->link_config.speed = SPEED_INVALID;
998 lp->link_config.duplex = DUPLEX_INVALID;
999 lp->link_config.autoneg = AUTONEG_INVALID;
1000 printk(KERN_INFO "%s: Link is Down.\n",dev->name);
1001 netif_carrier_off(dev);
1002 }
1003
1004 return 0;
1005 }
1006 /*
1007 This function reads the mib counters.
1008 */
1009 static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
1010 {
1011 unsigned int status;
1012 unsigned int data;
1013 unsigned int repeat = REPEAT_CNT;
1014
1015 writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
1016 do {
1017 status = readw(mmio + MIB_ADDR);
1018 udelay(2); /* controller takes MAX 2 us to get mib data */
1019 }
1020 while (--repeat && (status & MIB_CMD_ACTIVE));
1021
1022 data = readl(mmio + MIB_DATA);
1023 return data;
1024 }
1025
1026 /*
1027 This function reads the mib registers and returns the hardware statistics. It updates previous internal driver statistics with new values.
1028 */
1029 static struct net_device_stats *amd8111e_get_stats(struct net_device * dev)
1030 {
1031 struct amd8111e_priv *lp = netdev_priv(dev);
1032 void __iomem *mmio = lp->mmio;
1033 unsigned long flags;
1034 /* struct net_device_stats *prev_stats = &lp->prev_stats; */
1035 struct net_device_stats* new_stats = &lp->stats;
1036
1037 if(!lp->opened)
1038 return &lp->stats;
1039 spin_lock_irqsave (&lp->lock, flags);
1040
1041 /* stats.rx_packets */
1042 new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
1043 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
1044 amd8111e_read_mib(mmio, rcv_unicast_pkts);
1045
1046 /* stats.tx_packets */
1047 new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
1048
1049 /*stats.rx_bytes */
1050 new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
1051
1052 /* stats.tx_bytes */
1053 new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
1054
1055 /* stats.rx_errors */
1056 /* hw errors + errors driver reported */
1057 new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1058 amd8111e_read_mib(mmio, rcv_fragments)+
1059 amd8111e_read_mib(mmio, rcv_jabbers)+
1060 amd8111e_read_mib(mmio, rcv_alignment_errors)+
1061 amd8111e_read_mib(mmio, rcv_fcs_errors)+
1062 amd8111e_read_mib(mmio, rcv_miss_pkts)+
1063 lp->drv_rx_errors;
1064
1065 /* stats.tx_errors */
1066 new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1067
1068 /* stats.rx_dropped*/
1069 new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
1070
1071 /* stats.tx_dropped*/
1072 new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1073
1074 /* stats.multicast*/
1075 new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
1076
1077 /* stats.collisions*/
1078 new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
1079
1080 /* stats.rx_length_errors*/
1081 new_stats->rx_length_errors =
1082 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1083 amd8111e_read_mib(mmio, rcv_oversize_pkts);
1084
1085 /* stats.rx_over_errors*/
1086 new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1087
1088 /* stats.rx_crc_errors*/
1089 new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
1090
1091 /* stats.rx_frame_errors*/
1092 new_stats->rx_frame_errors =
1093 amd8111e_read_mib(mmio, rcv_alignment_errors);
1094
1095 /* stats.rx_fifo_errors */
1096 new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1097
1098 /* stats.rx_missed_errors */
1099 new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1100
1101 /* stats.tx_aborted_errors*/
1102 new_stats->tx_aborted_errors =
1103 amd8111e_read_mib(mmio, xmt_excessive_collision);
1104
1105 /* stats.tx_carrier_errors*/
1106 new_stats->tx_carrier_errors =
1107 amd8111e_read_mib(mmio, xmt_loss_carrier);
1108
1109 /* stats.tx_fifo_errors*/
1110 new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1111
1112 /* stats.tx_window_errors*/
1113 new_stats->tx_window_errors =
1114 amd8111e_read_mib(mmio, xmt_late_collision);
1115
1116 /* Reset the mibs for collecting new statistics */
1117 /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
1118
1119 spin_unlock_irqrestore (&lp->lock, flags);
1120
1121 return new_stats;
1122 }
1123 /* This function recalculate the interupt coalescing mode on every interrupt
1124 according to the datarate and the packet rate.
1125 */
1126 static int amd8111e_calc_coalesce(struct net_device *dev)
1127 {
1128 struct amd8111e_priv *lp = netdev_priv(dev);
1129 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
1130 int tx_pkt_rate;
1131 int rx_pkt_rate;
1132 int tx_data_rate;
1133 int rx_data_rate;
1134 int rx_pkt_size;
1135 int tx_pkt_size;
1136
1137 tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
1138 coal_conf->tx_prev_packets = coal_conf->tx_packets;
1139
1140 tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
1141 coal_conf->tx_prev_bytes = coal_conf->tx_bytes;
1142
1143 rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
1144 coal_conf->rx_prev_packets = coal_conf->rx_packets;
1145
1146 rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
1147 coal_conf->rx_prev_bytes = coal_conf->rx_bytes;
1148
1149 if(rx_pkt_rate < 800){
1150 if(coal_conf->rx_coal_type != NO_COALESCE){
1151
1152 coal_conf->rx_timeout = 0x0;
1153 coal_conf->rx_event_count = 0;
1154 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1155 coal_conf->rx_coal_type = NO_COALESCE;
1156 }
1157 }
1158 else{
1159
1160 rx_pkt_size = rx_data_rate/rx_pkt_rate;
1161 if (rx_pkt_size < 128){
1162 if(coal_conf->rx_coal_type != NO_COALESCE){
1163
1164 coal_conf->rx_timeout = 0;
1165 coal_conf->rx_event_count = 0;
1166 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1167 coal_conf->rx_coal_type = NO_COALESCE;
1168 }
1169
1170 }
1171 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
1172
1173 if(coal_conf->rx_coal_type != LOW_COALESCE){
1174 coal_conf->rx_timeout = 1;
1175 coal_conf->rx_event_count = 4;
1176 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1177 coal_conf->rx_coal_type = LOW_COALESCE;
1178 }
1179 }
1180 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
1181
1182 if(coal_conf->rx_coal_type != MEDIUM_COALESCE){
1183 coal_conf->rx_timeout = 1;
1184 coal_conf->rx_event_count = 4;
1185 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1186 coal_conf->rx_coal_type = MEDIUM_COALESCE;
1187 }
1188
1189 }
1190 else if(rx_pkt_size >= 1024){
1191 if(coal_conf->rx_coal_type != HIGH_COALESCE){
1192 coal_conf->rx_timeout = 2;
1193 coal_conf->rx_event_count = 3;
1194 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1195 coal_conf->rx_coal_type = HIGH_COALESCE;
1196 }
1197 }
1198 }
1199 /* NOW FOR TX INTR COALESC */
1200 if(tx_pkt_rate < 800){
1201 if(coal_conf->tx_coal_type != NO_COALESCE){
1202
1203 coal_conf->tx_timeout = 0x0;
1204 coal_conf->tx_event_count = 0;
1205 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1206 coal_conf->tx_coal_type = NO_COALESCE;
1207 }
1208 }
1209 else{
1210
1211 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1212 if (tx_pkt_size < 128){
1213
1214 if(coal_conf->tx_coal_type != NO_COALESCE){
1215
1216 coal_conf->tx_timeout = 0;
1217 coal_conf->tx_event_count = 0;
1218 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1219 coal_conf->tx_coal_type = NO_COALESCE;
1220 }
1221
1222 }
1223 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
1224
1225 if(coal_conf->tx_coal_type != LOW_COALESCE){
1226 coal_conf->tx_timeout = 1;
1227 coal_conf->tx_event_count = 2;
1228 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1229 coal_conf->tx_coal_type = LOW_COALESCE;
1230
1231 }
1232 }
1233 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
1234
1235 if(coal_conf->tx_coal_type != MEDIUM_COALESCE){
1236 coal_conf->tx_timeout = 2;
1237 coal_conf->tx_event_count = 5;
1238 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1239 coal_conf->tx_coal_type = MEDIUM_COALESCE;
1240 }
1241
1242 }
1243 else if(tx_pkt_size >= 1024){
1244 if (tx_pkt_size >= 1024){
1245 if(coal_conf->tx_coal_type != HIGH_COALESCE){
1246 coal_conf->tx_timeout = 4;
1247 coal_conf->tx_event_count = 8;
1248 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1249 coal_conf->tx_coal_type = HIGH_COALESCE;
1250 }
1251 }
1252 }
1253 }
1254 return 0;
1255
1256 }
1257 /*
1258 This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
1259 */
1260 static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1261 {
1262
1263 struct net_device * dev = (struct net_device *) dev_id;
1264 struct amd8111e_priv *lp = netdev_priv(dev);
1265 void __iomem *mmio = lp->mmio;
1266 unsigned int intr0, intren0;
1267 unsigned int handled = 1;
1268
1269 if(unlikely(dev == NULL))
1270 return IRQ_NONE;
1271
1272 spin_lock(&lp->lock);
1273
1274 /* disabling interrupt */
1275 writel(INTREN, mmio + CMD0);
1276
1277 /* Read interrupt status */
1278 intr0 = readl(mmio + INT0);
1279 intren0 = readl(mmio + INTEN0);
1280
1281 /* Process all the INT event until INTR bit is clear. */
1282
1283 if (!(intr0 & INTR)){
1284 handled = 0;
1285 goto err_no_interrupt;
1286 }
1287
1288 /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1289 writel(intr0, mmio + INT0);
1290
1291 /* Check if Receive Interrupt has occurred. */
1292 #ifdef CONFIG_AMD8111E_NAPI
1293 if(intr0 & RINT0){
1294 if(netif_rx_schedule_prep(dev)){
1295 /* Disable receive interupts */
1296 writel(RINTEN0, mmio + INTEN0);
1297 /* Schedule a polling routine */
1298 __netif_rx_schedule(dev);
1299 }
1300 else if (intren0 & RINTEN0) {
1301 printk("************Driver bug! \
1302 interrupt while in poll\n");
1303 /* Fix by disable receive interrupts */
1304 writel(RINTEN0, mmio + INTEN0);
1305 }
1306 }
1307 #else
1308 if(intr0 & RINT0){
1309 amd8111e_rx(dev);
1310 writel(VAL2 | RDMD0, mmio + CMD0);
1311 }
1312 #endif /* CONFIG_AMD8111E_NAPI */
1313 /* Check if Transmit Interrupt has occurred. */
1314 if(intr0 & TINT0)
1315 amd8111e_tx(dev);
1316
1317 /* Check if Link Change Interrupt has occurred. */
1318 if (intr0 & LCINT)
1319 amd8111e_link_change(dev);
1320
1321 /* Check if Hardware Timer Interrupt has occurred. */
1322 if (intr0 & STINT)
1323 amd8111e_calc_coalesce(dev);
1324
1325 err_no_interrupt:
1326 writel( VAL0 | INTREN,mmio + CMD0);
1327
1328 spin_unlock(&lp->lock);
1329
1330 return IRQ_RETVAL(handled);
1331 }
1332
1333 #ifdef CONFIG_NET_POLL_CONTROLLER
1334 static void amd8111e_poll(struct net_device *dev)
1335 {
1336 unsigned long flags;
1337 local_save_flags(flags);
1338 local_irq_disable();
1339 amd8111e_interrupt(0, dev);
1340 local_irq_restore(flags);
1341 }
1342 #endif
1343
1344
1345 /*
1346 This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
1347 */
1348 static int amd8111e_close(struct net_device * dev)
1349 {
1350 struct amd8111e_priv *lp = netdev_priv(dev);
1351 netif_stop_queue(dev);
1352
1353 spin_lock_irq(&lp->lock);
1354
1355 amd8111e_disable_interrupt(lp);
1356 amd8111e_stop_chip(lp);
1357 amd8111e_free_ring(lp);
1358
1359 netif_carrier_off(lp->amd8111e_net_dev);
1360
1361 /* Delete ipg timer */
1362 if(lp->options & OPTION_DYN_IPG_ENABLE)
1363 del_timer_sync(&lp->ipg_data.ipg_timer);
1364
1365 spin_unlock_irq(&lp->lock);
1366 free_irq(dev->irq, dev);
1367
1368 /* Update the statistics before closing */
1369 amd8111e_get_stats(dev);
1370 lp->opened = 0;
1371 return 0;
1372 }
1373 /* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device.
1374 */
1375 static int amd8111e_open(struct net_device * dev )
1376 {
1377 struct amd8111e_priv *lp = netdev_priv(dev);
1378
1379 if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED,
1380 dev->name, dev))
1381 return -EAGAIN;
1382
1383 spin_lock_irq(&lp->lock);
1384
1385 amd8111e_init_hw_default(lp);
1386
1387 if(amd8111e_restart(dev)){
1388 spin_unlock_irq(&lp->lock);
1389 if (dev->irq)
1390 free_irq(dev->irq, dev);
1391 return -ENOMEM;
1392 }
1393 /* Start ipg timer */
1394 if(lp->options & OPTION_DYN_IPG_ENABLE){
1395 add_timer(&lp->ipg_data.ipg_timer);
1396 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
1397 }
1398
1399 lp->opened = 1;
1400
1401 spin_unlock_irq(&lp->lock);
1402
1403 netif_start_queue(dev);
1404
1405 return 0;
1406 }
1407 /*
1408 This function checks if there is any transmit descriptors available to queue more packet.
1409 */
1410 static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp )
1411 {
1412 int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1413 if(lp->tx_skbuff[tx_index] != 0)
1414 return -1;
1415 else
1416 return 0;
1417
1418 }
1419 /*
1420 This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
1421 */
1422
1423 static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
1424 {
1425 struct amd8111e_priv *lp = netdev_priv(dev);
1426 int tx_index;
1427 unsigned long flags;
1428
1429 spin_lock_irqsave(&lp->lock, flags);
1430
1431 tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1432
1433 lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1434
1435 lp->tx_skbuff[tx_index] = skb;
1436 lp->tx_ring[tx_index].tx_flags = 0;
1437
1438 #if AMD8111E_VLAN_TAG_USED
1439 if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
1440 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1441 cpu_to_le16(TCC_VLAN_INSERT);
1442 lp->tx_ring[tx_index].tag_ctrl_info =
1443 cpu_to_le16(vlan_tx_tag_get(skb));
1444
1445 }
1446 #endif
1447 lp->tx_dma_addr[tx_index] =
1448 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1449 lp->tx_ring[tx_index].buff_phy_addr =
1450 (u32) cpu_to_le32(lp->tx_dma_addr[tx_index]);
1451
1452 /* Set FCS and LTINT bits */
1453 wmb();
1454 lp->tx_ring[tx_index].tx_flags |=
1455 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1456
1457 lp->tx_idx++;
1458
1459 /* Trigger an immediate send poll. */
1460 writel( VAL1 | TDMD0, lp->mmio + CMD0);
1461 writel( VAL2 | RDMD0,lp->mmio + CMD0);
1462
1463 dev->trans_start = jiffies;
1464
1465 if(amd8111e_tx_queue_avail(lp) < 0){
1466 netif_stop_queue(dev);
1467 }
1468 spin_unlock_irqrestore(&lp->lock, flags);
1469 return 0;
1470 }
1471 /*
1472 This function returns all the memory mapped registers of the device.
1473 */
1474 static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1475 {
1476 void __iomem *mmio = lp->mmio;
1477 /* Read only necessary registers */
1478 buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1479 buf[1] = readl(mmio + XMT_RING_LEN0);
1480 buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1481 buf[3] = readl(mmio + RCV_RING_LEN0);
1482 buf[4] = readl(mmio + CMD0);
1483 buf[5] = readl(mmio + CMD2);
1484 buf[6] = readl(mmio + CMD3);
1485 buf[7] = readl(mmio + CMD7);
1486 buf[8] = readl(mmio + INT0);
1487 buf[9] = readl(mmio + INTEN0);
1488 buf[10] = readl(mmio + LADRF);
1489 buf[11] = readl(mmio + LADRF+4);
1490 buf[12] = readl(mmio + STAT0);
1491 }
1492
1493 /*
1494 amd8111e crc generator implementation is different from the kernel
1495 ether_crc() function.
1496 */
1497 static int amd8111e_ether_crc(int len, char* mac_addr)
1498 {
1499 int i,byte;
1500 unsigned char octet;
1501 u32 crc= INITCRC;
1502
1503 for(byte=0; byte < len; byte++){
1504 octet = mac_addr[byte];
1505 for( i=0;i < 8; i++){
1506 /*If the next bit form the input stream is 1,subtract the divisor (CRC32) from the dividend(crc).*/
1507 if( (octet & 0x1) ^ (crc & 0x1) ){
1508 crc >>= 1;
1509 crc ^= CRC32;
1510 }
1511 else
1512 crc >>= 1;
1513
1514 octet >>= 1;
1515 }
1516 }
1517 return crc;
1518 }
1519 /*
1520 This function sets promiscuos mode, all-multi mode or the multicast address
1521 list to the device.
1522 */
1523 static void amd8111e_set_multicast_list(struct net_device *dev)
1524 {
1525 struct dev_mc_list* mc_ptr;
1526 struct amd8111e_priv *lp = netdev_priv(dev);
1527 u32 mc_filter[2] ;
1528 int i,bit_num;
1529 if(dev->flags & IFF_PROMISC){
1530 writel( VAL2 | PROM, lp->mmio + CMD2);
1531 return;
1532 }
1533 else
1534 writel( PROM, lp->mmio + CMD2);
1535 if(dev->flags & IFF_ALLMULTI || dev->mc_count > MAX_FILTER_SIZE){
1536 /* get all multicast packet */
1537 mc_filter[1] = mc_filter[0] = 0xffffffff;
1538 lp->mc_list = dev->mc_list;
1539 lp->options |= OPTION_MULTICAST_ENABLE;
1540 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1541 return;
1542 }
1543 if( dev->mc_count == 0 ){
1544 /* get only own packets */
1545 mc_filter[1] = mc_filter[0] = 0;
1546 lp->mc_list = NULL;
1547 lp->options &= ~OPTION_MULTICAST_ENABLE;
1548 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1549 /* disable promiscous mode */
1550 writel(PROM, lp->mmio + CMD2);
1551 return;
1552 }
1553 /* load all the multicast addresses in the logic filter */
1554 lp->options |= OPTION_MULTICAST_ENABLE;
1555 lp->mc_list = dev->mc_list;
1556 mc_filter[1] = mc_filter[0] = 0;
1557 for (i = 0, mc_ptr = dev->mc_list; mc_ptr && i < dev->mc_count;
1558 i++, mc_ptr = mc_ptr->next) {
1559 bit_num = ( amd8111e_ether_crc(ETH_ALEN,mc_ptr->dmi_addr) >> 26 ) & 0x3f;
1560 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1561 }
1562 amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
1563
1564 /* To eliminate PCI posting bug */
1565 readl(lp->mmio + CMD2);
1566
1567 }
1568
1569 static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info)
1570 {
1571 struct amd8111e_priv *lp = netdev_priv(dev);
1572 struct pci_dev *pci_dev = lp->pci_dev;
1573 strcpy (info->driver, MODULE_NAME);
1574 strcpy (info->version, MODULE_VERS);
1575 sprintf(info->fw_version,"%u",chip_version);
1576 strcpy (info->bus_info, pci_name(pci_dev));
1577 }
1578
1579 static int amd8111e_get_regs_len(struct net_device *dev)
1580 {
1581 return AMD8111E_REG_DUMP_LEN;
1582 }
1583
1584 static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1585 {
1586 struct amd8111e_priv *lp = netdev_priv(dev);
1587 regs->version = 0;
1588 amd8111e_read_regs(lp, buf);
1589 }
1590
1591 static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1592 {
1593 struct amd8111e_priv *lp = netdev_priv(dev);
1594 spin_lock_irq(&lp->lock);
1595 mii_ethtool_gset(&lp->mii_if, ecmd);
1596 spin_unlock_irq(&lp->lock);
1597 return 0;
1598 }
1599
1600 static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1601 {
1602 struct amd8111e_priv *lp = netdev_priv(dev);
1603 int res;
1604 spin_lock_irq(&lp->lock);
1605 res = mii_ethtool_sset(&lp->mii_if, ecmd);
1606 spin_unlock_irq(&lp->lock);
1607 return res;
1608 }
1609
1610 static int amd8111e_nway_reset(struct net_device *dev)
1611 {
1612 struct amd8111e_priv *lp = netdev_priv(dev);
1613 return mii_nway_restart(&lp->mii_if);
1614 }
1615
1616 static u32 amd8111e_get_link(struct net_device *dev)
1617 {
1618 struct amd8111e_priv *lp = netdev_priv(dev);
1619 return mii_link_ok(&lp->mii_if);
1620 }
1621
1622 static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1623 {
1624 struct amd8111e_priv *lp = netdev_priv(dev);
1625 wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1626 if (lp->options & OPTION_WOL_ENABLE)
1627 wol_info->wolopts = WAKE_MAGIC;
1628 }
1629
1630 static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1631 {
1632 struct amd8111e_priv *lp = netdev_priv(dev);
1633 if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1634 return -EINVAL;
1635 spin_lock_irq(&lp->lock);
1636 if (wol_info->wolopts & WAKE_MAGIC)
1637 lp->options |=
1638 (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1639 else if(wol_info->wolopts & WAKE_PHY)
1640 lp->options |=
1641 (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1642 else
1643 lp->options &= ~OPTION_WOL_ENABLE;
1644 spin_unlock_irq(&lp->lock);
1645 return 0;
1646 }
1647
1648 static const struct ethtool_ops ops = {
1649 .get_drvinfo = amd8111e_get_drvinfo,
1650 .get_regs_len = amd8111e_get_regs_len,
1651 .get_regs = amd8111e_get_regs,
1652 .get_settings = amd8111e_get_settings,
1653 .set_settings = amd8111e_set_settings,
1654 .nway_reset = amd8111e_nway_reset,
1655 .get_link = amd8111e_get_link,
1656 .get_wol = amd8111e_get_wol,
1657 .set_wol = amd8111e_set_wol,
1658 };
1659
1660 /*
1661 This function handles all the ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
1662 */
1663
1664 static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
1665 {
1666 struct mii_ioctl_data *data = if_mii(ifr);
1667 struct amd8111e_priv *lp = netdev_priv(dev);
1668 int err;
1669 u32 mii_regval;
1670
1671 if (!capable(CAP_NET_ADMIN))
1672 return -EPERM;
1673
1674 switch(cmd) {
1675 case SIOCGMIIPHY:
1676 data->phy_id = lp->ext_phy_addr;
1677
1678 /* fallthru */
1679 case SIOCGMIIREG:
1680
1681 spin_lock_irq(&lp->lock);
1682 err = amd8111e_read_phy(lp, data->phy_id,
1683 data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1684 spin_unlock_irq(&lp->lock);
1685
1686 data->val_out = mii_regval;
1687 return err;
1688
1689 case SIOCSMIIREG:
1690
1691 spin_lock_irq(&lp->lock);
1692 err = amd8111e_write_phy(lp, data->phy_id,
1693 data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1694 spin_unlock_irq(&lp->lock);
1695
1696 return err;
1697
1698 default:
1699 /* do nothing */
1700 break;
1701 }
1702 return -EOPNOTSUPP;
1703 }
1704 static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1705 {
1706 struct amd8111e_priv *lp = netdev_priv(dev);
1707 int i;
1708 struct sockaddr *addr = p;
1709
1710 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1711 spin_lock_irq(&lp->lock);
1712 /* Setting the MAC address to the device */
1713 for(i = 0; i < ETH_ADDR_LEN; i++)
1714 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1715
1716 spin_unlock_irq(&lp->lock);
1717
1718 return 0;
1719 }
1720
1721 /*
1722 This function changes the mtu of the device. It restarts the device to initialize the descriptor with new receive buffers.
1723 */
1724 static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1725 {
1726 struct amd8111e_priv *lp = netdev_priv(dev);
1727 int err;
1728
1729 if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU))
1730 return -EINVAL;
1731
1732 if (!netif_running(dev)) {
1733 /* new_mtu will be used
1734 when device starts netxt time */
1735 dev->mtu = new_mtu;
1736 return 0;
1737 }
1738
1739 spin_lock_irq(&lp->lock);
1740
1741 /* stop the chip */
1742 writel(RUN, lp->mmio + CMD0);
1743
1744 dev->mtu = new_mtu;
1745
1746 err = amd8111e_restart(dev);
1747 spin_unlock_irq(&lp->lock);
1748 if(!err)
1749 netif_start_queue(dev);
1750 return err;
1751 }
1752
1753 #if AMD8111E_VLAN_TAG_USED
1754 static void amd8111e_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1755 {
1756 struct amd8111e_priv *lp = netdev_priv(dev);
1757 spin_lock_irq(&lp->lock);
1758 lp->vlgrp = grp;
1759 spin_unlock_irq(&lp->lock);
1760 }
1761
1762 static void amd8111e_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1763 {
1764 struct amd8111e_priv *lp = netdev_priv(dev);
1765 spin_lock_irq(&lp->lock);
1766 if (lp->vlgrp)
1767 lp->vlgrp->vlan_devices[vid] = NULL;
1768 spin_unlock_irq(&lp->lock);
1769 }
1770 #endif
1771 static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
1772 {
1773 writel( VAL1|MPPLBA, lp->mmio + CMD3);
1774 writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1775
1776 /* To eliminate PCI posting bug */
1777 readl(lp->mmio + CMD7);
1778 return 0;
1779 }
1780
1781 static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
1782 {
1783
1784 /* Adapter is already stoped/suspended/interrupt-disabled */
1785 writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
1786
1787 /* To eliminate PCI posting bug */
1788 readl(lp->mmio + CMD7);
1789 return 0;
1790 }
1791 /* This function is called when a packet transmission fails to complete within a resonable period, on the assumption that an interrupts have been failed or the interface is locked up. This function will reinitialize the hardware */
1792
1793 static void amd8111e_tx_timeout(struct net_device *dev)
1794 {
1795 struct amd8111e_priv* lp = netdev_priv(dev);
1796 int err;
1797
1798 printk(KERN_ERR "%s: transmit timed out, resetting\n",
1799 dev->name);
1800 spin_lock_irq(&lp->lock);
1801 err = amd8111e_restart(dev);
1802 spin_unlock_irq(&lp->lock);
1803 if(!err)
1804 netif_wake_queue(dev);
1805 }
1806 static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
1807 {
1808 struct net_device *dev = pci_get_drvdata(pci_dev);
1809 struct amd8111e_priv *lp = netdev_priv(dev);
1810
1811 if (!netif_running(dev))
1812 return 0;
1813
1814 /* disable the interrupt */
1815 spin_lock_irq(&lp->lock);
1816 amd8111e_disable_interrupt(lp);
1817 spin_unlock_irq(&lp->lock);
1818
1819 netif_device_detach(dev);
1820
1821 /* stop chip */
1822 spin_lock_irq(&lp->lock);
1823 if(lp->options & OPTION_DYN_IPG_ENABLE)
1824 del_timer_sync(&lp->ipg_data.ipg_timer);
1825 amd8111e_stop_chip(lp);
1826 spin_unlock_irq(&lp->lock);
1827
1828 if(lp->options & OPTION_WOL_ENABLE){
1829 /* enable wol */
1830 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
1831 amd8111e_enable_magicpkt(lp);
1832 if(lp->options & OPTION_WAKE_PHY_ENABLE)
1833 amd8111e_enable_link_change(lp);
1834
1835 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1836 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1837
1838 }
1839 else{
1840 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1841 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1842 }
1843
1844 pci_save_state(pci_dev);
1845 pci_set_power_state(pci_dev, PCI_D3hot);
1846
1847 return 0;
1848 }
1849 static int amd8111e_resume(struct pci_dev *pci_dev)
1850 {
1851 struct net_device *dev = pci_get_drvdata(pci_dev);
1852 struct amd8111e_priv *lp = netdev_priv(dev);
1853
1854 if (!netif_running(dev))
1855 return 0;
1856
1857 pci_set_power_state(pci_dev, PCI_D0);
1858 pci_restore_state(pci_dev);
1859
1860 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1861 pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1862
1863 netif_device_attach(dev);
1864
1865 spin_lock_irq(&lp->lock);
1866 amd8111e_restart(dev);
1867 /* Restart ipg timer */
1868 if(lp->options & OPTION_DYN_IPG_ENABLE)
1869 mod_timer(&lp->ipg_data.ipg_timer,
1870 jiffies + IPG_CONVERGE_JIFFIES);
1871 spin_unlock_irq(&lp->lock);
1872
1873 return 0;
1874 }
1875
1876
1877 static void __devexit amd8111e_remove_one(struct pci_dev *pdev)
1878 {
1879 struct net_device *dev = pci_get_drvdata(pdev);
1880 if (dev) {
1881 unregister_netdev(dev);
1882 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio);
1883 free_netdev(dev);
1884 pci_release_regions(pdev);
1885 pci_disable_device(pdev);
1886 pci_set_drvdata(pdev, NULL);
1887 }
1888 }
1889 static void amd8111e_config_ipg(struct net_device* dev)
1890 {
1891 struct amd8111e_priv *lp = netdev_priv(dev);
1892 struct ipg_info* ipg_data = &lp->ipg_data;
1893 void __iomem *mmio = lp->mmio;
1894 unsigned int prev_col_cnt = ipg_data->col_cnt;
1895 unsigned int total_col_cnt;
1896 unsigned int tmp_ipg;
1897
1898 if(lp->link_config.duplex == DUPLEX_FULL){
1899 ipg_data->ipg = DEFAULT_IPG;
1900 return;
1901 }
1902
1903 if(ipg_data->ipg_state == SSTATE){
1904
1905 if(ipg_data->timer_tick == IPG_STABLE_TIME){
1906
1907 ipg_data->timer_tick = 0;
1908 ipg_data->ipg = MIN_IPG - IPG_STEP;
1909 ipg_data->current_ipg = MIN_IPG;
1910 ipg_data->diff_col_cnt = 0xFFFFFFFF;
1911 ipg_data->ipg_state = CSTATE;
1912 }
1913 else
1914 ipg_data->timer_tick++;
1915 }
1916
1917 if(ipg_data->ipg_state == CSTATE){
1918
1919 /* Get the current collision count */
1920
1921 total_col_cnt = ipg_data->col_cnt =
1922 amd8111e_read_mib(mmio, xmt_collisions);
1923
1924 if ((total_col_cnt - prev_col_cnt) <
1925 (ipg_data->diff_col_cnt)){
1926
1927 ipg_data->diff_col_cnt =
1928 total_col_cnt - prev_col_cnt ;
1929
1930 ipg_data->ipg = ipg_data->current_ipg;
1931 }
1932
1933 ipg_data->current_ipg += IPG_STEP;
1934
1935 if (ipg_data->current_ipg <= MAX_IPG)
1936 tmp_ipg = ipg_data->current_ipg;
1937 else{
1938 tmp_ipg = ipg_data->ipg;
1939 ipg_data->ipg_state = SSTATE;
1940 }
1941 writew((u32)tmp_ipg, mmio + IPG);
1942 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1943 }
1944 mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1945 return;
1946
1947 }
1948
1949 static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
1950 {
1951 struct amd8111e_priv *lp = netdev_priv(dev);
1952 int i;
1953
1954 for (i = 0x1e; i >= 0; i--) {
1955 u32 id1, id2;
1956
1957 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1958 continue;
1959 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1960 continue;
1961 lp->ext_phy_id = (id1 << 16) | id2;
1962 lp->ext_phy_addr = i;
1963 return;
1964 }
1965 lp->ext_phy_id = 0;
1966 lp->ext_phy_addr = 1;
1967 }
1968
1969 static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
1970 const struct pci_device_id *ent)
1971 {
1972 int err,i,pm_cap;
1973 unsigned long reg_addr,reg_len;
1974 struct amd8111e_priv* lp;
1975 struct net_device* dev;
1976
1977 err = pci_enable_device(pdev);
1978 if(err){
1979 printk(KERN_ERR "amd8111e: Cannot enable new PCI device,"
1980 "exiting.\n");
1981 return err;
1982 }
1983
1984 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
1985 printk(KERN_ERR "amd8111e: Cannot find PCI base address"
1986 "exiting.\n");
1987 err = -ENODEV;
1988 goto err_disable_pdev;
1989 }
1990
1991 err = pci_request_regions(pdev, MODULE_NAME);
1992 if(err){
1993 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, "
1994 "exiting.\n");
1995 goto err_disable_pdev;
1996 }
1997
1998 pci_set_master(pdev);
1999
2000 /* Find power-management capability. */
2001 if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){
2002 printk(KERN_ERR "amd8111e: No Power Management capability, "
2003 "exiting.\n");
2004 goto err_free_reg;
2005 }
2006
2007 /* Initialize DMA */
2008 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) < 0) {
2009 printk(KERN_ERR "amd8111e: DMA not supported,"
2010 "exiting.\n");
2011 goto err_free_reg;
2012 }
2013
2014 reg_addr = pci_resource_start(pdev, 0);
2015 reg_len = pci_resource_len(pdev, 0);
2016
2017 dev = alloc_etherdev(sizeof(struct amd8111e_priv));
2018 if (!dev) {
2019 printk(KERN_ERR "amd8111e: Etherdev alloc failed, exiting.\n");
2020 err = -ENOMEM;
2021 goto err_free_reg;
2022 }
2023
2024 SET_MODULE_OWNER(dev);
2025 SET_NETDEV_DEV(dev, &pdev->dev);
2026
2027 #if AMD8111E_VLAN_TAG_USED
2028 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ;
2029 dev->vlan_rx_register =amd8111e_vlan_rx_register;
2030 dev->vlan_rx_kill_vid = amd8111e_vlan_rx_kill_vid;
2031 #endif
2032
2033 lp = netdev_priv(dev);
2034 lp->pci_dev = pdev;
2035 lp->amd8111e_net_dev = dev;
2036 lp->pm_cap = pm_cap;
2037
2038 spin_lock_init(&lp->lock);
2039
2040 lp->mmio = ioremap(reg_addr, reg_len);
2041 if (lp->mmio == 0) {
2042 printk(KERN_ERR "amd8111e: Cannot map device registers, "
2043 "exiting\n");
2044 err = -ENOMEM;
2045 goto err_free_dev;
2046 }
2047
2048 /* Initializing MAC address */
2049 for(i = 0; i < ETH_ADDR_LEN; i++)
2050 dev->dev_addr[i] =readb(lp->mmio + PADR + i);
2051
2052 /* Setting user defined parametrs */
2053 lp->ext_phy_option = speed_duplex[card_idx];
2054 if(coalesce[card_idx])
2055 lp->options |= OPTION_INTR_COAL_ENABLE;
2056 if(dynamic_ipg[card_idx++])
2057 lp->options |= OPTION_DYN_IPG_ENABLE;
2058
2059 /* Initialize driver entry points */
2060 dev->open = amd8111e_open;
2061 dev->hard_start_xmit = amd8111e_start_xmit;
2062 dev->stop = amd8111e_close;
2063 dev->get_stats = amd8111e_get_stats;
2064 dev->set_multicast_list = amd8111e_set_multicast_list;
2065 dev->set_mac_address = amd8111e_set_mac_address;
2066 dev->do_ioctl = amd8111e_ioctl;
2067 dev->change_mtu = amd8111e_change_mtu;
2068 SET_ETHTOOL_OPS(dev, &ops);
2069 dev->irq =pdev->irq;
2070 dev->tx_timeout = amd8111e_tx_timeout;
2071 dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
2072 #ifdef CONFIG_AMD8111E_NAPI
2073 dev->poll = amd8111e_rx_poll;
2074 dev->weight = 32;
2075 #endif
2076 #ifdef CONFIG_NET_POLL_CONTROLLER
2077 dev->poll_controller = amd8111e_poll;
2078 #endif
2079
2080 #if AMD8111E_VLAN_TAG_USED
2081 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2082 dev->vlan_rx_register =amd8111e_vlan_rx_register;
2083 dev->vlan_rx_kill_vid = amd8111e_vlan_rx_kill_vid;
2084 #endif
2085 /* Probe the external PHY */
2086 amd8111e_probe_ext_phy(dev);
2087
2088 /* setting mii default values */
2089 lp->mii_if.dev = dev;
2090 lp->mii_if.mdio_read = amd8111e_mdio_read;
2091 lp->mii_if.mdio_write = amd8111e_mdio_write;
2092 lp->mii_if.phy_id = lp->ext_phy_addr;
2093
2094 /* Set receive buffer length and set jumbo option*/
2095 amd8111e_set_rx_buff_len(dev);
2096
2097
2098 err = register_netdev(dev);
2099 if (err) {
2100 printk(KERN_ERR "amd8111e: Cannot register net device, "
2101 "exiting.\n");
2102 goto err_iounmap;
2103 }
2104
2105 pci_set_drvdata(pdev, dev);
2106
2107 /* Initialize software ipg timer */
2108 if(lp->options & OPTION_DYN_IPG_ENABLE){
2109 init_timer(&lp->ipg_data.ipg_timer);
2110 lp->ipg_data.ipg_timer.data = (unsigned long) dev;
2111 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
2112 lp->ipg_data.ipg_timer.expires = jiffies +
2113 IPG_CONVERGE_JIFFIES;
2114 lp->ipg_data.ipg = DEFAULT_IPG;
2115 lp->ipg_data.ipg_state = CSTATE;
2116 };
2117
2118 /* display driver and device information */
2119
2120 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
2121 printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n", dev->name,MODULE_VERS);
2122 printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet ", dev->name, chip_version);
2123 for (i = 0; i < 6; i++)
2124 printk("%2.2x%c",dev->dev_addr[i],i == 5 ? ' ' : ':');
2125 printk( "\n");
2126 if (lp->ext_phy_id)
2127 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
2128 dev->name, lp->ext_phy_id, lp->ext_phy_addr);
2129 else
2130 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
2131 dev->name);
2132 return 0;
2133 err_iounmap:
2134 iounmap(lp->mmio);
2135
2136 err_free_dev:
2137 free_netdev(dev);
2138
2139 err_free_reg:
2140 pci_release_regions(pdev);
2141
2142 err_disable_pdev:
2143 pci_disable_device(pdev);
2144 pci_set_drvdata(pdev, NULL);
2145 return err;
2146
2147 }
2148
2149 static struct pci_driver amd8111e_driver = {
2150 .name = MODULE_NAME,
2151 .id_table = amd8111e_pci_tbl,
2152 .probe = amd8111e_probe_one,
2153 .remove = __devexit_p(amd8111e_remove_one),
2154 .suspend = amd8111e_suspend,
2155 .resume = amd8111e_resume
2156 };
2157
2158 static int __init amd8111e_init(void)
2159 {
2160 return pci_register_driver(&amd8111e_driver);
2161 }
2162
2163 static void __exit amd8111e_cleanup(void)
2164 {
2165 pci_unregister_driver(&amd8111e_driver);
2166 }
2167
2168 module_init(amd8111e_init);
2169 module_exit(amd8111e_cleanup);
MOXA 2.6.19 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz