arch/nios2nommu/drivers/pci/pci.c

   1 /* arch/sh/kernel/pci.c
   2  * $Id: pci.c,v 1.2 2007/01/25 01:26:48 gerg Exp $
   3  *
   4  * Copyright (c) 2002 M. R. Brown  <mrbrown@linux-sh.org>
   5  *
   6  *
   7  * These functions are collected here to reduce duplication of common
   8  * code amongst the many platform-specific PCI support code files.
   9  *
  10  * These routines require the following board-specific routines:
  11  * void pcibios_fixup_irqs();
  12  *
  13  * See include/asm-sh/pci.h for more information.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19
  20 static int __init pcibios_init(void)
  21 {
  22         struct pci_channel *p;
  23         struct pci_bus *bus;
  24         int busno;
  25
  26 #ifdef CONFIG_PCI_AUTO
  27         /* assign resources */
  28         busno = 0;
  29         for (p = board_pci_channels; p->pci_ops != NULL; p++) {
  30                 busno = pciauto_assign_resources(busno, p) + 1;
  31         }
  32 #endif
  33
  34         /* scan the buses */
  35         busno = 0;
  36         for (p= board_pci_channels; p->pci_ops != NULL; p++) {
  37                 bus = pci_scan_bus(busno, p->pci_ops, p);
  38                 busno = bus->subordinate+1;
  39         }
  40
  41         /* board-specific fixups */
  42         pcibios_fixup_irqs();
  43
  44         return 0;
  45 }
  46
  47 subsys_initcall(pcibios_init);
  48
  49 void
  50 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
  51                         struct resource *res, int resource)
  52 {
  53         u32 new, check;
  54         int reg;
  55
  56         new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
  57         if (resource < 6) {
  58                 reg = PCI_BASE_ADDRESS_0 + 4*resource;
  59         } else if (resource == PCI_ROM_RESOURCE) {
  60                 res->flags |= IORESOURCE_ROM_ENABLE;
  61                 new |= PCI_ROM_ADDRESS_ENABLE;
  62                 reg = dev->rom_base_reg;
  63         } else {
  64                 /* Somebody might have asked allocation of a non-standard resource */
  65                 return;
  66         }
  67
  68         pci_write_config_dword(dev, reg, new);
  69         pci_read_config_dword(dev, reg, &check);
  70         if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
  71                 printk(KERN_ERR "PCI: Error while updating region "
  72                        "%s/%d (%08x != %08x)\n", pci_name(dev), resource,
  73                        new, check);
  74         }
  75 }
  76
  77 /*
  78  * We need to avoid collisions with `mirrored' VGA ports
  79  * and other strange ISA hardware, so we always want the
  80  * addresses to be allocated in the 0x000-0x0ff region
  81  * modulo 0x400.
  82  */
  83 void pcibios_align_resource(void *data, struct resource *res,
  84                             resource_size_t size, resource_size_t align)
  85 {
  86         if (res->flags & IORESOURCE_IO) {
  87                 unsigned long start = res->start;
  88
  89                 if (start & 0x300) {
  90                         start = (start + 0x3ff) & ~0x3ff;
  91                         res->start = start;
  92                 }
  93         }
  94 }
  95
  96 int pcibios_enable_device(struct pci_dev *dev, int mask)
  97 {
  98         u16 cmd, old_cmd;
  99         int idx;
 100         struct resource *r;
 101
 102         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 103         old_cmd = cmd;
 104         for(idx=0; idx<6; idx++) {
 105                 if (!(mask & (1 << idx)))
 106                         continue;
 107                 r = &dev->resource[idx];
 108                 if (!r->start && r->end) {
 109                         printk(KERN_ERR "PCI: Device %s not available because "
 110                                "of resource collisions\n", pci_name(dev));
 111                         return -EINVAL;
 112                 }
 113                 if (r->flags & IORESOURCE_IO)
 114                         cmd |= PCI_COMMAND_IO;
 115                 if (r->flags & IORESOURCE_MEM)
 116                         cmd |= PCI_COMMAND_MEMORY;
 117         }
 118         if (dev->resource[PCI_ROM_RESOURCE].start)
 119                 cmd |= PCI_COMMAND_MEMORY;
 120         if (cmd != old_cmd) {
 121                 printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n",
 122                        pci_name(dev), old_cmd, cmd);
 123                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 124         }
 125         return 0;
 126 }
 127
 128 /*
 129  *  If we set up a device for bus mastering, we need to check and set
 130  *  the latency timer as it may not be properly set.
 131  */
 132 unsigned int pcibios_max_latency = 255;
 133
 134 void pcibios_set_master(struct pci_dev *dev)
 135 {
 136         u8 lat;
 137         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 138         if (lat < 16)
 139                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 140         else if (lat > pcibios_max_latency)
 141                 lat = pcibios_max_latency;
 142         else
 143                 return;
 144         printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
 145         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 146 }
 147
 148 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
 149 {
 150         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 151 }