| blob | d2e64e83ab405350acf861734c504001957d6d1d |
1 /*
2 * linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
3 *
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2001 Altera Corporation
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 *
24 * These are the low level assembler for performing cache and TLB
25 * functions on the arm922.
26 *
27 * CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
28 */
29 #include <linux/linkage.h>
30 #include <linux/init.h>
31 #include <asm/assembler.h>
32 #include <asm/pgtable-hwdef.h>
33 #include <asm/pgtable.h>
34 #include <asm/procinfo.h>
35 #include <asm/page.h>
36 #include <asm/ptrace.h>
37 #include "proc-macros.S"
39 /*
40 * The size of one data cache line.
41 */
42 #define CACHE_DLINESIZE 16
43 #if 1 /* add by Victor Yu. 02-08-2007 */
44 #define CACHE_DSIZE 16384
45 #define CACHE_ISIZE 16384
46 #define CACHE_ILINESIZE 16
47 #endif
49 /*
50 * The number of data cache segments.
51 */
52 #define CACHE_DSEGMENTS 4
54 /*
55 * The number of lines in a cache segment.
56 */
57 #define CACHE_DENTRIES 64
59 /*
60 * This is the size at which it becomes more efficient to
61 * clean the whole cache, rather than using the individual
62 * cache line maintainence instructions. (I think this should
63 * be 32768).
64 */
65 #define CACHE_DLIMIT 8192
68 .text
69 /*
70 * cpu_arm922_proc_init()
71 */
72 ENTRY(cpu_arm922_proc_init)
73 mov pc, lr
75 /*
76 * cpu_arm922_proc_fin()
77 */
78 ENTRY(cpu_arm922_proc_fin)
79 stmfd sp!, {lr}
80 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
81 msr cpsr_c, ip
82 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
83 bl arm922_flush_kern_cache_all
84 #else
85 bl v4wt_flush_kern_cache_all
86 #endif
87 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
88 bic r0, r0, #0x1000 @ ...i............
89 bic r0, r0, #0x000e @ ............wca.
90 mcr p15, 0, r0, c1, c0, 0 @ disable caches
91 ldmfd sp!, {pc}
93 /*
94 * cpu_arm922_reset(loc)
95 *
96 * Perform a soft reset of the system. Put the CPU into the
97 * same state as it would be if it had been reset, and branch
98 * to what would be the reset vector.
99 *
100 * loc: location to jump to for soft reset
101 */
102 .align 5
103 ENTRY(cpu_arm922_reset)
104 mov ip, #0
105 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
106 mcr p15, 0, ip, c7, c10, 4 @ drain WB
107 #ifdef CONFIG_MMU
108 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
109 #endif
110 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
111 bic ip, ip, #0x000f @ ............wcam
112 bic ip, ip, #0x1100 @ ...i...s........
113 #if 1 /* add by Victor Yu. 06-09-2005 */
114 bic ip, ip, #0x0800 @ off BTB
115 #endif
116 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
117 mov pc, r0
119 /*
120 * cpu_arm922_do_idle()
121 */
122 .align 5
123 ENTRY(cpu_arm922_do_idle)
124 #if 0 /* mask by Victor Yu. 02-08-2007 */
125 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
126 #endif
127 mov pc, lr
130 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
132 /*
133 * flush_user_cache_all()
134 *
135 * Clean and invalidate all cache entries in a particular
136 * address space.
137 */
138 ENTRY(arm922_flush_user_cache_all)
139 /* FALLTHROUGH */
141 /*
142 * flush_kern_cache_all()
143 *
144 * Clean and invalidate the entire cache.
145 */
146 ENTRY(arm922_flush_kern_cache_all)
147 #if 1 /* mask by Victor Yu. 05-30-2005 */
148 mov r2, #VM_EXEC
149 mov ip, #0
150 __flush_whole_cache:
151 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
152 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
153 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
154 subs r3, r3, #1 << 26
155 bcs 2b @ entries 63 to 0
156 subs r1, r1, #1 << 5
157 bcs 1b @ segments 7 to 0
158 tst r2, #VM_EXEC
159 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
160 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
161 mov pc, lr
162 #else /* add by Victor Yu. 05-30-2005 */
163 mov ip, #0
165 #ifndef CONFIG_CPU_ICACHE_DISABLE
166 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
167 #endif
169 __flush_whole_cache:
171 #ifndef CONFIG_CPU_DCACHE_DISABLE
172 mov ip, #0
173 # ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
174 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
175 # else
176 mcr p15, 0, ip, c7,c14, 0 @ clean/invalidate D cache
177 # endif
178 #endif /*CONFIG_CPU_DCACHE_DISABLE*/
180 #ifndef CONFIG_CPU_FA_WB_DISABLE
181 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
182 #endif
183 mov pc, lr
184 #endif
186 /*
187 * flush_user_cache_range(start, end, flags)
188 *
189 * Clean and invalidate a range of cache entries in the
190 * specified address range.
191 *
192 * - start - start address (inclusive)
193 * - end - end address (exclusive)
194 * - flags - vm_flags describing address space
195 */
196 ENTRY(arm922_flush_user_cache_range)
197 #if 1 /* mask by Victor Yu. 05-30-2005 */
198 mov ip, #0
199 sub r3, r1, r0 @ calculate total size
200 cmp r3, #CACHE_DLIMIT
201 bhs __flush_whole_cache
203 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
204 tst r2, #VM_EXEC
205 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
206 add r0, r0, #CACHE_DLINESIZE
207 cmp r0, r1
208 blo 1b
209 tst r2, #VM_EXEC
210 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
211 mov pc, lr
212 #else /* add by Victor Yu. 05-30-2005 */
213 mov ip, #0
214 sub r3, r1, r0 @ calculate total size
215 #ifndef CONFIG_CPU_ICACHE_DISABLE
216 tst r2, #VM_EXEC @ executable region?
217 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
218 #endif
220 #ifndef CONFIG_CPU_DCACHE_DISABLE
221 cmp r3, #CACHE_DSIZE @ total size >= limit?
222 bhs __flush_whole_cache @ flush whole D cache
224 1:
226 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
227 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
228 #else
229 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
230 #endif
231 add r0, r0, #CACHE_DLINESIZE
232 cmp r0, r1
233 bls 1b
234 #endif /* CONFIG_CPU_DCACHE_DISABLE */
236 #ifndef CONFIG_CPU_FA_WB_DISABLE
237 tst r2, #VM_EXEC
238 mcreq p15, 0, r4, c7, c10, 4 @ drain write buffer
239 #endif
241 mov pc, lr
242 #endif
244 /*
245 * flush_kern_dcache_page(void *page)
246 *
247 * Ensure no D cache aliasing occurs, either with itself or
248 * the I cache
249 *
250 * - addr - page aligned address
251 */
252 ENTRY(arm922_flush_kern_dcache_page)
253 #if 1 /* mask by Victor Yu. 05-30-2005 */
254 add r1, r0, #PAGE_SZ
255 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
256 add r0, r0, #CACHE_DLINESIZE
257 cmp r0, r1
258 blo 1b
259 mov r0, #0
260 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
261 mcr p15, 0, r0, c7, c10, 4 @ drain WB
262 mov pc, lr
263 #else /* add by Victor Yu. 05-30-2005 */
264 add r1, r0, #PAGE_SZ
265 /* fall through */
266 #endif
268 /*
269 * coherent_kern_range(start, end)
270 *
271 * Ensure coherency between the Icache and the Dcache in the
272 * region described by start, end. If you have non-snooping
273 * Harvard caches, you need to implement this function.
274 *
275 * - start - virtual start address
276 * - end - virtual end address
277 */
278 ENTRY(arm922_coherent_kern_range)
279 /* FALLTHROUGH */
281 /*
282 * coherent_user_range(start, end)
283 *
284 * Ensure coherency between the Icache and the Dcache in the
285 * region described by start, end. If you have non-snooping
286 * Harvard caches, you need to implement this function.
287 *
288 * - start - virtual start address
289 * - end - virtual end address
290 */
291 ENTRY(arm922_coherent_user_range)
292 #if 1 /* mask by Victor Yu. 06-09-2005 */
293 bic r0, r0, #CACHE_DLINESIZE - 1
294 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
295 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
296 add r0, r0, #CACHE_DLINESIZE
297 cmp r0, r1
298 blo 1b
299 mcr p15, 0, r0, c7, c10, 4 @ drain WB
300 mov pc, lr
301 #else /* add by Victor Yu. 06-09-2005 */
302 bic r0, r0, #CACHE_DLINESIZE-1
304 #if !(defined(CONFIG_CPU_DCACHE_DISABLE) && defined(CONFIG_CPU_ICACHE_DISABLE))
305 1:
306 #ifndef CONFIG_CPU_DCACHE_DISABLE
307 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
308 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
309 #else
310 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
311 #endif
312 #endif /* CONFIG_CPU_DCACHE_DISABLE */
314 #ifndef CONFIG_CPU_ICACHE_DISABLE
315 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
316 #endif
317 add r0, r0, #CACHE_DLINESIZE
318 cmp r0, r1
319 bls 1b @ Luke Lee 05/19/2005 blo->bls
320 #endif /* !(defined(CONFIG_CPU_DCACHE_DISABLE) && defined(CONFIG_CPU_ICACHE_DISABLE)) */
322 mov ip, #0
324 #ifndef CONFIG_CPU_FA_WB_DISABLE
325 mcr p15, 0, ip, c7, c10, 4 @ drain WB
326 #endif
328 mov pc, lr
329 #endif
331 /*
332 * dma_inv_range(start, end)
333 *
334 * Invalidate (discard) the specified virtual address range.
335 * May not write back any entries. If 'start' or 'end'
336 * are not cache line aligned, those lines must be written
337 * back.
338 *
339 * - start - virtual start address
340 * - end - virtual end address
341 *
342 * (same as v4wb)
343 */
344 ENTRY(arm922_dma_inv_range)
345 #if 1 /* mask by Victor Yu. 05-30-2005 */
346 tst r0, #CACHE_DLINESIZE - 1
347 bic r0, r0, #CACHE_DLINESIZE - 1
348 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
349 tst r1, #CACHE_DLINESIZE - 1
350 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
351 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
352 add r0, r0, #CACHE_DLINESIZE
353 cmp r0, r1
354 blo 1b
355 mcr p15, 0, r0, c7, c10, 4 @ drain WB
356 mov pc, lr
357 #else /* add by Victor Yu. 05-30-2005 */
358 #ifndef CONFIG_CPU_DCACHE_DISABLE
360 # ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
361 tst r0, #CACHE_DLINESIZE -1
362 bic r0, r0, #CACHE_DLINESIZE -1
363 mcrne p15, 0, r0, c7, c10, 1 @ clean boundary D entry
364 mcr p15, 0, r1, c7, c10, 1 @ clean boundary D entry
365 # else
366 bic r0, r0, #CACHE_DLINESIZE -1
367 # endif /* CONFIG_CPU_DCACHE_WRITETHROUGH */
369 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
370 add r0, r0, #CACHE_DLINESIZE
371 cmp r0, r1
372 bls 1b @ Luke Lee 05/19/2005 blo->bls
373 #endif /* CONFIG_CPU_DCACHE_DISABLE */
375 #ifndef CONFIG_CPU_FA_WB_DISABLE
376 mov r0, #0
377 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
378 #endif
379 mov pc, lr
380 #endif
382 /*
383 * dma_clean_range(start, end)
384 *
385 * Clean the specified virtual address range.
386 *
387 * - start - virtual start address
388 * - end - virtual end address
389 *
390 * (same as v4wb)
391 */
392 ENTRY(arm922_dma_clean_range)
393 #if 1 /* mask by Victor Yu. 05-30-2005 */
394 bic r0, r0, #CACHE_DLINESIZE - 1
395 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
396 add r0, r0, #CACHE_DLINESIZE
397 cmp r0, r1
398 blo 1b
399 mcr p15, 0, r0, c7, c10, 4 @ drain WB
400 mov pc, lr
401 #else /* add by Victor Yu. 05-30-2005 */
402 #ifndef CONFIG_CPU_DCACHE_DISABLE
403 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
404 bic r0, r0, #CACHE_DLINESIZE - 1
405 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
406 add r0, r0, #CACHE_DLINESIZE
407 cmp r0, r1
408 bls 1b @ Luke Lee 05/19/2005 blo->bls
410 #endif /* CONFIG_CPU_DCACHE_WRITETHROUGH */
411 #endif /* CONFIG_CPU_DCACHE_DISABLE */
413 #ifndef CONFIG_CPU_FA_WB_DISABLE
414 mov r0, #0
415 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
416 #endif
417 mov pc, lr
418 #endif
420 /*
421 * dma_flush_range(start, end)
422 *
423 * Clean and invalidate the specified virtual address range.
424 *
425 * - start - virtual start address
426 * - end - virtual end address
427 */
428 #if 1 /* mask by Victor Yu. 06-09-2005 */
429 ENTRY(arm922_dma_flush_range)
430 bic r0, r0, #CACHE_DLINESIZE - 1
431 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
432 add r0, r0, #CACHE_DLINESIZE
433 cmp r0, r1
434 blo 1b
435 mcr p15, 0, r0, c7, c10, 4 @ drain WB
436 mov pc, lr
437 #else /* add by Victor Yu. 06-09-2005 */
438 .globl arm922_dma_flush_range
439 .set arm922_dma_flush_range, arm922_coherent_kern_range
440 #endif
442 ENTRY(arm922_cache_fns)
443 .long arm922_flush_kern_cache_all
444 .long arm922_flush_user_cache_all
445 .long arm922_flush_user_cache_range
446 .long arm922_coherent_kern_range
447 .long arm922_coherent_user_range
448 .long arm922_flush_kern_dcache_page
449 .long arm922_dma_inv_range
450 .long arm922_dma_clean_range
451 .long arm922_dma_flush_range
452 #if 1 /* add by Victor Yu. 06-09-2005 */
453 .size arm922_cache_fns, . - arm922_cache_fns
454 #endif
456 #endif
459 ENTRY(cpu_arm922_dcache_clean_area)
460 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
461 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
462 add r0, r0, #CACHE_DLINESIZE
463 subs r1, r1, #CACHE_DLINESIZE
464 bhi 1b
465 #endif
466 mov pc, lr
468 /* =============================== PageTable ============================== */
470 /*
471 * cpu_arm922_switch_mm(pgd)
472 *
473 * Set the translation base pointer to be as described by pgd.
474 *
475 * pgd: new page tables
476 */
477 .align 5
478 ENTRY(cpu_arm922_switch_mm)
479 #ifdef CONFIG_MMU
480 mov ip, #0
481 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
482 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
483 #else
484 @ && 'Clean & Invalidate whole DCache'
485 @ && Re-written to use Index Ops.
486 @ && Uses registers r1, r3 and ip
488 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 4 segments
489 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
490 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
491 subs r3, r3, #1 << 26
492 bcs 2b @ entries 63 to 0
493 subs r1, r1, #1 << 5
494 bcs 1b @ segments 7 to 0
495 #endif
496 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
497 mcr p15, 0, ip, c7, c10, 4 @ drain WB
498 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
499 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
500 #endif
501 mov pc, lr
503 /*
504 * cpu_arm922_set_pte(ptep, pte)
505 *
506 * Set a PTE and flush it out
507 */
508 .align 5
509 ENTRY(cpu_arm922_set_pte)
510 #ifdef CONFIG_MMU
511 str r1, [r0], #-2048 @ linux version
513 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
515 bic r2, r1, #PTE_SMALL_AP_MASK
516 bic r2, r2, #PTE_TYPE_MASK
517 orr r2, r2, #PTE_TYPE_SMALL
519 tst r1, #L_PTE_USER @ User?
520 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
522 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
523 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
525 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
526 movne r2, #0
528 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
529 eor r3, r2, #0x0a @ C & small page?
530 tst r3, #0x0b
531 biceq r2, r2, #4
532 #endif
533 str r2, [r0] @ hardware version
534 mov r0, r0
535 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
536 mcr p15, 0, r0, c7, c10, 4 @ drain WB
537 #endif /* CONFIG_MMU */
538 mov pc, lr
540 __INIT
542 .type __arm922_setup, #function
543 __arm922_setup:
544 mov r0, #0
545 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
546 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
547 #ifdef CONFIG_MMU
548 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
549 #endif
550 adr r5, arm922_crval
551 ldmia r5, {r5, r6}
552 mrc p15, 0, r0, c1, c0 @ get control register v4
553 bic r0, r0, r5
554 orr r0, r0, r6
555 mov pc, lr
556 .size __arm922_setup, . - __arm922_setup
558 /*
559 * R
560 * .RVI ZFRS BLDP WCAM
561 * ..11 0001 ..11 0101
562 *
563 */
564 .type arm922_crval, #object
565 arm922_crval:
566 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
568 __INITDATA
570 /*
571 * Purpose : Function pointers used to access above functions - all calls
572 * come through these
573 */
574 .type arm922_processor_functions, #object
575 arm922_processor_functions:
576 #if 0 /* mask by Victor Yu. 02-08-2007 */
577 .word v4t_early_abort
578 #else
579 .word nommu_early_abort
580 #endif
581 .word cpu_arm922_proc_init
582 .word cpu_arm922_proc_fin
583 .word cpu_arm922_reset
584 .word cpu_arm922_do_idle
585 .word cpu_arm922_dcache_clean_area
586 .word cpu_arm922_switch_mm
587 .word cpu_arm922_set_pte
588 .size arm922_processor_functions, . - arm922_processor_functions
590 .section ".rodata"
592 .type cpu_arch_name, #object
593 cpu_arch_name:
594 .asciz "armv4t"
595 .size cpu_arch_name, . - cpu_arch_name
597 .type cpu_elf_name, #object
598 cpu_elf_name:
599 .asciz "v4"
600 .size cpu_elf_name, . - cpu_elf_name
602 .type cpu_arm922_name, #object
603 cpu_arm922_name:
604 .asciz "ARM922T"
605 .size cpu_arm922_name, . - cpu_arm922_name
607 .align
609 .section ".proc.info.init", #alloc, #execinstr
611 .type __arm922_proc_info,#object
612 __arm922_proc_info:
613 #if 0 /* mask by Victor Yu. 02-08-2007 */
614 .long 0x41009220
615 .long 0xff00fff0
616 #else
617 .long 0x66015261
618 .long 0xff01fff1
619 #endif
620 .long PMD_TYPE_SECT | \
621 PMD_SECT_BUFFERABLE | \
622 PMD_SECT_CACHEABLE | \
623 PMD_BIT4 | \
624 PMD_SECT_AP_WRITE | \
625 PMD_SECT_AP_READ
626 .long PMD_TYPE_SECT | \
627 PMD_BIT4 | \
628 PMD_SECT_AP_WRITE | \
629 PMD_SECT_AP_READ
630 b __arm922_setup
631 .long cpu_arch_name
632 .long cpu_elf_name
633 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
634 .long cpu_arm922_name
635 .long arm922_processor_functions
636 .long v4wbi_tlb_fns
637 .long v4wb_user_fns
638 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
639 .long arm922_cache_fns
640 #else
641 .long v4wt_cache_fns
642 #endif
643 .size __arm922_proc_info, . - __arm922_proc_info