arch/arm/mach-s3c44b0x/irq.c

   1 /*
   2  *  linux/arch/arm/mach-s3c44b0x/irq.c
   3  */
   4
   5 #include <linux/types.h>
   6 #include <linux/sched.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/types.h>
   9 #include <linux/kernel.h>
  10 #include <linux/init.h>
  11 #include <linux/list.h>
  12 #include <linux/device.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/sysdev.h>
  16
  17 #include <asm/hardware.h>
  18 #include <asm/io.h>
  19 #include <asm/irq.h>
  20 #include <asm/setup.h>
  21 #include <asm/mach-types.h>
  22
  23 #include <asm/mach/arch.h>
  24 #include <asm/mach/irq.h>
  25 #include <asm/mach/map.h>
  26
  27 void __inline__ s3c44b0x_mask_irq(unsigned int irq)
  28 {
  29         SYSREG_OR_SET(S3C44B0X_INTMSK, 1<<irq);
  30 }
  31
  32 void __inline__ s3c44b0x_unmask_irq(unsigned int irq)
  33 {
  34         SYSREG_CLR(S3C44B0X_INTMSK, 1<<irq);
  35 }
  36
  37 void __inline__ s3c44b0x_mask_ack_irq(unsigned int irq)
  38 {
  39         s3c44b0x_mask_irq(irq);
  40 }
  41
  42 /* Clear pending bit */
  43 void __inline__ s3c44b0x_clear_pb(unsigned int irq)
  44 {
  45         SYSREG_OR_SET(S3C44B0X_I_ISPC, 1<<irq);
  46 }
  47
  48
  49 /* YOU CAN CHANGE THIS ROUTINE FOR SPEED UP */
  50 __inline__ unsigned int fixup_irq (int irq )
  51 {
  52         s3c44b0x_clear_pb(irq);
  53         return(irq);
  54 }
  55
  56 static struct irqchip s3c44b0x_chip = {
  57         .ack    = s3c44b0x_clear_pb,
  58         .mask   = s3c44b0x_mask_irq,
  59         .unmask = s3c44b0x_unmask_irq,
  60 };
  61
  62 #ifdef CONFIG_PM
  63 static unsigned long ic_irq_enable;
  64
  65 static int irq_suspend(struct sys_device *dev, u32 state)
  66 {
  67         return 0;
  68 }
  69
  70 static int irq_resume(struct sys_device *dev)
  71 {
  72         /* disable all irq sources */
  73         return 0;
  74 }
  75 #else
  76 #define irq_suspend NULL
  77 #define irq_resume NULL
  78 #endif
  79
  80 static struct sysdev_class irq_class = {
  81         set_kset_name("irq"),
  82         .suspend        = irq_suspend,
  83         .resume         = irq_resume,
  84 };
  85
  86 static struct sys_device irq_device = {
  87         .id     = 0,
  88         .cls    = &irq_class,
  89 };
  90
  91 static int __init irq_init_sysfs(void)
  92 {
  93         int ret = sysdev_class_register(&irq_class);
  94         if (ret == 0)
  95                 ret = sysdev_register(&irq_device);
  96         return ret;
  97 }
  98
  99 device_initcall(irq_init_sysfs);
 100
 101
 102 void __init s3c44b0x_init_irq(void)
 103 {
 104         int irq;
 105
 106         for (irq = 0; irq < NR_IRQS; irq++) {
 107                 set_irq_chip(irq, &s3c44b0x_chip);
 108                 set_irq_handler(irq, do_level_IRQ);
 109                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 110         }
 111
 112         /* Note: in Samsung s3c44b0x um
 113
 114         "1. INTMSK register can be masked only when it is sure that the corresponding interrupt does not be
 115         requested. If your application should mask any interrupt mask bit(INTMSK) just when the
 116         corresponding interrupt is issued, please contact our FAE (field application engineer).
 117
 118         2. If you need that all interrupt is masked, we recommend that I/F bits in CPSR are set using MRS, MSR
 119         instructions. The I, F bit in CPSR can be masked even when any interrupt is issued."
 120
 121         */
 122         /* at this moment, the I/F bits should has been set, so it's safe to use rINTMAK */
 123
 124         /* mask and disable all further interrupts */
 125         SYSREG_SET(S3C44B0X_INTMSK, 0x07ffffff);
 126
 127         /* set all to IRQ mode, not FIQ */
 128
 129         SYSREG_SET(S3C44B0X_INTCON, 0x5);        // Vectored & IRQ & !FIQ
 130         SYSREG_SET(S3C44B0X_INTMOD, 0x00000000); // All IRQ mode
 131
 132         /* Clear Intrerrupt pending register */
 133
 134         SYSREG_OR_SET(S3C44B0X_I_ISPC, 0x7fffffff);
 135
 136         /*
 137          * enable the gloabal interrupt flag, this should be
 138          * safe now, all sources are masked out and acknowledged
 139          */
 140         SYSREG_CLR(S3C44B0X_INTMSK, 1<<26);
 141 }
 142