firmware/rolo.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 Randy D. Wood
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "config.h"
  23 #include "lcd.h"
  24 #include "lcd-remote.h"
  25 #include "thread.h"
  26 #include "kernel.h"
  27 #include "button.h"
  28 #include "file.h"
  29 #include "audio.h"
  30 #include "system.h"
  31 #include "i2c.h"
  32 #include "adc.h"
  33 #include "string.h"
  34 #include "buffer.h"
  35 #include "storage.h"
  36 #include "rolo.h"
  37
  38 #ifdef MI4_FORMAT
  39 #include "crc32-mi4.h"
  40 #undef FIRMWARE_OFFSET_FILE_CRC
  41 #undef FIRMWARE_OFFSET_FILE_DATA
  42 #define FIRMWARE_OFFSET_FILE_CRC     0xC
  43 #define FIRMWARE_OFFSET_FILE_DATA    0x200
  44 #endif
  45
  46 #if !defined(IRIVER_IFP7XX_SERIES)
  47 /* FIX: this doesn't work on iFP */
  48
  49 #define IRQ0_EDGE_TRIGGER 0x80
  50
  51 #ifdef CPU_PP
  52 /* Handle the COP properly - it needs to jump to a function outside SDRAM while
  53  * the new firmware is being loaded, and then jump to the start of SDRAM
  54  * TODO: Use the mailboxes built into the PP processor for this
  55  */
  56
  57 #if NUM_CORES > 1
  58 volatile unsigned char IDATA_ATTR cpu_message = 0;
  59 volatile unsigned char IDATA_ATTR cpu_reply = 0;
  60 extern int cop_idlestackbegin[];
  61
  62 void rolo_restart_cop(void) ICODE_ATTR;
  63 void rolo_restart_cop(void)
  64 {
  65     if (CURRENT_CORE == CPU)
  66     {
  67         /* There should be free thread slots aplenty */
  68         create_thread(rolo_restart_cop, cop_idlestackbegin, IDLE_STACK_SIZE,
  69                       0, "rolo COP" IF_PRIO(, PRIORITY_REALTIME)
  70                       IF_COP(, COP));
  71         return;
  72     }
  73
  74     COP_INT_DIS = -1;
  75
  76     /* Invalidate cache */
  77     cpucache_invalidate();
  78
  79     /* Disable cache */
  80     CACHE_CTL = CACHE_CTL_DISABLE;
  81
  82     /* Tell the main core that we're ready to reload */
  83     cpu_reply = 1;
  84
  85     /* Wait while RoLo loads the image into SDRAM */
  86     /* TODO: Accept checksum failure gracefully */
  87     while(cpu_message != 1);
  88
  89     /* Acknowledge the CPU and then reload */
  90     cpu_reply = 2;
  91
  92     asm volatile(
  93         "bx    %0   \n"
  94         : : "r"(DRAM_START)
  95     );
  96 }
  97 #endif /* NUM_CORES > 1 */
  98 #endif /* CPU_PP */
  99
 100 static void rolo_error(const char *text)
 101 {
 102     buffer_release_buffer(0);
 103     lcd_clear_display();
 104     lcd_puts(0, 0, "ROLO error:");
 105     lcd_puts_scroll(0, 1, text);
 106     lcd_update();
 107     button_get(true);
 108     button_get(true);
 109     button_get(true);
 110     lcd_stop_scroll();
 111 }
 112
 113 #if CONFIG_CPU == SH7034 || CONFIG_CPU == IMX31L
 114 /* these are in assembler file "descramble.S" for SH7034 */
 115 extern unsigned short descramble(const unsigned char* source,
 116                                  unsigned char* dest, int length);
 117 /* this is in firmware/target/arm/imx31/rolo_restart.c for IMX31 */
 118 extern void rolo_restart(const unsigned char* source, unsigned char* dest,
 119                          int length);
 120 #else
 121
 122 /* explicitly put this code in iram, ICODE_ATTR is defined to be null for some
 123    targets that are low on iram, like the gigabeat F/X */
 124 void rolo_restart(const unsigned char* source, unsigned char* dest,
 125                   long length) __attribute__ ((section(".icode")));
 126 void rolo_restart(const unsigned char* source, unsigned char* dest,
 127                   long length)
 128 {
 129     long i;
 130     unsigned char* localdest = dest;
 131
 132     /* This is the equivalent of a call to memcpy() but this must be done from
 133        iram to avoid overwriting itself and we don't want to depend on memcpy()
 134        always being in iram */
 135     for(i = 0;i < length;i++)
 136         *localdest++ = *source++;
 137
 138 #if defined(CPU_COLDFIRE)
 139     asm (
 140         "movec.l %0,%%vbr    \n"
 141         "move.l  (%0)+,%%sp  \n"
 142         "move.l  (%0),%0     \n"
 143         "jmp     (%0)        \n"
 144         : : "a"(dest)
 145     );
 146 #elif defined(CPU_PP)
 147     CPU_INT_DIS = -1;
 148
 149     /* Flush cache */
 150     cpucache_flush();
 151
 152     /* Disable cache */
 153     CACHE_CTL = CACHE_CTL_DISABLE;
 154
 155     /* Reset the memory mapping registers to zero */
 156     {
 157         volatile unsigned long *mmap_reg;
 158         for (mmap_reg = &MMAP_FIRST; mmap_reg <= &MMAP_LAST; mmap_reg++)
 159             *mmap_reg = 0;
 160     }
 161
 162 #if NUM_CORES > 1
 163     /* Tell the COP it's safe to continue rebooting */
 164     cpu_message = 1;
 165
 166     /* Wait for the COP to tell us it is rebooting */
 167     while(cpu_reply != 2);
 168 #endif
 169
 170     asm volatile(
 171         "bx    %0   \n"
 172         : : "r"(DRAM_START)
 173     );
 174
 175 #elif defined(CPU_ARM)
 176 #ifdef HAVE_CPUCACHE_INVALIDATE
 177     /* Flush and invalidate caches */
 178     cpucache_invalidate();
 179 #endif
 180     asm volatile(
 181         "bx    %0   \n"
 182         : : "r"(dest)
 183     );
 184 #elif defined(CPU_MIPS)
 185     __dcache_writeback_all();
 186     asm volatile(
 187         "jr     %0               \n"
 188         : : "r"(dest)
 189     );
 190 #endif
 191 }
 192 #endif
 193
 194 /* This is assigned in the linker control file */
 195 extern unsigned long loadaddress;
 196
 197 /***************************************************************************
 198  *
 199  * Name: rolo_load_app(char *filename,int scrambled)
 200  * Filename must be a fully defined filename including the path and extension
 201  *
 202  ***************************************************************************/
 203 int rolo_load(const char* filename)
 204 {
 205     int fd;
 206     long length;
 207 #if defined(CPU_COLDFIRE) || defined(CPU_ARM) || defined(CPU_MIPS)
 208 #if !defined(MI4_FORMAT)
 209     int i;
 210 #endif
 211     unsigned long checksum,file_checksum;
 212 #else
 213     long file_length;
 214     unsigned short checksum,file_checksum;
 215 #endif
 216     unsigned char* ramstart = (void*)&loadaddress;
 217     unsigned char* filebuf;
 218     size_t filebuf_size;
 219
 220     lcd_clear_display();
 221     lcd_puts(0, 0, "ROLO...");
 222     lcd_puts(0, 1, "Loading");
 223     lcd_update();
 224 #ifdef HAVE_REMOTE_LCD
 225     lcd_remote_clear_display();
 226     lcd_remote_puts(0, 0, "ROLO...");
 227     lcd_remote_puts(0, 1, "Loading");
 228     lcd_remote_update();
 229 #endif
 230
 231     audio_stop();
 232
 233     fd = open(filename, O_RDONLY);
 234     if(-1 == fd) {
 235         rolo_error("File not found");
 236         return -1;
 237     }
 238
 239     length = filesize(fd) - FIRMWARE_OFFSET_FILE_DATA;
 240
 241     /* get the system buffer. release only in case of error, otherwise
 242      * we don't return anyway */
 243     filebuf = buffer_get_buffer(&filebuf_size);
 244
 245 #if CONFIG_CPU != SH7034
 246     /* Read and save checksum */
 247     lseek(fd, FIRMWARE_OFFSET_FILE_CRC, SEEK_SET);
 248     if (read(fd, &file_checksum, 4) != 4) {
 249         rolo_error("Error Reading checksum");
 250         return -1;
 251     }
 252
 253 #if !defined(MI4_FORMAT)
 254     /* Rockbox checksums are big-endian */
 255     file_checksum = betoh32(file_checksum);
 256 #endif
 257
 258 #if defined(CPU_PP) && NUM_CORES > 1
 259     lcd_puts(0, 2, "Waiting for coprocessor...");
 260     lcd_update();
 261     rolo_restart_cop();
 262     /* Wait for COP to be in safe code */
 263     while(cpu_reply != 1);
 264     lcd_puts(0, 2, "                          ");
 265     lcd_update();
 266 #endif
 267
 268     lseek(fd, FIRMWARE_OFFSET_FILE_DATA, SEEK_SET);
 269
 270     /* this shouldn't happen, but well */
 271     if ((long)filebuf_size < length)
 272     {
 273         rolo_error("File too big");
 274         return -1;
 275     }
 276
 277     if (read(fd, filebuf, length) != length) {
 278         rolo_error("Error Reading File");
 279         return -1;
 280     }
 281
 282 #ifdef MI4_FORMAT
 283     /* Check CRC32 to see if we have a valid file */
 284     chksum_crc32gentab();
 285     checksum = chksum_crc32 (filebuf, length);
 286 #else
 287     checksum = MODEL_NUMBER;
 288
 289     for(i = 0;i < length;i++) {
 290         checksum += filebuf[i];
 291     }
 292 #endif
 293
 294     /* Verify checksum against file header */
 295     if (checksum != file_checksum) {
 296         rolo_error("Checksum Error");
 297         return -1;
 298     }
 299
 300 #ifdef HAVE_STORAGE_FLUSH
 301     lcd_puts(0, 1, "Flushing storage buffers");
 302     lcd_update();
 303     storage_flush();
 304 #endif
 305
 306     lcd_puts(0, 1, "Executing");
 307     lcd_update();
 308 #ifdef HAVE_REMOTE_LCD
 309     lcd_remote_puts(0, 1, "Executing");
 310     lcd_remote_update();
 311 #endif
 312     adc_close();
 313
 314 #if CONFIG_CPU != IMX31L /* We're not finished yet */
 315 #ifdef CPU_ARM
 316     /* Should do these together since some ARM version should never have
 317      * FIQ disabled and not IRQ (imx31 errata). */
 318     disable_interrupt(IRQ_FIQ_STATUS);
 319 #else
 320     /* Some targets have a higher disable level than HIGEST_IRQ_LEVEL */
 321     set_irq_level(DISABLE_INTERRUPTS);
 322 #endif
 323 #endif /* CONFIG_CPU == IMX31L */
 324
 325 #else /* CONFIG_CPU == SH7034 */
 326     /* Read file length from header and compare to real file length */
 327     lseek(fd, FIRMWARE_OFFSET_FILE_LENGTH, SEEK_SET);
 328     if(read(fd, &file_length, 4) != 4) {
 329         rolo_error("Error Reading File Length");
 330         return -1;
 331     }
 332     if (length != file_length) {
 333         rolo_error("File length mismatch");
 334         return -1;
 335     }
 336
 337     /* Read and save checksum */
 338     lseek(fd, FIRMWARE_OFFSET_FILE_CRC, SEEK_SET);
 339     if (read(fd, &file_checksum, 2) != 2) {
 340         rolo_error("Error Reading checksum");
 341         return -1;
 342     }
 343     lseek(fd, FIRMWARE_OFFSET_FILE_DATA, SEEK_SET);
 344
 345     /* verify that file can be read and descrambled */
 346     if ((size_t)((2*length)+4) >= filebuf_size) {
 347         rolo_error("Not enough room to load file");
 348         return -1;
 349     }
 350
 351     if (read(fd, &filebuf[length], length) != (int)length) {
 352         rolo_error("Error Reading File");
 353         return -1;
 354     }
 355
 356     lcd_puts(0, 1, "Descramble");
 357     lcd_update();
 358
 359     checksum = descramble(filebuf + length, filebuf, length);
 360
 361     /* Verify checksum against file header */
 362     if (checksum != file_checksum) {
 363         rolo_error("Checksum Error");
 364         return -1;
 365     }
 366
 367 #ifdef HAVE_STORAGE_FLUSH
 368     lcd_puts(0, 1, "Flushing      ");
 369     lcd_update();
 370     storage_flush();
 371 #endif
 372
 373     lcd_puts(0, 1, "Executing     ");
 374     lcd_update();
 375
 376     set_irq_level(HIGHEST_IRQ_LEVEL);
 377
 378     /* Calling these 2 initialization routines was necessary to get the
 379        the origional Archos version of the firmware to load and execute. */
 380     system_init();           /* Initialize system for restart */
 381     i2c_init();              /* Init i2c bus - it seems like a good idea */
 382     ICR = IRQ0_EDGE_TRIGGER; /* Make IRQ0 edge triggered */
 383     TSTR = 0xE0;             /* disable all timers */
 384     /* model-specific de-init, needed when flashed */
 385     /* Especially the Archos software is picky about this */
 386 #if defined(ARCHOS_RECORDER) || defined(ARCHOS_RECORDERV2) || \
 387     defined(ARCHOS_FMRECORDER)
 388     PAIOR = 0x0FA0;
 389 #endif
 390 #endif
 391     rolo_restart(filebuf, ramstart, length);
 392
 393     return 0; /* this is never reached */
 394     (void)checksum; (void)file_checksum;
 395 }
 396 #else  /* !defined(IRIVER_IFP7XX_SERIES) */
 397 int rolo_load(const char* filename)
 398 {
 399     /* dummy */
 400     (void)filename;
 401     return 0;
 402 }
 403
 404 #endif /* !defined(IRIVER_IFP7XX_SERIES) */