firmware/export/as3525.h

   1 /*
   2 * (C) Copyright 2006
   3 * Copyright (C) 2006 Austriamicrosystems, by thomas.luo
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License as
   7 * published by the Free Software Foundation; either version 2 of
   8 * the License, or (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 * MA 02111-1307 USA
  19 */
  20 #ifndef __AS3525_H__
  21 #define __AS3525_H__
  22
  23 #define UART_CHANNELS 1
  24
  25 /* AS352X only supports 512 Byte HW ECC */
  26 #define ECCSIZE 512
  27 #define ECCBYTES 3
  28
  29
  30 /* AS352X device base addresses */
  31
  32
  33 /*
  34 ------------------------------------------------------------------------
  35 *  AS352X Registers
  36 *
  37 ------------------------------------------------------------------------
  38 *
  39 */
  40
  41
  42 /* AHB */
  43 #define USB_BASE             0xC6000000
  44 #define VIC_BASE             0xC6010000
  45 #define DMAC_BASE            0xC6020000
  46 #define MPMC_BASE            0xC6030000
  47 #define MEMSTICK_BASE        0xC6040000
  48 #define CF_IDE_BASE          0xC6050000
  49
  50 /* APB */
  51 #define NAND_FLASH_BASE      0xC8000000
  52 #define BIST_MANAGER_BASE    0xC8010000
  53 #define SD_MCI_BASE          0xC8020000
  54 #define TIMER_BASE           0xC8040000
  55 #define WDT_BASE             0xC8050000
  56 #define I2C_MS_BASE          0xC8060000
  57 #define I2C_AUDIO_BASE       0xC8070000
  58 #define SSP_BASE             0xC8080000
  59 #define I2SIN_BASE           0xC8090000
  60 #define I2SOUT_BASE          0xC80A0000
  61 #define GPIOA_BASE           0xC80B0000
  62 #define GPIOB_BASE           0xC80C0000
  63 #define GPIOC_BASE           0xC80D0000
  64 #define GPIOD_BASE           0xC80E0000
  65 #define CGU_BASE             0xC80F0000
  66 #define CCU_BASE             0xC8100000
  67 #define UART0_BASE           0xC8110000
  68 #define DBOP_BASE            0xC8120000
  69
  70
  71
  72
  73
  74
  75
  76
  77 /*
  78 ------------------------------------------------------------------------
  79 *  AS352X control registers
  80 *
  81 ------------------------------------------------------------------------
  82 */
  83
  84 #define CCU_SRC           (*(volatile unsigned long *)(CCU_BASE + 0x00))
  85 #define CCU_SRL           (*(volatile unsigned long *)(CCU_BASE + 0x04))
  86 #define CCU_MEMMAP        (*(volatile unsigned long *)(CCU_BASE + 0x08))
  87 #define CCU_IO            (*(volatile unsigned long *)(CCU_BASE + 0x0C))
  88 #define CCU_SCON          (*(volatile unsigned long *)(CCU_BASE + 0x10))
  89 #define CCU_VERS          (*(volatile unsigned long *)(CCU_BASE + 0x14))
  90 #define CCU_SPARE1        (*(volatile unsigned long *)(CCU_BASE + 0x18))
  91 #define CCU_SPARE2        (*(volatile unsigned long *)(CCU_BASE + 0x1C))
  92
  93 /* DBOP */
  94 #define DBOP_TIMPOL_01    (*(volatile unsigned long *)(DBOP_BASE + 0x00))
  95 #define DBOP_TIMPOL_23    (*(volatile unsigned long *)(DBOP_BASE + 0x04))
  96 #define DBOP_CTRL         (*(volatile unsigned long *)(DBOP_BASE + 0x08))
  97 #define DBOP_STAT         (*(volatile unsigned long *)(DBOP_BASE + 0x0C))
  98 #define DBOP_DOUT         (*(volatile unsigned short*)(DBOP_BASE + 0x10))
  99 #define DBOP_DIN          (*(volatile unsigned long *)(DBOP_BASE + 0x14))
 100
 101
 102 /**
 103 * Reset Control Lines in CCU_SRC register
 104 **/
 105 #define CCU_SRC_DBOP_EN        ( 1 << 24 )
 106 #define CCU_SRC_SPDIF_EN       ( 1 << 22 )
 107 #define CCU_SRC_TIMER_EN       ( 1 << 21 )
 108 #define CCU_SRC_SSP_EN         ( 1 << 20 )
 109 #define CCU_SRC_WDO_EN         ( 1 << 19 )
 110 #define CCU_SRC_IDE_EN         ( 1 << 18 )
 111 #define CCU_SRC_IDE_AHB_EN     ( 1 << 17 )
 112 #define CCU_SRC_UART0          ( 1 << 16 )
 113 #define CCU_SRC_NAF_EN         ( 1 << 15 )
 114 #define CCU_SRC_SDMCI_EN       ( 1 << 14 )
 115 #define CCU_SRC_GPIO_EN        ( 1 << 13 )
 116 #define CCU_SRC_I2C_AUDIO_EN   ( 1 << 12 )
 117 #define CCU_SRC_I2C_EN         ( 1 << 11 )
 118 #define CCU_SRC_MST_EN         ( 1 << 10 )
 119 #define CCU_SRC_I2SIN          ( 1 <<  9 )
 120 #define CCU_SRC_I2SOUT         ( 1 <<  8 )
 121 #define CCU_SRC_USB_AHB_EN     ( 1 <<  7 )
 122 #define CCU_SRC_USB_PHY_EN     ( 1 <<  6 )
 123 #define CCU_SRC_DMAC_EN        ( 1 <<  5 )
 124 #define CCU_SRC_VIC_EN         ( 1 <<  4 )
 125
 126 /**
 127 * Magic number for CCU_SRL for reset.
 128 **/
 129 #define CCU_SRL_MAGIC_NUMBER      0x1A720212
 130
 131 /**
 132 * Chip select lines for NAF. Use these constants to select/deselct the
 133 CE lines
 134 * for NAND flashes in Register CCU_IO.
 135 **/
 136 #define CCU_IO_NAF_CE_LINE_0      ( 0 << 7 )
 137 #define CCU_IO_NAF_CE_LINE_1      ( 1 << 7 )
 138 #define CCU_IO_NAF_CE_LINE_2      ( 2 << 7 )
 139 #define CCU_IO_NAF_CE_LINE_3      ( 3 << 7 )
 140
 141 /* CCU IO Select/Deselect IDE */
 142 #define CCU_IO_IDE                ( 1 << 5 )
 143
 144 /* CCU IO Select/desect I2C */
 145 #define CCU_IO_I2C_MASTER_SLAVE   ( 1 << 1 )
 146
 147 /* CCU IO Select/desect UART */
 148 #define CCU_IO_UART0               ( 1 << 0 )
 149
 150
 151 #define CCU_RESET_ALL_BUT_MEMORY \
 152  ( CCU_SRC_DBOP_EN        \
 153  | CCU_SRC_SPDIF_EN       \
 154  | CCU_SRC_TIMER_EN       \
 155  | CCU_SRC_SSP_EN         \
 156  | CCU_SRC_WDO_EN         \
 157  | CCU_SRC_IDE_EN         \
 158  | CCU_SRC_IDE_AHB_EN     \
 159  | CCU_SRC_UART0          \
 160  | CCU_SRC_NAF_EN         \
 161  | CCU_SRC_SDMCI_EN       \
 162  | CCU_SRC_GPIO_EN        \
 163  | CCU_SRC_I2C_AUDIO_EN   \
 164  | CCU_SRC_I2C_EN         \
 165  | CCU_SRC_MST_EN         \
 166  | CCU_SRC_I2SIN          \
 167  | CCU_SRC_I2SOUT         \
 168  | CCU_SRC_USB_AHB_EN     \
 169  | CCU_SRC_USB_PHY_EN     \
 170  | CCU_SRC_DMAC_EN        \
 171  | CCU_SRC_VIC_EN         \
 172  )
 173
 174 #define CCU_IO_UART               ( 1 << 0 )
 175 /*
 176 ------------------------------------------------------------------------
 177 *  AS352X clock control registers
 178 *
 179 ------------------------------------------------------------------------
 180 */
 181
 182 #define CGU_PLLA         (*(volatile unsigned long *)(CGU_BASE + 0x00))
 183 #define CGU_PLLB         (*(volatile unsigned long *)(CGU_BASE + 0x04))
 184 #define CGU_PLLASUP      (*(volatile unsigned long *)(CGU_BASE + 0x08))
 185 #define CGU_PLLBSUP      (*(volatile unsigned long *)(CGU_BASE + 0x0C))
 186 #define CGU_PROC         (*(volatile unsigned long *)(CGU_BASE + 0x10))
 187 #define CGU_PERI         (*(volatile unsigned long *)(CGU_BASE + 0x14))
 188 #define CGU_AUDIO        (*(volatile unsigned long *)(CGU_BASE + 0x18))
 189 #define CGU_USB          (*(volatile unsigned long *)(CGU_BASE + 0x1C))
 190 #define CGU_INTCTRL      (*(volatile unsigned long *)(CGU_BASE + 0x20))
 191 #define CGU_IRQ          (*(volatile unsigned long *)(CGU_BASE + 0x24))
 192 #define CGU_COUNTA       (*(volatile unsigned long *)(CGU_BASE + 0x28))
 193 #define CGU_COUNTB       (*(volatile unsigned long *)(CGU_BASE + 0x2C))
 194 #define CGU_IDE          (*(volatile unsigned long *)(CGU_BASE + 0x30))
 195 #define CGU_MEMSTICK     (*(volatile unsigned long *)(CGU_BASE + 0x34))
 196 #define CGU_DBOP         (*(volatile unsigned long *)(CGU_BASE + 0x38))
 197
 198 #define CGU_VIC_CLOCK_ENABLE                 ( 1 << 23 ) /* vic */
 199 /* --- are disabled after reset --- */
 200 #define CGU_DMA_CLOCK_ENABLE                 ( 1 << 22 ) /* dma */
 201 #define CGU_USB_CLOCK_ENABLE                 ( 1 << 21 ) /* usb */
 202 #define CGU_I2SOUT_APB_CLOCK_ENABLE          ( 1 << 20 ) /* i2sout */
 203 #define CGU_I2SIN_APB_CLOCK_ENABLE           ( 1 << 19 ) /* i2sin */
 204 #define CGU_I2C_MASTER_SLAVE_CLOCK_ENABLE    ( 1 << 18 ) /* i2c master/slave */
 205 #define CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE    ( 1 << 17 ) /* i2c audio master */
 206 #define CGU_GPIO_CLOCK_ENABLE                ( 1 << 16 ) /* gpio */
 207 #define CGU_MCI_CLOCK_ENABLE                 ( 1 << 15 ) /* mmc + sd */
 208 #define CGU_NAF_CLOCK_ENABLE                 ( 1 << 14 ) /* naf */
 209 #define CGU_UART_APB_CLOCK_ENABLE            ( 1 << 13 ) /* uart */
 210 #define CGU_WDOCNT_CLOCK_ENABLE              ( 1 << 12 ) /* watchdog counter */
 211 #define CGU_WDOIF_CLOCK_ENABLE               ( 1 << 11 ) /* watchdog timer module */
 212 #define CGU_SSP_CLOCK_ENABLE                 ( 1 << 10 ) /* ssp */
 213 #define CGU_TIMER1_CLOCK_ENABLE              ( 1 <<  9 ) /* timer 1 */
 214 #define CGU_TIMER2_CLOCK_ENABLE              ( 1 <<  8 ) /* timer 2 */
 215 #define CGU_TIMERIF_CLOCK_ENABLE             ( 1 <<  7 ) /* timer
 216 interface */
 217
 218 /**  ------------------------------------------------------------------
 219 * Number of cycles to wait before cgu is safely locked.
 220 **/
 221 #define CGU_LOCK_CNT 0xFF
 222
 223 /* FIFO depth is 16 for tx and rx fifo */
 224 #define UART_FIFO_DEPTH           16
 225
 226 /* ------------------- UART Line Control Register bit fields -------------------- */
 227
 228 #define UART_LNCTL_DLSEN          (1 << 7) /* Device latch select bit */
 229
 230
 231 /* --------------   UART Interrupt Control Register bit fields --------------- */
 232
 233 #define UART_INTR_RXDRDY           0x1 /* Data ready interrupt */
 234 #define UART_INTR_TXEMT            0x2 /* Transmit data empty interrupt */
 235 #define UART_INTR_RXLINESTATUS     0x4 /* Receive line status interrupt */
 236
 237 /* ------------------- UART Line Status Register bit fields --------------------  */
 238
 239 #define UART_ERRORBITS             0x1E
 240 #define UART_RX_DATA_READY        (1 << 0)
 241 #define UART_TX_HOLD_EMPTY    (1 << 5)
 242
 243 /* -------------------        FIFO CNTL Register contants -------------------*/
 244
 245 #define UART_FIFO_EN              (1 << 0)  /* Enable the UART FIFO */
 246 #define UART_TX_FIFO_RST          (1 << 1)  /* Enable the UART FIFO */
 247 #define UART_RX_FIFO_RST          (1 << 2)
 248 #define UART_RXFIFO_TRIGLVL_1     (0 << 4) /* RX FIFO TRIGGER_LEVEL 1 */
 249 #define UART_RXFIFO_TRIGLVL_4      0x08    /* RX FIFO TRIGGER_LEVEL 4 */
 250 #define UART_RXFIFO_TRIGLVL_8      0x10    /* RX FIFO TRIGGER_LEVEL 8 */
 251 #define UART_RXFIFO_TRIGLVL_14     0x18    /* RX FIFO TRIGGER_LEVEL 14 */
 252
 253
 254 /* -------------------        FIFO status Register contants ------------------*/
 255 #define UART_TX_FIFO_FULL         (1 << 0)
 256 #define UART_RX_FIFO_FULL         (1 << 1)
 257 #define UART_TX_FIFO_EMPTY        (1 << 2)
 258 #define UART_RX_FIFO_EMPTY        (1 << 3)
 259
 260
 261 /* ----------------------- defines ---------------------------------------- */
 262
 263
 264
 265 #define UART_DATA_REG       (*(volatile unsigned long*)(UART0_BASE + 0x00)) /* Data register */
 266 #define UART_DLO_REG        (*(volatile unsigned long*)(UART0_BASE + 0x00)) /* Clock divider(lower byte) register */
 267 #define UART_DHI_REG        (*(volatile unsigned long*)(UART0_BASE + 0x04)) /* Clock divider(higher byte) register */
 268 #define UART_INTEN_REG      (*(volatile unsigned long*)(UART0_BASE + 0x04)) /* Interrupt enable register */
 269 #define UART_INTSTATUS_REG  (*(volatile unsigned long*)(UART0_BASE + 0x08)) /* Interrupt status register */
 270 #define UART_FCTL_REG       (*(volatile unsigned long*)(UART0_BASE + 0x0C)) /* Fifo control  register */
 271 #define UART_FSTATUS_REG    (*(volatile unsigned long*)(UART0_BASE + 0x0C)) /* Fifo status register */
 272 #define UART_LNCTL_REG      (*(volatile unsigned long*)(UART0_BASE + 0x10)) /* Line control register */
 273 #define UART_LNSTATUS_REG   (*(volatile unsigned long*)(UART0_BASE + 0x14)) /* Line status register */
 274
 275
 276
 277
 278 #define TIMER1_LOAD      (*(volatile unsigned long*)(TIMER_BASE + 0x00)) /* 32-bit width */
 279 #define TIMER1_VALUE     (*(volatile unsigned long*)(TIMER_BASE + 0x04)) /* 32 bit width */
 280 #define TIMER1_CONTROL   (*(volatile unsigned long*)(TIMER_BASE + 0x08)) /*  8 bit width */
 281 #define TIMER1_INTCLR    (*(volatile unsigned long*)(TIMER_BASE + 0x0C)) /* clears ir by write access */
 282 #define TIMER1_RIS       (*(volatile unsigned long*)(TIMER_BASE + 0x10)) /*  1 bit width */
 283 #define TIMER1_MIS       (*(volatile unsigned long*)(TIMER_BASE + 0x14)) /*  1 bit width */
 284 #define TIMER1_BGLOAD    (*(volatile unsigned long*)(TIMER_BASE + 0x18)) /* 32-bit width */
 285
 286 #define TIMER2_LOAD      (*(volatile unsigned long*)(TIMER_BASE + 0x20)) /* 32-bit width */
 287 #define TIMER2_VALUE     (*(volatile unsigned long*)(TIMER_BASE + 0x24)) /* 32 bit width */
 288 #define TIMER2_CONTROL   (*(volatile unsigned long*)(TIMER_BASE + 0x28)) /*  8 bit width */
 289 #define TIMER2_INTCLR    (*(volatile unsigned long*)(TIMER_BASE + 0x2C)) /* clears ir by write access */
 290 #define TIMER2_RIS       (*(volatile unsigned long*)(TIMER_BASE + 0x30)) /*  1 bit width */
 291 #define TIMER2_MIS       (*(volatile unsigned long*)(TIMER_BASE + 0x34)) /*  1 bit width */
 292 #define TIMER2_BGLOAD    (*(volatile unsigned long*)(TIMER_BASE + 0x38)) /* 32-bit width */
 293
 294 /**
 295 * Counter/Timer control register bits
 296 **/
 297 #define TIMER_ENABLE       0x80
 298 #define TIMER_PERIODIC     0x40
 299 #define TIMER_INT_ENABLE   0x20
 300 #define TIMER_32_BIT   0x02
 301 #define TIMER_ONE_SHOT   0x01
 302 #define TIMER_PRESCALE_1   0x00
 303 #define TIMER_PRESCALE_16   0x04
 304 #define TIMER_PRESCALE_256 0x08
 305
 306 /* GPIO registers */
 307
 308 #define GPIOA_DIR       (*(volatile unsigned char*)(GPIOA_BASE+0x400))
 309 #define GPIOA_AFSEL     (*(volatile unsigned char*)(GPIOA_BASE+0x420))
 310 #define GPIOA_PIN(a)    (*(volatile unsigned char*)(GPIOA_BASE+4*(1<<(a))))
 311
 312 #define GPIOB_DIR       (*(volatile unsigned char*)(GPIOB_BASE+0x400))
 313 #define GPIOB_AFSEL     (*(volatile unsigned char*)(GPIOB_BASE+0x420))
 314 #define GPIOB_PIN(a)    (*(volatile unsigned char*)(GPIOB_BASE+4*(1<<(a))))
 315
 316 #define GPIOC_DIR       (*(volatile unsigned char*)(GPIOC_BASE+0x400))
 317 #define GPIOC_AFSEL     (*(volatile unsigned char*)(GPIOC_BASE+0x420))
 318 #define GPIOC_PIN(a)    (*(volatile unsigned char*)(GPIOC_BASE+4*(1<<(a))))
 319
 320 #define GPIOD_DIR       (*(volatile unsigned char*)(GPIOD_BASE+0x400))
 321 #define GPIOD_AFSEL     (*(volatile unsigned char*)(GPIOD_BASE+0x420))
 322 #define GPIOD_PIN(a)    (*(volatile unsigned char*)(GPIOD_BASE+4*(1<<(a))))
 323
 324 /* ARM PL172 Memory Controller registers */
 325
 326 #define MPMC_CONTROL              (*(volatile unsigned long*)(MPMC_BASE+0x000))
 327 #define MPMC_STATUS               (*(volatile unsigned long*)(MPMC_BASE+0x004))
 328 #define MPMC_CONFIG               (*(volatile unsigned long*)(MPMC_BASE+0x008))
 329
 330 #define MPMC_DYNAMIC_CONTROL      (*(volatile unsigned long*)(MPMC_BASE+0x020))
 331 #define MPMC_DYNAMIC_REFRESH      (*(volatile unsigned long*)(MPMC_BASE+0x024))
 332 #define MPMC_DYNAMIC_READ_CONFIG  (*(volatile unsigned long*)(MPMC_BASE+0x028))
 333 #define MPMC_DYNAMIC_tRP          (*(volatile unsigned long*)(MPMC_BASE+0x030))
 334 #define MPMC_DYNAMIC_tRAS         (*(volatile unsigned long*)(MPMC_BASE+0x034))
 335 #define MPMC_DYNAMIC_tSREX        (*(volatile unsigned long*)(MPMC_BASE+0x038))
 336 #define MPMC_DYNAMIC_tAPR         (*(volatile unsigned long*)(MPMC_BASE+0x03C))
 337 #define MPMC_DYNAMIC_tDAL         (*(volatile unsigned long*)(MPMC_BASE+0x040))
 338 #define MPMC_DYNAMIC_tWR          (*(volatile unsigned long*)(MPMC_BASE+0x044))
 339 #define MPMC_DYNAMIC_tRC          (*(volatile unsigned long*)(MPMC_BASE+0x048))
 340 #define MPMC_DYNAMIC_tRFC         (*(volatile unsigned long*)(MPMC_BASE+0x04C))
 341 #define MPMC_DYNAMIC_tXSR         (*(volatile unsigned long*)(MPMC_BASE+0x050))
 342 #define MPMC_DYNAMIC_tRRD         (*(volatile unsigned long*)(MPMC_BASE+0x054))
 343 #define MPMC_DYNAMIC_tMRD         (*(volatile unsigned long*)(MPMC_BASE+0x058))
 344
 345 #define MPMC_STATIC_EXTENDED_WAIT (*(volatile unsigned long*)(MPMC_BASE+0x080))
 346
 347 #define MPMC_DYNAMIC_CONFIG_0     (*(volatile unsigned long*)(MPMC_BASE+0x100))
 348 #define MPMC_DYNAMIC_CONFIG_1     (*(volatile unsigned long*)(MPMC_BASE+0x120))
 349 #define MPMC_DYNAMIC_CONFIG_2     (*(volatile unsigned long*)(MPMC_BASE+0x140))
 350 #define MPMC_DYNAMIC_CONFIG_3     (*(volatile unsigned long*)(MPMC_BASE+0x160))
 351
 352 #define MPMC_DYNAMIC_RASCAS_0     (*(volatile unsigned long*)(MPMC_BASE+0x104))
 353 #define MPMC_DYNAMIC_RASCAS_1     (*(volatile unsigned long*)(MPMC_BASE+0x124))
 354 #define MPMC_DYNAMIC_RASCAS_2     (*(volatile unsigned long*)(MPMC_BASE+0x144))
 355 #define MPMC_DYNAMIC_RASCAS_3     (*(volatile unsigned long*)(MPMC_BASE+0x164))
 356
 357 #define MPMC_PERIPH_ID2           (*(volatile unsigned long*)(MPMC_BASE+0xFE8))
 358
 359 /* VIC controller (PL190) registers */
 360
 361 #define VIC_IRQ_STATUS      (*(volatile unsigned long*)(VIC_BASE+0x00))
 362 #define VIC_FIQ_STATUS      (*(volatile unsigned long*)(VIC_BASE+0x04))
 363 #define VIC_RAW_INTR        (*(volatile unsigned long*)(VIC_BASE+0x08))
 364 #define VIC_INT_SELECT      (*(volatile unsigned long*)(VIC_BASE+0x0C))
 365 #define VIC_INT_ENABLE      (*(volatile unsigned long*)(VIC_BASE+0x10))
 366 #define VIC_INT_EN_CLEAR    (*(volatile unsigned long*)(VIC_BASE+0x14))
 367 #define VIC_SOFT_INT        (*(volatile unsigned long*)(VIC_BASE+0x18))
 368 #define VIC_SOFT_INT_CLEAR  (*(volatile unsigned long*)(VIC_BASE+0x1C))
 369 #define VIC_PROTECTION      (*(volatile unsigned long*)(VIC_BASE+0x20))
 370 #define VIC_VECT_ADDR       (*(volatile unsigned long*)(VIC_BASE+0x30))
 371 #define VIC_DEF_VECT_ADDR   (*(volatile unsigned long*)(VIC_BASE+0x34))
 372
 373 /* Interrupts */
 374 #define INTERRUPT_WATCHDOG      (1<<0)
 375 #define INTERRUPT_TIMER1        (1<<1)
 376 #define INTERRUPT_TIMER2        (1<<2)
 377 #define INTERRUPT_USB           (1<<3)
 378 #define INTERRUPT_DMAC          (1<<4)
 379 #define INTERRUPT_NAND          (1<<5)
 380 #define INTERRUPT_IDE           (1<<6)
 381 #define INTERRUPT_MCI0          (1<<1<<7)
 382 #define INTERRUPT_MCI1          (1<<8)
 383 #define INTERRUPT_AUDIO         (1<<9)
 384 #define INTERRUPT_SSP           (1<<10)
 385 #define INTERRUPT_I2C_MS        (1<<11)
 386 #define INTERRUPT_I2C_AUDIO     (1<<12)
 387 #define INTERRUPT_I2SIN         (1<<13)
 388 #define INTERRUPT_I2SOUT        (1<<14)
 389 #define INTERRUPT_UART          (1<<15)
 390 #define INTERRUPT_GPIOD         (1<<16)
 391 /* 17 reserved */
 392 #define INTERRUPT_CGU           (1<<18)
 393 #define INTERRUPT_MEMORY_STICK  (1<<19)
 394 #define INTERRUPT_DBOP          (1<<20)
 395 /* 21-28 reserved */
 396 #define INTERRUPT_GPIOA         (1<<29)
 397 #define INTERRUPT_GPIOB         (1<<30)
 398 #define INTERRUPT_GPIOC         (1<<31)
 399
 400 #endif /*__AS3525_H__*/