firmware/export/imx31l.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 by James Espinoza
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef __IMX31L_H__
  22 #define __IMX31L_H__
  23
  24 /* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/
  25
  26 #define REG8_PTR_T  volatile unsigned char *
  27 #define REG16_PTR_T volatile unsigned short *
  28 #define REG32_PTR_T volatile unsigned long *
  29
  30 /* Place in the section with the framebuffer */
  31 #define TTB_BASE_ADDR (CSD0_BASE_ADDR + (MEM*0x100000) - TTB_SIZE)
  32 #define TTB_SIZE      (0x4000)
  33 #define IRAM_SIZE     (0x4000)
  34 #define TTB_BASE      ((unsigned long *)TTB_BASE_ADDR)
  35 #define FRAME_SIZE    (240*320*2)
  36 /* Rockbox framebuffer address, not retail OS */
  37 #define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE)
  38 #define FRAME         ((void *)(FRAME_PHYS_ADDR-CSD0_BASE_ADDR))
  39
  40 #define DEVBSS_ATTR   __attribute__((section(".devbss"),nocommon))
  41 /* USBOTG */
  42 #define USB_QHARRAY_ATTR    __attribute__((section(".qharray"),nocommon,aligned(2048)))
  43 #define USB_NUM_ENDPOINTS   8
  44 #define USB_DEVBSS_ATTR     DEVBSS_ATTR
  45 #define USB_BASE            OTG_BASE_ADDR
  46
  47 /*
  48  * AIPS 1
  49  */
  50 #define IRAM_BASE_ADDR          0x1fffc000
  51 #define L2CC_BASE_ADDR          0x30000000
  52 #define AIPS1_BASE_ADDR         0x43F00000
  53 #define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
  54 #define MAX_BASE_ADDR           0x43F04000
  55 #define EVTMON_BASE_ADDR        0x43F08000
  56 #define CLKCTL_BASE_ADDR        0x43F0C000
  57 #define ETB_SLOT4_BASE_ADDR     0x43F10000
  58 #define ETB_SLOT5_BASE_ADDR     0x43F14000
  59 #define ECT_CTIO_BASE_ADDR      0x43F18000
  60 #define I2C1_BASE_ADDR          0x43F80000
  61 #define I2C3_BASE_ADDR          0x43F84000
  62 #define OTG_BASE_ADDR           0x43F88000
  63 #define ATA_BASE_ADDR           0x43F8C000
  64 #define UART1_BASE_ADDR         0x43F90000
  65 #define UART2_BASE_ADDR         0x43F94000
  66 #define I2C2_BASE_ADDR          0x43F98000
  67 #define OWIRE_BASE_ADDR         0x43F9C000
  68 #define SSI1_BASE_ADDR          0x43FA0000
  69 #define CSPI1_BASE_ADDR         0x43FA4000
  70 #define KPP_BASE_ADDR           0x43FA8000
  71 #define IOMUXC_BASE_ADDR        0x43FAC000
  72 #define UART4_BASE_ADDR         0x43FB0000
  73 #define UART5_BASE_ADDR         0x43FB4000
  74 #define ECT_IP1_BASE_ADDR       0x43FB8000
  75 #define ECT_IP2_BASE_ADDR       0x43FBC000
  76
  77 /*
  78  * SPBA
  79  */
  80 #define SPBA_BASE_ADDR          0x50000000
  81 #define MMC_SDHC1_BASE_ADDR     0x50004000
  82 #define MMC_SDHC2_BASE_ADDR     0x50008000
  83 #define UART3_BASE_ADDR         0x5000C000
  84 #define CSPI2_BASE_ADDR         0x50010000
  85 #define SSI2_BASE_ADDR          0x50014000
  86 #define SIM_BASE_ADDR           0x50018000
  87 #define IIM_BASE_ADDR           0x5001C000
  88 #define ATA_DMA_BASE_ADDR       0x50020000
  89 #define SPBA_CTRL_BASE_ADDR     0x5003C000
  90
  91 /*
  92  * AIPS 2
  93  */
  94 #define AIPS2_BASE_ADDR         0x53F00000
  95 #define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
  96 #define CCM_BASE_ADDR           0x53F80000
  97 #define CSPI3_BASE_ADDR         0x53F84000
  98 #define FIRI_BASE_ADDR          0x53F8C000
  99 #define GPT1_BASE_ADDR          0x53F90000
 100 #define EPIT1_BASE_ADDR         0x53F94000
 101 #define EPIT2_BASE_ADDR         0x53F98000
 102 #define GPIO3_BASE_ADDR         0x53FA4000
 103 #define SCC_BASE                0x53FAC000
 104 #define SCM_BASE                0x53FAE000
 105 #define SMN_BASE                0x53FAF000
 106 #define RNGA_BASE_ADDR          0x53FB0000
 107 #define IPU_CTRL_BASE_ADDR      0x53FC0000
 108 #define AUDMUX_BASE             0x53FC4000
 109 #define MPEG4_ENC_BASE          0x53FC8000
 110 #define GPIO1_BASE_ADDR         0x53FCC000
 111 #define GPIO2_BASE_ADDR         0x53FD0000
 112 #define SDMA_BASE_ADDR          0x53FD4000
 113 #define RTC_BASE_ADDR           0x53FD8000
 114 #define WDOG_BASE_ADDR          0x53FDC000
 115 #define PWM_BASE_ADDR           0x53FE0000
 116 #define RTIC_BASE_ADDR          0x53FEC000
 117
 118 #define WDOG1_BASE_ADDR         WDOG_BASE_ADDR
 119 #define CRM_MCU_BASE_ADDR       CCM_BASE_ADDR
 120
 121 /* IOMUXC */
 122 #define IOMUXC_(o)              (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o)))
 123
 124 /* GPR */
 125 #define IOMUXC_GPR              IOMUXC_(0x008)
 126
 127 /* SW_MUX_CTL */
 128 #define SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD          IOMUXC_(0x00C)
 129 #define SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI              IOMUXC_(0x010)
 130 #define SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK                  IOMUXC_(0x014)
 131 #define SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0                IOMUXC_(0x018)
 132 #define SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0                     IOMUXC_(0x01C)
 133 #define SW_MUX_CTL_VSYNC3_CONTRAST_D3_REV_D3_CLS                        IOMUXC_(0x020)
 134 #define SW_MUX_CTL_SER_RS_PAR_RS_WRITE_READ                             IOMUXC_(0x024)
 135 #define SW_MUX_CTL_SD_D_IO_SD_D_CLK_LCS0_LCS1                           IOMUXC_(0x028)
 136 #define SW_MUX_CTL_HSYNC_FPSHIFT_DRDY0_SD_D_I                           IOMUXC_(0x02C)
 137 #define SW_MUX_CTL_LD15_LD16_LD17_VSYNC0                                IOMUXC_(0x030)
 138 #define SW_MUX_CTL_LD11_LD12_LD13_LD14                                  IOMUXC_(0x034)
 139 #define SW_MUX_CTL_LD7_LD8_LD9_LD10                                     IOMUXC_(0x038)
 140 #define SW_MUX_CTL_LD3_LD4_LD5_LD6                                      IOMUXC_(0x03C)
 141 #define SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2                              IOMUXC_(0x040)
 142 #define SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0            IOMUXC_(0x044)
 143 #define SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK     IOMUXC_(0x048)
 144 #define SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4  IOMUXC_(0x04C)
 145 #define SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0        IOMUXC_(0x050)
 146 #define SW_MUX_CTL_USB_PWR_USB_OC_USB_BYP_USBOTG_CLK                    IOMUXC_(0x054)
 147 #define SW_MUX_CTL_TDO_TRSTB_DE_B_SJC_MOD                               IOMUXC_(0x058)
 148 #define SW_MUX_CTL_RTCK_TCK_TMS_TDI                                     IOMUXC_(0x05C)
 149 #define SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7                  IOMUXC_(0x060)
 150 #define SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3                  IOMUXC_(0x064)
 151 #define SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7                  IOMUXC_(0x068)
 152 #define SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3                  IOMUXC_(0x06C)
 153 #define SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE                             IOMUXC_(0x070)
 154 #define SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2                       IOMUXC_(0x074)
 155 #define SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1                   IOMUXC_(0x078)
 156 #define SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1                          IOMUXC_(0x07C)
 157 #define SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1                   IOMUXC_(0x080)
 158 #define SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2             IOMUXC_(0x084)
 159 #define SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI        IOMUXC_(0x088)
 160 #define SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1            IOMUXC_(0x08C)
 161 #define SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6                                IOMUXC_(0x090)
 162 #define SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5                                IOMUXC_(0x094)
 163 #define SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4                                IOMUXC_(0x098)
 164 #define SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3                                IOMUXC_(0x09C)
 165 #define SW_MUX_CTL_CSI_HSYNC_CSI_PIXCLK_I2C_CLK_I2C_DAT                 IOMUXC_(0x0A0)
 166 #define SW_MUX_CTL_CSI_D14_CSI_D15_CSI_MCLK_CSI_VSYNC                   IOMUXC_(0x0A4)
 167 #define SW_MUX_CTL_CSI_D10_CSI_D11_CSI_D12_CSI_D13                      IOMUXC_(0x0A8)
 168 #define SW_MUX_CTL_CSI_D6_CSI_D7_CSI_D8_CSI_D9                          IOMUXC_(0x0AC)
 169 #define SW_MUX_CTL_M_REQUEST_M_GRANT_CSI_D4_CSI_D5                      IOMUXC_(0x0B0)
 170 #define SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE                         IOMUXC_(0x0B4)
 171 #define SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2                        IOMUXC_(0x0B8)
 172 #define SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON                 IOMUXC_(0x0BC)
 173 #define SW_MUX_CTL_D2_D1_D0_PC_CD1_B                                    IOMUXC_(0x0C0)
 174 #define SW_MUX_CTL_D6_D5_D4_D3                                          IOMUXC_(0x0C4)
 175 #define SW_MUX_CTL_D10_D9_D8_D7                                         IOMUXC_(0x0C8)
 176 #define SW_MUX_CTL_D14_D13_D12_D11                                      IOMUXC_(0x0CC)
 177 #define SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15                               IOMUXC_(0x0D0)
 178 #define SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE                            IOMUXC_(0x0D4)
 179 #define SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3                              IOMUXC_(0x0D8)
 180 #define SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B                          IOMUXC_(0x0DC)
 181 #define SW_MUX_CTL_RW_RAS_CAS_SDWE                                      IOMUXC_(0x0E0)
 182 #define SW_MUX_CTL_CS5_ECB_LBA_BCLK                                     IOMUXC_(0x0E4)
 183 #define SW_MUX_CTL_CS1_CS2_CS3_CS4                                      IOMUXC_(0x0E8)
 184 #define SW_MUX_CTL_EB0_EB1_OE_CS0                                       IOMUXC_(0x0EC)
 185 #define SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3                                  IOMUXC_(0x0F0)
 186 #define SW_MUX_CTL_SD28_SD29_SD30_SD31                                  IOMUXC_(0x0F4)
 187 #define SW_MUX_CTL_SD24_SD25_SD26_SD27                                  IOMUXC_(0x0F8)
 188 #define SW_MUX_CTL_SD20_SD21_SD22_SD23                                  IOMUXC_(0x0FC)
 189 #define SW_MUX_CTL_SD16_SD17_SD18_SD19                                  IOMUXC_(0x100)
 190 #define SW_MUX_CTL_SD12_SD13_SD14_SD15                                  IOMUXC_(0x104)
 191 #define SW_MUX_CTL_SD8_SD9_SD10_SD11                                    IOMUXC_(0x108)
 192 #define SW_MUX_CTL_SD4_SD5_SD6_SD7                                      IOMUXC_(0x10C)
 193 #define SW_MUX_CTL_SD0_SD1_SD2_SD3                                      IOMUXC_(0x110)
 194 #define SW_MUX_CTL_A24_A25_SDBA1_SDBA0                                  IOMUXC_(0x114)
 195 #define SW_MUX_CTL_A20_A21_A22_A23                                      IOMUXC_(0x118)
 196 #define SW_MUX_CTL_A16_A17_A18_A19                                      IOMUXC_(0x11C)
 197 #define SW_MUX_CTL_A12_A13_A14_A15                                      IOMUXC_(0x120)
 198 #define SW_MUX_CTL_A9_A10_MA10_A11                                      IOMUXC_(0x124)
 199 #define SW_MUX_CTL_A5_A6_A7_A8                                          IOMUXC_(0x128)
 200 #define SW_MUX_CTL_A1_A2_A3_A4                                          IOMUXC_(0x12C)
 201 #define SW_MUX_CTL_DVFS1_VPG0_VPG1_A0                                   IOMUXC_(0x130)
 202 #define SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0                          IOMUXC_(0x134)
 203 #define SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4          IOMUXC_(0x138)
 204 #define SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0                     IOMUXC_(0x13C)
 205 #define SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH                                IOMUXC_(0x140)
 206 #define SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0                            IOMUXC_(0x144)
 207 #define SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0                      IOMUXC_(0x148)
 208 #define SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3                      IOMUXC_(0x14C)
 209 #define SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO                    IOMUXC_(0x150)
 210
 211 #define SW_MUX_OUT              (0x7 << 4)
 212 #define SW_MUX_OUT_GPIO_DR      (0x0 << 4)
 213 #define SW_MUX_OUT_FUNCTIONAL   (0x1 << 4)
 214 #define SW_MUX_OUT_ALT1         (0x2 << 4)
 215 #define SW_MUX_OUT_ALT2         (0x3 << 4)
 216 #define SW_MUX_OUT_ALT3         (0x4 << 4)
 217 #define SW_MUX_OUT_ALT4         (0x5 << 4)
 218 #define SW_MUX_OUT_ALT5         (0x6 << 4)
 219 #define SW_MUX_OUT_ALT6         (0x7 << 4)
 220
 221 #define SW_MUX_IN               (0xf << 0)
 222 #define SW_MUX_IN_NO_INPUTS     (0x0 << 0)
 223 #define SW_MUX_IN_GPIO_PSR_ISR  (0x1 << 0)
 224 #define SW_MUX_IN_FUNCTIONAL    (0x2 << 0)
 225 #define SW_MUX_IN_ALT1          (0x4 << 0)
 226 #define SW_MUX_IN_ALT2          (0x8 << 0)
 227
 228 /* Masks for each signal field */
 229 #define SW_MUX_CTL_SIG1         (0x7f <<  0)
 230 #define SW_MUX_CTL_SIG2         (0x7f <<  8)
 231 #define SW_MUX_CTL_SIG3         (0x7f << 16)
 232 #define SW_MUX_CTL_SIG4         (0x7f << 24)
 233 /* Shift above flags into one of the four fields in each register */
 234 #define SW_MUX_CTL_SIG1w(x)     (((x) <<  0) & SW_MUX_CTL_SIG1)
 235 #define SW_MUX_CTL_SIG2w(x)     (((x) <<  8) & SW_MUX_CTL_SIG2)
 236 #define SW_MUX_CTL_SIG3w(x)     (((x) << 16) & SW_MUX_CTL_SIG3)
 237 #define SW_MUX_CTL_SIG4w(x)     (((x) << 24) & SW_MUX_CTL_SIG4)
 238
 239 /* SW_PAD_CTL */
 240 #define SW_PAD_CTL_TTM_PAD__X__X                            IOMUXC_(0x154)
 241 #define SW_PAD_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY      IOMUXC_(0x158)
 242 #define SW_PAD_CTL_CE_CONTROL_CLKSS_CSPI3_MOSI              IOMUXC_(0x15C)
 243 #define SW_PAD_CTL_ATA_DIOW_ATA_DMACK_ATA_RESET_B           IOMUXC_(0x160)
 244 #define SW_PAD_CTL_ATA_CS0_ATA_CS1_ATA_DIOR                 IOMUXC_(0x164)
 245 #define SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3            IOMUXC_(0x168)
 246 #define SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0                IOMUXC_(0x16C)
 247 #define SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL                     IOMUXC_(0x170)
 248 #define SW_PAD_CTL_READ_VSYNC3_CONTRAST                     IOMUXC_(0x174)
 249 #define SW_PAD_CTL_SER_RS_PAR_RS_WRITE                      IOMUXC_(0x178)
 250 #define SW_PAD_CTL_SD_D_CLK_LCS0_LCS1                       IOMUXC_(0x17C)
 251 #define SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO                     IOMUXC_(0x180)
 252 #define SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT                     IOMUXC_(0x184)
 253 #define SW_PAD_CTL_LD15_LD16_LD17                           IOMUXC_(0x188)
 254 #define SW_PAD_CTL_LD12_LD13_LD14                           IOMUXC_(0x18C)
 255 #define SW_PAD_CTL_LD9_LD10_LD11                            IOMUXC_(0x190)
 256 #define SW_PAD_CTL_LD6_LD7_LD8                              IOMUXC_(0x194)
 257 #define SW_PAD_CTL_LD3_LD4_LD5                              IOMUXC_(0x198)
 258 #define SW_PAD_CTL_LD0_LD1_LD2                              IOMUXC_(0x19C)
 259 #define SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1        IOMUXC_(0x1A0)
 260 #define SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP            IOMUXC_(0x1A4)
 261 #define SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7   IOMUXC_(0x1A8)
 262 #define SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4   IOMUXC_(0x1AC)
 263 #define SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1     IOMUXC_(0x1B0)
 264 #define SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP         IOMUXC_(0x1B4)
 265 #define SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP                   IOMUXC_(0x1B8)
 266 #define SW_PAD_CTL_TRSTB_DE_B_SJC_MOD                       IOMUXC_(0x1BC)
 267 #define SW_PAD_CTL_TMS_TDI_TDO                              IOMUXC_(0x1C0)
 268 #define SW_PAD_CTL_KEY_COL7_RTCK_TCK                        IOMUXC_(0x1C4)
 269 #define SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6               IOMUXC_(0x1C8)
 270 #define SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3               IOMUXC_(0x1CC)
 271 #define SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0               IOMUXC_(0x1D0)
 272 #define SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5               IOMUXC_(0x1D4)
 273 #define SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2               IOMUXC_(0x1D8)
 274 #define SW_PAD_CTL_RTS2_CTS2_BATT_LINE                      IOMUXC_(0x1DC)
 275 #define SW_PAD_CTL_DTR_DCE2_RXD2_TXD2                       IOMUXC_(0x1E0)
 276 #define SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1                IOMUXC_(0x1E4)
 277 #define SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1                IOMUXC_(0x1E8)
 278 #define SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1                   IOMUXC_(0x1EC)
 279 #define SW_PAD_CTL_RXD1_TXD1_RTS1                           IOMUXC_(0x1F0)
 280 #define SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY       IOMUXC_(0x1F4)
 281 #define SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1           IOMUXC_(0x1F8)
 282 #define SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI      IOMUXC_(0x1FC)
 283 #define SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS             IOMUXC_(0x200)
 284 #define SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO               IOMUXC_(0x204)
 285 #define SW_PAD_CTL_STXD6_SRXD6_SCK6                         IOMUXC_(0x208)
 286 #define SW_PAD_CTL_SRXD5_SCK5_SFS5                          IOMUXC_(0x20C)
 287 #define SW_PAD_CTL_SCK4_SFS4_STXD5                          IOMUXC_(0x210)
 288 #define SW_PAD_CTL_SFS3_STXD4_SRXD4                         IOMUXC_(0x214)
 289 #define SW_PAD_CTL_STXD3_SRXD3_SCK3                         IOMUXC_(0x218)
 290 #define SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT               IOMUXC_(0x21C)
 291 #define SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC             IOMUXC_(0x220)
 292 #define SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15                  IOMUXC_(0x224)
 293 #define SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12                  IOMUXC_(0x228)
 294 #define SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9                     IOMUXC_(0x22C)
 295 #define SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6                     IOMUXC_(0x230)
 296 #define SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT                 IOMUXC_(0x234)
 297 #define SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B                    IOMUXC_(0x238)
 298 #define SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2                   IOMUXC_(0x23C)
 299 #define SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1                 IOMUXC_(0x240)
 300 #define SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B              IOMUXC_(0x244)
 301 #define SW_PAD_CTL_D2_D1_D0                                 IOMUXC_(0x248)
 302 #define SW_PAD_CTL_D5_D4_D3                                 IOMUXC_(0x24C)
 303 #define SW_PAD_CTL_D8_D7_D6                                 IOMUXC_(0x250)
 304 #define SW_PAD_CTL_D11_D10_D9                               IOMUXC_(0x254)
 305 #define SW_PAD_CTL_D14_D13_D12                              IOMUXC_(0x258)
 306 #define SW_PAD_CTL_NFCE_B_NFRB_D15                          IOMUXC_(0x25C)
 307 #define SW_PAD_CTL_NFALE_NFCLE_NFWP_B                       IOMUXC_(0x260)
 308 #define SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B                      IOMUXC_(0x264)
 309 #define SW_PAD_CTL_SDQS0_SDQS1_SDQS2                        IOMUXC_(0x268)
 310 #define SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B                     IOMUXC_(0x26C)
 311 #define SW_PAD_CTL_CAS_SDWE_SDCKE0                          IOMUXC_(0x270)
 312 #define SW_PAD_CTL_BCLK_RW_RAS                              IOMUXC_(0x274)
 313 #define SW_PAD_CTL_CS5_ECB_LBA                              IOMUXC_(0x278)
 314 #define SW_PAD_CTL_CS2_CS3_CS4                              IOMUXC_(0x27C)
 315 #define SW_PAD_CTL_OE_CS0_CS1                               IOMUXC_(0x280)
 316 #define SW_PAD_CTL_DQM3_EB0_EB1                             IOMUXC_(0x284)
 317 #define SW_PAD_CTL_DQM0_DQM1_DQM2                           IOMUXC_(0x288)
 318 #define SW_PAD_CTL_SD29_SD30_SD31                           IOMUXC_(0x28C)
 319 #define SW_PAD_CTL_SD26_SD27_SD28                           IOMUXC_(0x290)
 320 #define SW_PAD_CTL_SD23_SD24_SD25                           IOMUXC_(0x294)
 321 #define SW_PAD_CTL_SD20_SD21_SD22                           IOMUXC_(0x298)
 322 #define SW_PAD_CTL_SD17_SD18_SD19                           IOMUXC_(0x29C)
 323 #define SW_PAD_CTL_SD14_SD15_SD16                           IOMUXC_(0x2A0)
 324 #define SW_PAD_CTL_SD11_SD12_SD13                           IOMUXC_(0x2A4)
 325 #define SW_PAD_CTL_SD8_SD9_SD10                             IOMUXC_(0x2A8)
 326 #define SW_PAD_CTL_SD5_SD6_SD7                              IOMUXC_(0x2AC)
 327 #define SW_PAD_CTL_SD2_SD3_SD4                              IOMUXC_(0x2B0)
 328 #define SW_PAD_CTL_SDBA0_SD0_SD1                            IOMUXC_(0x2B4)
 329 #define SW_PAD_CTL_A24_A25_SDBA1                            IOMUXC_(0x2B8)
 330 #define SW_PAD_CTL_A21_A22_A23                              IOMUXC_(0x2BC)
 331 #define SW_PAD_CTL_A18_A19_A20                              IOMUXC_(0x2C0)
 332 #define SW_PAD_CTL_A15_A16_A17                              IOMUXC_(0x2C4)
 333 #define SW_PAD_CTL_A12_A13_A14                              IOMUXC_(0x2C8)
 334 #define SW_PAD_CTL_A10_MA10_A11                             IOMUXC_(0x2CC)
 335 #define SW_PAD_CTL_A7_A8_A9                                 IOMUXC_(0x2D0)
 336 #define SW_PAD_CTL_A4_A5_A6                                 IOMUXC_(0x2D4)
 337 #define SW_PAD_CTL_A1_A2_A3                                 IOMUXC_(0x2D8)
 338 #define SW_PAD_CTL_VPG0_VPG1_A0                             IOMUXC_(0x2DC)
 339 #define SW_PAD_CTL_VSTBY_DVFS0_DVFS1                        IOMUXC_(0x2E0)
 340 #define SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL               IOMUXC_(0x2E4)
 341 #define SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3         IOMUXC_(0x2E8)
 342 #define SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0                    IOMUXC_(0x2EC)
 343 #define SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B                   IOMUXC_(0x2F0)
 344 #define SW_PAD_CTL_SVEN0_STX0_SRX0                          IOMUXC_(0x2F4)
 345 #define SW_PAD_CTL_GPIO3_1_SCLK0_SRST0                      IOMUXC_(0x2F8)
 346 #define SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0                  IOMUXC_(0x2FC)
 347 #define SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4                  IOMUXC_(0x300)
 348 #define SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1                     IOMUXC_(0x304)
 349 #define SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST             IOMUXC_(0x308)
 350
 351 /* SW_PAD_CTL flags */
 352 #define SW_PAD_CTL_LOOPBACK             (0x1 << 9) /* Route output to input */
 353 /* Pullup, pulldown and keeper enable */
 354 #define SW_PAD_CTL_PUE_PKE              (0x3 << 7)
 355 #define SW_PAD_CTL_PUE_PKE_DISABLE      (0x0 << 7)
 356 #define SW_PAD_CTL_PUE_PKE_DISABLE_2    (0x1 << 7) /* Same as 0x0 */
 357 #define SW_PAD_CTL_PUE_PKE_KEEPER       (0x2 << 7)
 358 #define SW_PAD_CTL_PUE_PKE_PULLUPDOWN   (0x3 << 7) /* Enb. Pull up or down */
 359 /* Pullup/down resistance */
 360 #define SW_PAD_CTL_PUS                  (0x3 << 5)
 361 #define SW_PAD_CTL_PUS_DOWN_100K        (0x0 << 5)
 362 #define SW_PAD_CTL_PUS_UP_100K          (0x1 << 5)
 363 #if 0 /* Completeness */
 364 #define SW_PAD_CTL_PUS_UP_47K           (0x2 << 5) /* Not in IMX31/L */
 365 #define SW_PAD_CTL_PUS_UP_22K           (0x3 << 5) /* Not in IMX31/L */
 366 #endif
 367 #define SW_PAD_CTL_HYS                  (0x1 << 4) /* Schmitt trigger input */
 368 #define SW_PAD_CTL_ODE                  (0x1 << 3) /* Open drain output 0=CMOS pushpull*/
 369 #define SW_PAD_CTL_DSE                  (0x3 << 1)
 370 #define SW_PAD_CTL_DSE_STD              (0x0 << 1) /* Drive strength */
 371 #define SW_PAD_CTL_DSE_HIGH             (0x1 << 1)
 372 #define SW_PAD_CTL_DSE_MAX              (0x2 << 1)
 373 #define SW_PAD_CTL_DSE_MAX_2            (0x3 << 1) /* Same as 0x2 */
 374 #define SW_PAD_CTL_SRE                  (0x1 << 0) /* Slew rate, 1=fast */
 375
 376 /* Masks for each IO field */
 377 #define SW_PAD_CTL_IO1                  (0x3ff << 0)
 378 #define SW_PAD_CTL_IO2                  (0x3ff << 10)
 379 #define SW_PAD_CTL_IO3                  (0x3ff << 20)
 380
 381 /* Shift above flags into one of the three fields in each register */
 382 #define SW_PAD_CTL_IO1w(x)              (((x) <<  0) & SW_PAD_CTL_IO1)
 383 #define SW_PAD_CTL_IO2w(x)              (((x) << 10) & SW_PAD_CTL_IO2)
 384 #define SW_PAD_CTL_IO3w(x)              (((x) << 20) & SW_PAD_CTL_IO3)
 385
 386 /* RNGA */
 387 #define RNGA_CONTROL            (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00))
 388
 389 #define RNGA_CONTROL_SLEEP                          (1 << 4)
 390
 391 /* IPU */
 392 #define IPU_CONF                (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00))
 393 #define IPU_CHA_BUF0_RDY        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04))
 394 #define IPU_CHA_BUF1_RDY        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08))
 395 #define IPU_CHA_DB_MODE_SEL     (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C))
 396 #define IPU_CHA_CUR_BUF         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10))
 397 #define IPU_FS_PROC_FLOW        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14))
 398 #define IPU_FS_DISP_FLOW        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18))
 399 #define IPU_TASKS_STAT          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1C))
 400 #define IPU_IMA_ADDR            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x20))
 401 #define IPU_IMA_DATA            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x24))
 402 #define IPU_INT_CTRL_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x28))
 403 #define IPU_INT_CTRL_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x2C))
 404 #define IPU_INT_CTRL_3          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x30))
 405 #define IPU_INT_CTRL_4          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x34))
 406 #define IPU_INT_CTRL_5          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x38))
 407 #define IPU_INT_STAT_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x3C))
 408 #define IPU_INT_STAT_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x40))
 409 #define IPU_INT_STAT_3          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x44))
 410 #define IPU_INT_STAT_4          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x48))
 411 #define IPU_INT_STAT_5          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x4C))
 412 #define IPU_BRK_CTRL_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x50))
 413 #define IPU_BRK_CTRL_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54))
 414 #define IPU_BRK_STAT            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58))
 415 #define IPU_DIAGB_CTRL          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60))
 416 #define IPU_IDMAC_CONF          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA4))
 417 #define IPU_IDMAC_CHA_EN        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA8))
 418 #define IPU_IDMAC_CHA_PRI       (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xAC))
 419 #define IPU_IDMAC_CHA_BUSY      (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xB0))
 420
 421
 422
 423 /* ATA */
 424 #define ATA_TIME_OFF            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00))
 425 #define ATA_TIME_ON             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x01))
 426 #define ATA_TIME_1              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x02))
 427 #define ATA_TIME_2W             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x03))
 428     /* PIO */
 429 #define ATA_TIME_2R             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x04))
 430 #define ATA_TIME_AX             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x05))
 431 #define ATA_TIME_4              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x07))
 432 #define ATA_TIME_9              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x08))
 433     /* MDMA */
 434 #define ATA_TIME_M              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x09))
 435 #define ATA_TIME_JN             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0A))
 436 #define ATA_TIME_D              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0B))
 437 #define ATA_TIME_K              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0C))
 438     /* UDMA */
 439 #define ATA_TIME_ACK            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0D))
 440 #define ATA_TIME_ENV            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0E))
 441 #define ATA_TIME_PIO_RDX        (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0F))
 442 #define ATA_TIME_ZAH            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x10))
 443 #define ATA_TIME_MLIX           (*(REG8_PTR_T)(ATA_BASE_ADDR+0x11))
 444 #define ATA_TIME_DVH            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x12))
 445 #define ATA_TIME_DZFS           (*(REG8_PTR_T)(ATA_BASE_ADDR+0x13))
 446 #define ATA_TIME_DVS            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x14))
 447 #define ATA_TIME_CVS            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x15))
 448 #define ATA_TIME_SS             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x16))
 449 #define ATA_TIME_CYC            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x17))
 450     /* */
 451 #define ATA_FIFO_DATA_32        (*(REG32_PTR_T)(ATA_BASE_ADDR+0x18))
 452 #define ATA_FIFO_DATA_16        (*(REG16_PTR_T)(ATA_BASE_ADDR+0x1c))
 453 #define ATA_FIFO_FILL           (*(REG8_PTR_T)(ATA_BASE_ADDR+0x20))
 454     /* Actually ATA_CONTROL but conflicts arise */
 455 #define ATA_INTF_CONTROL        (*(REG8_PTR_T)(ATA_BASE_ADDR+0x24))
 456 #define ATA_INTERRUPT_PENDING   (*(REG8_PTR_T)(ATA_BASE_ADDR+0x28))
 457 #define ATA_INTERRUPT_ENABLE    (*(REG8_PTR_T)(ATA_BASE_ADDR+0x2c))
 458 #define ATA_INTERRUPT_CLEAR     (*(REG8_PTR_T)(ATA_BASE_ADDR+0x30))
 459 #define ATA_FIFO_ALARM          (*(REG8_PTR_T)(ATA_BASE_ADDR+0x34))
 460 #define ATA_DRIVE_DATA          (*(REG16_PTR_T)(ATA_BASE_ADDR+0xA0))
 461 #define ATA_DRIVE_FEATURES      (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA4))
 462 #define ATA_DRIVE_SECTOR_COUNT  (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA8))
 463 #define ATA_DRIVE_SECTOR_NUM    (*(REG8_PTR_T)(ATA_BASE_ADDR+0xAC))
 464 #define ATA_DRIVE_CYL_LOW       (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB0))
 465 #define ATA_DRIVE_CYL_HIGH      (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB4))
 466 #define ATA_DRIVE_CYL_HEAD      (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB8))
 467 #define ATA_DRIVE_STATUS        (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* rd */
 468 #define ATA_DRIVE_COMMAND       (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* wr */
 469 #define ATA_ALT_DRIVE_STATUS    (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* rd */
 470 #define ATA_DRIVE_CONTROL       (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* wr */
 471
 472 /* ATA_INTF_CONTROL flags */
 473 #define ATA_FIFO_RST            (1 << 7)
 474 #define ATA_ATA_RST             (1 << 6)
 475 #define ATA_FIFO_TX_EN          (1 << 5)
 476 #define ATA_FIFO_RCV_EN         (1 << 4)
 477 #define ATA_DMA_PENDING         (1 << 3)
 478 #define ATA_DMA_ULTRA_SELECTED  (1 << 2)
 479 #define ATA_DMA_WRITE           (1 << 1)
 480 #define ATA_IORDY_EN            (1 << 0)
 481
 482 /* ATA_INTERRUPT_PENDING, ATA_INTERRUPT_ENABLE, ATA_INTERRUPT_CLEAR flags */
 483 #define ATA_INTRQ1              (1 << 7)
 484 #define ATA_FIFO_UNDERFLOW      (1 << 6)
 485 #define ATA_FIFO_OVERFLOW       (1 << 5)
 486 #define ATA_CONTROLLER_IDLE     (1 << 4)
 487 #define ATA_INTRQ2              (1 << 3)
 488
 489 /* EPIT */
 490 #define EPITCR1                 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00))
 491 #define EPITSR1                 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x04))
 492 #define EPITLR1                 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x08))
 493 #define EPITCMPR1               (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x0C))
 494 #define EPITCNT1                (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x10))
 495
 496 #define EPITCR2                 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x00))
 497 #define EPITSR2                 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x04))
 498 #define EPITLR2                 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x08))
 499 #define EPITCMPR2               (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x0C))
 500 #define EPITCNT2                (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x10))
 501
 502 #define EPITCR_CLKSRC_OFF               (0 << 24)
 503 #define EPITCR_CLKSRC_IPG_CLK           (1 << 24)
 504 #define EPITCR_CLKSRC_IPG_CLK_HIGHFREQ  (2 << 24)
 505 #define EPITCR_CLKSRC_IPG_CLK_32K       (3 << 24)
 506 #define EPITCR_OM_DISCONNECTED          (0 << 22)
 507 #define EPITCR_OM_TOGGLE                (1 << 22)
 508 #define EPITCR_OM_CLEAR                 (2 << 22)
 509 #define EPITCR_OM_SET                   (3 << 22)
 510 #define EPITCR_STOPEN                   (1 << 21)
 511 #define EPITCR_DOZEN                    (1 << 20)
 512 #define EPITCR_WAITEN                   (1 << 19)
 513 #define EPITCR_DBGEN                    (1 << 18)
 514 #define EPITCR_IOVW                     (1 << 17)
 515 #define EPITCR_SWR                      (1 << 16)
 516 #define EPITCR_PRESCALER(n)             ((n) << 4) /* Divide by n+1 */
 517 #define EPITCR_RLD                      (1 << 3)
 518 #define EPITCR_OCIEN                    (1 << 2)
 519 #define EPITCR_ENMOD                    (1 << 1)
 520 #define EPITCR_EN                       (1 << 0)
 521
 522 #define EPITSR_OCIF                     (1 << 0)
 523
 524 /* GPT */
 525 #define GPTCR                   (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x00))
 526 #define GPTPR                   (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x04))
 527 #define GPTSR                   (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x08))
 528 #define GPTIR                   (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x0C))
 529 #define GPTOCR1                 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x10))
 530 #define GPTOCR2                 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x14))
 531 #define GPTOCR3                 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x18))
 532 #define GPTICR1                 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x1C))
 533 #define GPTICR2                 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x20))
 534 #define GPTCNT                  (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x24))
 535
 536 /* GPTCR */
 537 #define GPTCR_FO3               (0x1 << 31)
 538 #define GPTCR_FO2               (0x1 << 30)
 539 #define GPTCR_FO1               (0x1 << 29)
 540
 541 #define GPTCR_OM3               (0x7 << 26)
 542 #define GPTCR_OM3_DISCONNECTED  (0x0 << 26)
 543 #define GPTCR_OM3_TOGGLE        (0x1 << 26)
 544 #define GPTCR_OM3_CLEAR         (0x2 << 26)
 545 #define GPTCR_OM3_SET           (0x3 << 26)
 546 #define GPTCR_OM3_SINGLE_COUNT  (0x4 << 26)
 547     /* 0x5-0x7 same as 0x4 */
 548
 549 #define GPTCR_OM2               (0x7 << 23)
 550 #define GPTCR_OM2_DISCONNECTED  (0x0 << 23)
 551 #define GPTCR_OM2_TOGGLE        (0x1 << 23)
 552 #define GPTCR_OM2_CLEAR         (0x2 << 23)
 553 #define GPTCR_OM2_SET           (0x3 << 23)
 554 #define GPTCR_OM2_SINGLE_COUNT  (0x4 << 23)
 555
 556     /* 0x5-0x7 same as 0x4 */
 557 #define GPTCR_OM1               (0x7 << 20)
 558 #define GPTCR_OM1_DISCONNECTED  (0x0 << 20)
 559 #define GPTCR_OM1_TOGGLE        (0x1 << 20)
 560 #define GPTCR_OM1_CLEAR         (0x2 << 20)
 561 #define GPTCR_OM1_SET           (0x3 << 20)
 562 #define GPTCR_OM1_SINGLE_COUNT  (0x4 << 20)
 563
 564     /* 0x5-0x7 same as 0x4 */
 565 #define GPTCR_IM2               (0x3 << 18)
 566 #define GPTCR_IM2_DISABLED      (0x0 << 18)
 567 #define GPTCR_IM2_RISING        (0x1 << 18)
 568 #define GPTCR_IM2_FALLING       (0x2 << 18)
 569 #define GPTCR_IM2_BOTH          (0x3 << 18)
 570
 571 #define GPTCR_IM1               (0x3 << 16)
 572 #define GPTCR_IM1_DISABLED      (0x0 << 16)
 573 #define GPTCR_IM1_RISING        (0x1 << 16)
 574 #define GPTCR_IM1_FALLING       (0x2 << 16)
 575 #define GPTCR_IM1_BOTH          (0x3 << 16)
 576
 577 #define GPTCR_SWR               (0x1 << 15)
 578 #define GPTCR_FRR               (0x1 << 9)
 579
 580 #define GPTCR_CLKSRC            (0x7 << 6)
 581 #define GPTCR_CLKSRC_NONE               (0x0 << 6)
 582 #define GPTCR_CLKSRC_IPG_CLK            (0x1 << 6)
 583 #define GPTCR_CLKSRC_IPG_CLK_HIGHFREQ   (0x2 << 6)
 584 #define GPTCR_CLKSRC_IPG_CLK_32K        (0x4 << 6)
 585 /* Other values not defined */
 586
 587 #define GPTCR_STOPEN            (0x1 << 5)
 588 #define GPTCR_DOZEN             (0x1 << 4)
 589 #define GPTCR_WAITEN            (0x1 << 3)
 590 #define GPTCR_DBGEN             (0x1 << 2)
 591 #define GPTCR_ENMODE            (0x1 << 1)
 592 #define GPTCR_EN                (0x1 << 0)
 593
 594 /* GPTSR */
 595 #define GPTSR_ROV               (0x1 << 5)
 596 #define GPTSR_IF2               (0x1 << 4)
 597 #define GPTSR_IF1               (0x1 << 3)
 598 #define GPTSR_OF3               (0x1 << 2)
 599 #define GPTSR_OF2               (0x1 << 1)
 600 #define GPTSR_OF1               (0x1 << 0)
 601
 602 /* GPTIR */
 603 #define GPTIR_ROV               (0x1 << 5)
 604 #define GPTIR_IF2IE             (0x1 << 4)
 605 #define GPTIR_IF1IE             (0x1 << 3)
 606 #define GPTIR_OF3IE             (0x1 << 2)
 607 #define GPTIR_OF2IE             (0x1 << 1)
 608 #define GPTIR_OF1IE             (0x1 << 0)
 609
 610 /* GPIO */
 611 #define GPIO1_DR                (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00))
 612 #define GPIO1_GDIR              (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04))
 613 #define GPIO1_PSR               (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x08))
 614 #define GPIO1_ICR1              (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x0C))
 615 #define GPIO1_ICR2              (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x10))
 616 #define GPIO1_IMR               (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x14))
 617 #define GPIO1_ISR               (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x18))
 618
 619 #define GPIO2_DR                (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x00))
 620 #define GPIO2_GDIR              (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x04))
 621 #define GPIO2_PSR               (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x08))
 622 #define GPIO2_ICR1              (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x0C))
 623 #define GPIO2_ICR2              (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x10))
 624 #define GPIO2_IMR               (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x14))
 625 #define GPIO2_ISR               (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x18))
 626
 627 #define GPIO3_DR                (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x00))
 628 #define GPIO3_GDIR              (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x04))
 629 #define GPIO3_PSR               (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x08))
 630 #define GPIO3_ICR1              (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x0C))
 631 #define GPIO3_ICR2              (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x10))
 632 #define GPIO3_IMR               (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14))
 633 #define GPIO3_ISR               (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18))
 634
 635 /* CSPI */
 636 #define CSPI_RXDATA1            (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00))
 637 #define CSPI_TXDATA1            (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04))
 638 #define CSPI_CONREG1            (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08))
 639 #define CSPI_INTREG1            (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x0C))
 640 #define CSPI_DMAREG1            (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x10))
 641 #define CSPI_STATREG1           (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x14))
 642 #define CSPI_PERIODREG1         (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x18))
 643 #define CSPI_TESTREG1           (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x1C0))
 644
 645 #define CSPI_RXDATA2            (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x00))
 646 #define CSPI_TXDATA2            (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x04))
 647 #define CSPI_CONREG2            (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x08))
 648 #define CSPI_INTREG2            (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x0C))
 649 #define CSPI_DMAREG2            (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x10))
 650 #define CSPI_STATREG2           (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x14))
 651 #define CSPI_PERIODREG2         (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18))
 652 #define CSPI_TESTREG2           (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0))
 653
 654 #define CSPI_RXDATA3            (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x00))
 655 #define CSPI_TXDATA3            (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x04))
 656 #define CSPI_CONREG3            (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x08))
 657 #define CSPI_INTREG3            (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x0C))
 658 #define CSPI_DMAREG3            (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x10))
 659 #define CSPI_STATREG3           (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x14))
 660 #define CSPI_PERIODREG3         (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x18))
 661 #define CSPI_TESTREG3           (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x1C0))
 662
 663 /* CSPI CONREG flags/fields */
 664 #define CSPI_CONREG_CHIP_SELECT_SS0     (0 << 24)
 665 #define CSPI_CONREG_CHIP_SELECT_SS1     (1 << 24)
 666 #define CSPI_CONREG_CHIP_SELECT_SS2     (2 << 24)
 667 #define CSPI_CONREG_CHIP_SELECT_SS3     (3 << 24)
 668 #define CSPI_CONREG_CHIP_SELECT_MASK    (3 << 24)
 669 #define CSPI_CONREG_DRCTL_DONT_CARE     (0 << 20)
 670 #define CSPI_CONREG_DRCTL_TRIG_FALLING  (1 << 20)
 671 #define CSPI_CONREG_DRCTL_TRIG_LOW      (2 << 20)
 672 #define CSPI_CONREG_DRCTL_TRIG_RSV      (3 << 20)
 673 #define CSPI_CONREG_DRCTL_MASK          (3 << 20)
 674 #define CSPI_CONREG_DATA_RATE_DIV_4     (0 << 16)
 675 #define CSPI_CONREG_DATA_RATE_DIV_8     (1 << 16)
 676 #define CSPI_CONREG_DATA_RATE_DIV_16    (2 << 16)
 677 #define CSPI_CONREG_DATA_RATE_DIV_32    (3 << 16)
 678 #define CSPI_CONREG_DATA_RATE_DIV_64    (4 << 16)
 679 #define CSPI_CONREG_DATA_RATE_DIV_128   (5 << 16)
 680 #define CSPI_CONREG_DATA_RATE_DIV_256   (6 << 16)
 681 #define CSPI_CONREG_DATA_RATE_DIV_512   (7 << 16)
 682 #define CSPI_CONREG_DATA_RATE_DIV_MASK  (7 << 16)
 683 #define CSPI_BITCOUNT(n)                ((n) << 8)
 684 #define CSPI_CONREG_SSPOL               (1 << 7)
 685 #define CSPI_CONREG_SSCTL               (1 << 6)
 686 #define CSPI_CONREG_PHA                 (1 << 6)
 687 #define CSPI_CONREG_POL                 (1 << 4)
 688 #define CSPI_CONREG_SMC                 (1 << 3)
 689 #define CSPI_CONREG_XCH                 (1 << 2)
 690 #define CSPI_CONREG_MODE                (1 << 1)
 691 #define CSPI_CONREG_EN                  (1 << 0)
 692
 693 /* CSPI INTREG flags */
 694 #define CSPI_INTREG_TCEN                (1 << 8)
 695 #define CSPI_INTREG_BOEN                (1 << 7)
 696 #define CSPI_INTREG_ROEN                (1 << 6)
 697 #define CSPI_INTREG_RFEN                (1 << 5)
 698 #define CSPI_INTREG_RHEN                (1 << 4)
 699 #define CSPI_INTREG_RREN                (1 << 3)
 700 #define CSPI_INTREG_TFEN                (1 << 2)
 701 #define CSPI_INTREG_THEN                (1 << 1)
 702 #define CSPI_INTREG_TEEN                (1 << 0)
 703
 704 /* CSPI DMAREG flags */
 705 #define CSPI_DMAREG_RFDEN               (1 << 5)
 706 #define CSPI_DMAREG_RHDEN               (1 << 4)
 707 #define CSPI_DMAREG_THDEN               (1 << 1)
 708 #define CSPI_DMAREG_TEDEN               (1 << 0)
 709
 710 /* CSPI STATREG flags */
 711 #define CSPI_STATREG_TC                 (1 << 8) /* w1c */
 712 #define CSPI_STATREG_BO                 (1 << 7) /* w1c */
 713 #define CSPI_STATREG_RO                 (1 << 6)
 714 #define CSPI_STATREG_RF                 (1 << 5)
 715 #define CSPI_STATREG_RH                 (1 << 4)
 716 #define CSPI_STATREG_RR                 (1 << 3)
 717 #define CSPI_STATREG_TF                 (1 << 2)
 718 #define CSPI_STATREG_TH                 (1 << 1)
 719 #define CSPI_STATREG_TE                 (1 << 0)
 720
 721 /* CSPI PERIODREG flags */
 722 #define CSPI_PERIODREG_CSRC             (1 << 15)
 723
 724 /* CSPI TESTREG flags */
 725 #define CSPI_TESTREG_SWAP               (1 << 15)
 726 #define CSPI_TESTREG_LBC                (1 << 14)
 727
 728 /* I2C */
 729 #define I2C_IADR1               (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x0))
 730 #define I2C_IFDR1               (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x4))
 731 #define I2C_I2CR1               (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x8))
 732 #define I2C_I2SR1               (*(REG16_PTR_T)(I2C1_BASE_ADDR+0xC))
 733 #define I2C_I2DR1               (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x10))
 734
 735 #define I2C_IADR2               (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x0))
 736 #define I2C_IFDR2               (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x4))
 737 #define I2C_I2CR2               (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x8))
 738 #define I2C_I2SR2               (*(REG16_PTR_T)(I2C2_BASE_ADDR+0xC))
 739 #define I2C_I2DR2               (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x10))
 740
 741 #define I2C_IADR3               (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x0))
 742 #define I2C_IFDR3               (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x4))
 743 #define I2C_I2CR3               (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x8))
 744 #define I2C_I2SR3               (*(REG16_PTR_T)(I2C3_BASE_ADDR+0xC))
 745 #define I2C_I2DR3               (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x10))
 746
 747     /* IADR - [7:1] Address */
 748
 749     /* IFDR */
 750 #define I2C_IFDR_DIV30           0x00
 751 #define I2C_IFDR_DIV32           0x01
 752 #define I2C_IFDR_DIV36           0x02
 753 #define I2C_IFDR_DIV42           0x03
 754 #define I2C_IFDR_DIV48           0x04
 755 #define I2C_IFDR_DIV52           0x05
 756 #define I2C_IFDR_DIV60           0x06
 757 #define I2C_IFDR_DIV72           0x07
 758 #define I2C_IFDR_DIV80           0x08
 759 #define I2C_IFDR_DIV88           0x09
 760 #define I2C_IFDR_DIV104          0x0a
 761 #define I2C_IFDR_DIV128          0x0b
 762 #define I2C_IFDR_DIV144          0x0c
 763 #define I2C_IFDR_DIV160          0x0d
 764 #define I2C_IFDR_DIV192          0x0e
 765 #define I2C_IFDR_DIV240          0x0f
 766 #define I2C_IFDR_DIV288          0x10
 767 #define I2C_IFDR_DIV320          0x11
 768 #define I2C_IFDR_DIV384          0x12
 769 #define I2C_IFDR_DIV480          0x13
 770 #define I2C_IFDR_DIV576          0x14
 771 #define I2C_IFDR_DIV640          0x15
 772 #define I2C_IFDR_DIV768          0x16
 773 #define I2C_IFDR_DIV960          0x17
 774 #define I2C_IFDR_DIV1152         0x18
 775 #define I2C_IFDR_DIV1280         0x19
 776 #define I2C_IFDR_DIV1536         0x1a
 777 #define I2C_IFDR_DIV1920         0x1b
 778 #define I2C_IFDR_DIV2304         0x1c
 779 #define I2C_IFDR_DIV2560         0x1d
 780 #define I2C_IFDR_DIV3072         0x1e
 781 #define I2C_IFDR_DIV3840         0x1f
 782 #define I2C_IFDR_DIV22           0x20
 783 #define I2C_IFDR_DIV24           0x21
 784 #define I2C_IFDR_DIV26           0x22
 785 #define I2C_IFDR_DIV28           0x23
 786 #define I2C_IFDR_DIV32_2         0x24
 787 #define I2C_IFDR_DIV36_2         0x25
 788 #define I2C_IFDR_DIV40           0x26
 789 #define I2C_IFDR_DIV44           0x27
 790 #define I2C_IFDR_DIV48_2         0x28
 791 #define I2C_IFDR_DIV56           0x29
 792 #define I2C_IFDR_DIV64           0x2a
 793 #define I2C_IFDR_DIV72_2         0x2b
 794 #define I2C_IFDR_DIV80_2         0x2c
 795 #define I2C_IFDR_DIV96           0x2d
 796 #define I2C_IFDR_DIV112          0x2e
 797 #define I2C_IFDR_DIV128_2        0x2f
 798 #define I2C_IFDR_DIV160_2        0x30
 799 #define I2C_IFDR_DIV192_2        0x31
 800 #define I2C_IFDR_DIV224          0x32
 801 #define I2C_IFDR_DIV256          0x33
 802 #define I2C_IFDR_DIV320_2        0x34
 803 #define I2C_IFDR_DIV384_2        0x35
 804 #define I2C_IFDR_DIV448          0x36
 805 #define I2C_IFDR_DIV512          0x37
 806 #define I2C_IFDR_DIV640_2        0x38
 807 #define I2C_IFDR_DIV768_2        0x39
 808 #define I2C_IFDR_DIV896          0x3a
 809 #define I2C_IFDR_DIV1024         0x3b
 810 #define I2C_IFDR_DIV1280_2       0x3c
 811 #define I2C_IFDR_DIV1536_2       0x3d
 812 #define I2C_IFDR_DIV1792         0x3e
 813 #define I2C_IFDR_DIV2048         0x3f
 814
 815     /* I2CR */
 816 #define I2C_I2CR_IEN            (1 << 7)
 817 #define I2C_I2CR_IIEN           (1 << 6)
 818 #define I2C_I2CR_MSTA           (1 << 5)
 819 #define I2C_I2CR_MTX            (1 << 4)
 820 #define I2C_I2CR_TXAK           (1 << 3)
 821 #define I2C_I2CR_RSATA          (1 << 2)
 822
 823     /* I2SR */
 824 #define I2C_I2SR_ICF            (1 << 7)
 825 #define I2C_I2SR_IAAS           (1 << 6)
 826 #define I2C_I2SR_IBB            (1 << 5)
 827 #define I2C_I2SR_IAL            (1 << 4)
 828 #define I2C_I2SR_SRW            (1 << 2)
 829 #define I2C_I2SR_IIF            (1 << 1)
 830 #define I2C_I2SR_RXAK           (1 << 0)
 831
 832     /* I2DR - [7:0] Data */
 833
 834 /* AUDMUX */
 835 #define AUDMUX_PTCR1            (*(REG32_PTR_T)(AUDMUX_BASE+0x00))
 836 #define AUDMUX_PDCR1            (*(REG32_PTR_T)(AUDMUX_BASE+0x04))
 837 #define AUDMUX_PTCR2            (*(REG32_PTR_T)(AUDMUX_BASE+0x08))
 838 #define AUDMUX_PDCR2            (*(REG32_PTR_T)(AUDMUX_BASE+0x0C))
 839 #define AUDMUX_PTCR3            (*(REG32_PTR_T)(AUDMUX_BASE+0x10))
 840 #define AUDMUX_PDCR3            (*(REG32_PTR_T)(AUDMUX_BASE+0x14))
 841 #define AUDMUX_PTCR4            (*(REG32_PTR_T)(AUDMUX_BASE+0x18))
 842 #define AUDMUX_PDCR4            (*(REG32_PTR_T)(AUDMUX_BASE+0x1C))
 843 #define AUDMUX_PTCR5            (*(REG32_PTR_T)(AUDMUX_BASE+0x20))
 844 #define AUDMUX_PDCR5            (*(REG32_PTR_T)(AUDMUX_BASE+0x24))
 845 #define AUDMUX_PTCR6            (*(REG32_PTR_T)(AUDMUX_BASE+0x28))
 846 #define AUDMUX_PDCR6            (*(REG32_PTR_T)(AUDMUX_BASE+0x2C))
 847 #define AUDMUX_PTCR7            (*(REG32_PTR_T)(AUDMUX_BASE+0x30))
 848 #define AUDMUX_PDCR7            (*(REG32_PTR_T)(AUDMUX_BASE+0x34))
 849 #define AUDMUX_CNMCR            (*(REG32_PTR_T)(AUDMUX_BASE+0x38))
 850
 851 #define AUDMUX_PTCR_TFS_DIR         (1 << 31)
 852
 853 #define AUDMUX_PTCR_TFSEL           (0xf << 27)
 854 #define AUDMUX_PTCR_TFSEL_TXFS      (0x0 << 27)
 855 #define AUDMUX_PTCR_TFSEL_RXFS      (0x8 << 27)
 856 #define AUDMUX_PTCR_TFSEL_PORT1     (0x0 << 27)
 857 #define AUDMUX_PTCR_TFSEL_PORT2     (0x1 << 27)
 858 #define AUDMUX_PTCR_TFSEL_PORT3     (0x2 << 27)
 859 #define AUDMUX_PTCR_TFSEL_PORT4     (0x3 << 27)
 860 #define AUDMUX_PTCR_TFSEL_PORT5     (0x4 << 27)
 861 #define AUDMUX_PTCR_TFSEL_PORT6     (0x5 << 27)
 862 #define AUDMUX_PTCR_TFSEL_PORT7     (0x6 << 27)
 863
 864 #define AUDMUX_PTCR_TCLKDIR         (1 << 26)
 865
 866 #define AUDMUX_PTCR_TCSEL           (0xf << 22)
 867 #define AUDMUX_PTCR_TCSEL_TXFS      (0x0 << 22)
 868 #define AUDMUX_PTCR_TCSEL_RXFS      (0x8 << 22)
 869 #define AUDMUX_PTCR_TCSEL_PORT1     (0x0 << 22)
 870 #define AUDMUX_PTCR_TCSEL_PORT2     (0x1 << 22)
 871 #define AUDMUX_PTCR_TCSEL_PORT3     (0x2 << 22)
 872 #define AUDMUX_PTCR_TCSEL_PORT4     (0x3 << 22)
 873 #define AUDMUX_PTCR_TCSEL_PORT5     (0x4 << 22)
 874 #define AUDMUX_PTCR_TCSEL_PORT6     (0x5 << 22)
 875 #define AUDMUX_PTCR_TCSEL_PORT7     (0x6 << 22)
 876
 877 #define AUDMUX_PTCR_RFS_DIR         (1 << 21)
 878
 879 #define AUDMUX_PTCR_RFSSEL          (0xf << 17)
 880 #define AUDMUX_PTCR_RFSSEL_TXFS     (0x0 << 17)
 881 #define AUDMUX_PTCR_RFSSEL_RXFS     (0x8 << 17)
 882 #define AUDMUX_PTCR_RFSSEL_PORT1    (0x0 << 17)
 883 #define AUDMUX_PTCR_RFSSEL_PORT2    (0x1 << 17)
 884 #define AUDMUX_PTCR_RFSSEL_PORT3    (0x2 << 17)
 885 #define AUDMUX_PTCR_RFSSEL_PORT4    (0x3 << 17)
 886 #define AUDMUX_PTCR_RFSSEL_PORT5    (0x4 << 17)
 887 #define AUDMUX_PTCR_RFSSEL_PORT6    (0x5 << 17)
 888 #define AUDMUX_PTCR_RFSSEL_PORT7    (0x6 << 17)
 889
 890 #define AUDMUX_PTCR_RCLKDIR         (1 << 16)
 891
 892 #define AUDMUX_PTCR_RCSEL           (0xf << 12)
 893 #define AUDMUX_PTCR_RCSEL_TXFS      (0x0 << 12)
 894 #define AUDMUX_PTCR_RCSEL_RXFS      (0x8 << 12)
 895 #define AUDMUX_PTCR_RCSEL_PORT1     (0x0 << 12)
 896 #define AUDMUX_PTCR_RCSEL_PORT2     (0x1 << 12)
 897 #define AUDMUX_PTCR_RCSEL_PORT3     (0x2 << 12)
 898 #define AUDMUX_PTCR_RCSEL_PORT4     (0x3 << 12)
 899 #define AUDMUX_PTCR_RCSEL_PORT5     (0x4 << 12)
 900 #define AUDMUX_PTCR_RCSEL_PORT6     (0x5 << 12)
 901 #define AUDMUX_PTCR_RCSEL_PORT7     (0x6 << 12)
 902 #define AUDMUX_PTCR_SYN             (1 << 11)
 903
 904 #define AUDMUX_PDCR_RXDSEL          (0x7 << 13)
 905 #define AUDMUX_PDCR_RXDSEL_PORT1    (0 << 13)
 906 #define AUDMUX_PDCR_RXDSEL_PORT2    (1 << 13)
 907 #define AUDMUX_PDCR_RXDSEL_PORT3    (2 << 13)
 908 #define AUDMUX_PDCR_RXDSEL_PORT4    (3 << 13)
 909 #define AUDMUX_PDCR_RXDSEL_PORT5    (4 << 13)
 910 #define AUDMUX_PDCR_RXDSEL_PORT6    (5 << 13)
 911 #define AUDMUX_PDCR_RXDSEL_PORT7    (6 << 13)
 912 #define AUDMUX_PDCR_TXRXEN          (1 << 12)
 913
 914 #define AUDMUX_CNMCR_BEN            (1 << 18)
 915 #define AUDMUX_CNMCR_FSPOL          (1 << 17)
 916 #define AUDMUX_CNMCR_CLKPOL         (1 << 16)
 917
 918 #define AUDMUX_CNMCR_CNTHI          (0xff << 8)
 919 #define AUDMUX_CNMCR_CNTHIw(x)      (((x) << 8) & AUDMUX_CNMCR_CNTHI)
 920
 921 #define AUDMUX_CNMCR_CNTLOW         (0xff << 0)
 922 #define AUDMUX_CNMCR_CNTLOWw(x)     (((x) << 0) & AUDMUX_CNMCR_CNTLOW)
 923
 924 /* SSI */
 925 #define SSI_STX0_1              (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x00))
 926 #define SSI_STX1_1              (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x04))
 927 #define SSI_SRX0_1              (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x08))
 928 #define SSI_SRX1_1              (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x0C))
 929 #define SSI_SCR1                (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x10))
 930 #define SSI_SISR1               (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x14))
 931 #define SSI_SIER1               (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x18))
 932 #define SSI_STCR1               (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x1C))
 933 #define SSI_SRCR1               (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x20))
 934 #define SSI_STCCR1              (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x24))
 935 #define SSI_SRCCR1              (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x28))
 936 #define SSI_SFCSR1              (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x2C))
 937 #define SSI_SACNT1              (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x38))
 938 #define SSI_SACADD1             (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x3C))
 939 #define SSI_SACDAT1             (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x40))
 940 #define SSI_SATAG1              (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x44))
 941 #define SSI_STMSK1              (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x48))
 942 #define SSI_SRMSK1              (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x4C))
 943
 944 #define SSI_STX0_2              (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x00))
 945 #define SSI_STX1_2              (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x04))
 946 #define SSI_SRX0_2              (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x08))
 947 #define SSI_SRX1_2              (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x0C))
 948 #define SSI_SCR2                (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x10))
 949 #define SSI_SISR2               (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x14))
 950 #define SSI_SIER2               (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x18))
 951 #define SSI_STCR2               (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x1C))
 952 #define SSI_SRCR2               (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x20))
 953 #define SSI_STCCR2              (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x24))
 954 #define SSI_SRCCR2              (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x28))
 955 #define SSI_SFCSR2              (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x2C))
 956 #define SSI_SACNT2              (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x38))
 957 #define SSI_SACADD2             (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x3C))
 958 #define SSI_SACDAT2             (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x40))
 959 #define SSI_SATAG2              (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x44))
 960 #define SSI_STMSK2              (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x48))
 961 #define SSI_SRMSK2              (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x4C))
 962
 963 /* SSI SCR */
 964 #define SSI_SCR_CLK_IST         (0x1 << 9)
 965 #define SSI_SCR_TCHN_EN         (0x1 << 8)
 966 #define SSI_SCR_SYS_CLK_EN      (0x1 << 7)
 967
 968 #define SSI_SCR_I2S_MODE        (0x3 << 5)
 969 #define SSI_SCR_I2S_MODE_NORMAL (0x0 << 5)
 970 #define SSI_SCR_I2S_MODE_MASTER (0x1 << 5)
 971 #define SSI_SCR_I2S_MODE_SLAVE  (0x2 << 5)
 972 #define SSI_SCR_I2S_MODE_NOR2   (0x3 << 5)
 973
 974 #define SSI_SCR_SYN             (0x1 << 4)
 975 #define SSI_SCR_NET             (0x1 << 3)
 976 #define SSI_SCR_RE              (0x1 << 2)
 977 #define SSI_SCR_TE              (0x1 << 1)
 978 #define SSI_SCR_SSIEN           (0x1 << 0)
 979
 980 /* SSI SISR */
 981 #define SSI_SISR_CMDAU          (0x1 << 18)
 982 #define SSI_SISR_CMDDU          (0x1 << 17)
 983 #define SSI_SISR_RXT            (0x1 << 16)
 984 #define SSI_SISR_RDR1           (0x1 << 15)
 985 #define SSI_SISR_RDR0           (0x1 << 14)
 986 #define SSI_SISR_TDE1           (0x1 << 13)
 987 #define SSI_SISR_TDE0           (0x1 << 12)
 988 #define SSI_SISR_ROE1           (0x1 << 11)
 989 #define SSI_SISR_ROE0           (0x1 << 10)
 990 #define SSI_SISR_TUE1           (0x1 << 9)
 991 #define SSI_SISR_TUE0           (0x1 << 8)
 992 #define SSI_SISR_TFS            (0x1 << 7)
 993 #define SSI_SISR_RFS            (0x1 << 6)
 994 #define SSI_SISR_TLS            (0x1 << 5)
 995 #define SSI_SISR_RLS            (0x1 << 4)
 996 #define SSI_SISR_RFF1           (0x1 << 3)
 997 #define SSI_SISR_RFF2           (0x1 << 2)
 998 #define SSI_SISR_TFE1           (0x1 << 1)
 999 #define SSI_SISR_TFE0           (0x1 << 0)
1000
1001 /* SSI SIER */
1002 #define SSI_SIER_RDMAE          (0x1 << 22)
1003 #define SSI_SIER_RIE            (0x1 << 21)
1004 #define SSI_SIER_TDMAE          (0x1 << 20)
1005 #define SSI_SIER_TIE            (0x1 << 19)
1006 #define SSI_SIER_CMDAU          (0x1 << 18)
1007 #define SSI_SIER_CMDDU          (0x1 << 17)
1008 #define SSI_SIER_RXT            (0x1 << 16)
1009 #define SSI_SIER_RDR1           (0x1 << 15)
1010 #define SSI_SIER_RDR0           (0x1 << 14)
1011 #define SSI_SIER_TDE1           (0x1 << 13)
1012 #define SSI_SIER_TDE0           (0x1 << 12)
1013 #define SSI_SIER_ROE1           (0x1 << 11)
1014 #define SSI_SIER_ROE0           (0x1 << 10)
1015 #define SSI_SIER_TUE1           (0x1 << 9)
1016 #define SSI_SIER_TUE0           (0x1 << 8)
1017 #define SSI_SIER_TFS            (0x1 << 7)
1018 #define SSI_SIER_RFS            (0x1 << 6)
1019 #define SSI_SIER_TLS            (0x1 << 5)
1020 #define SSI_SIER_RLS            (0x1 << 4)
1021 #define SSI_SIER_RFF1           (0x1 << 3)
1022 #define SSI_SIER_RFF0           (0x1 << 2)
1023 #define SSI_SIER_TFE1           (0x1 << 1)
1024 #define SSI_SIER_TFE0           (0x1 << 0)
1025
1026 /* SSI STCR */
1027 #define SSI_STCR_TXBIT0         (0x1 << 9)
1028 #define SSI_STCR_TFEN1          (0x1 << 8)
1029 #define SSI_STCR_TFEN0          (0x1 << 7)
1030 #define SSI_STCR_TFDIR          (0x1 << 6)
1031 #define SSI_STCR_TXDIR          (0x1 << 5)
1032 #define SSI_STCR_TSHFD          (0x1 << 4)
1033 #define SSI_STCR_TSCKP          (0x1 << 3)
1034 #define SSI_STCR_TFSI           (0x1 << 2)
1035 #define SSI_STCR_TFSL           (0x1 << 1)
1036 #define SSI_STCR_TEFS           (0x1 << 0)
1037
1038 /* SSI SRCR */
1039 #define SSI_SRCR_RXEXT          (0x1 << 10)
1040 #define SSI_SRCR_RXBIT0         (0x1 << 9)
1041 #define SSI_SRCR_RFEN1          (0x1 << 8)
1042 #define SSI_SRCR_RFEN0          (0x1 << 7)
1043 #define SSI_SRCR_RFDIR          (0x1 << 6)
1044 #define SSI_SRCR_RXDIR          (0x1 << 5)
1045 #define SSI_SRCR_RSHFD          (0x1 << 4)
1046 #define SSI_SRCR_RSCKP          (0x1 << 3)
1047 #define SSI_SRCR_RFSI           (0x1 << 2)
1048 #define SSI_SRCR_RFSL           (0x1 << 1)
1049 #define SSI_SRCR_REFS           (0x1 << 0)
1050
1051 /* SSI STCCR/SRCCR */
1052 #define SSI_STRCCR_DIV2         (0x1 << 18)
1053 #define SSI_STRCCR_PSR          (0x1 << 17)
1054
1055 #define SSI_STRCCR_WL           (0xf << 13)
1056 #define SSI_STRCCR_WL8          (0x3 << 13)
1057 #define SSI_STRCCR_WL10         (0x4 << 13)
1058 #define SSI_STRCCR_WL12         (0x5 << 13)
1059 #define SSI_STRCCR_WL16         (0x7 << 13)
1060 #define SSI_STRCCR_WL18         (0x8 << 13)
1061 #define SSI_STRCCR_WL20         (0x9 << 13)
1062 #define SSI_STRCCR_WL22         (0xa << 13)
1063 #define SSI_STRCCR_WL24         (0xb << 13)
1064
1065 #define SSI_STRCCR_DC           (0x1f << 8)
1066 #define SSI_STRCCR_DCw(x)       (((x) << 8) & SSI_STRCCR_DC)
1067 #define SSI_STRCCR_DCr(x)       (((x) & SSI_SRCCR_DC) >> 8)
1068
1069 #define SSI_STRCCR_PM           (0xf << 0)
1070 #define SSI_STRCCR_PMw(x)       (((x) << 0) & SSI_STRCCR_PM)
1071 #define SSI_STRCCR_PMr(x)       (((x) & SSI_SRCCR_PM) >> 0)
1072
1073 /* SSI SFCSR */
1074 #define SSI_SFCSR_RFCNT1        (0xf << 28)
1075 #define SSI_SFCSR_RFCNT1w(x)    (((x) << 28) & SSI_SFCSR_RFCNT1)
1076 #define SSI_SFCSR_RFCNT1r(x)    (((x) & SSI_SFCSR_RFCNT1) >> 28)
1077
1078 #define SSI_SFCSR_TFCNT1        (0xf << 24)
1079 #define SSI_SFCSR_TFCNT1w(x)    (((x) << 24) & SSI_SFCSR_TFCNT1)
1080 #define SSI_SFCSR_TFCNT1r(x)    (((x) & SSI_SFCSR_TFCNT1) >> 24)
1081
1082 #define SSI_SFCSR_RFWM1         (0xf << 20)
1083 #define SSI_SFCSR_RFWM1w(x)     (((x) << 20) & SSI_SFCSR_RFWM1)
1084 #define SSI_SFCSR_RFWM1r(x)     (((x) & SSI_SFCSR_RFWM1) >> 20)
1085 #define SSI_SFCSR_RFWM1_1       (0x1 << 20)
1086 #define SSI_SFCSR_RFWM1_2       (0x2 << 20)
1087 #define SSI_SFCSR_RFWM1_3       (0x3 << 20)
1088 #define SSI_SFCSR_RFWM1_4       (0x4 << 20)
1089 #define SSI_SFCSR_RFWM1_5       (0x5 << 20)
1090 #define SSI_SFCSR_RFWM1_6       (0x6 << 20)
1091 #define SSI_SFCSR_RFWM1_7       (0x7 << 20)
1092
1093 #define SSI_SFCSR_TFWM1         (0xf << 16)
1094 #define SSI_SFCSR_TFWM1w(x)     (((x) << 16) & SSI_SFCSR_TFWM1)
1095 #define SSI_SFCSR_TFWM1r(x)     (((x) & SSI_SFCSR_TFWM1) >> 16)
1096
1097 #define SSI_SFCSR_RFCNT0        (0xf << 12)
1098 #define SSI_SFCSR_RFCNT0w(x)    (((x) << 12) & SSI_SFCSR_RFCNT0)
1099 #define SSI_SFCSR_RFCNT0r(x)    (((x) & SSI_SFCSR_RFCNT0) >> 12)
1100
1101 #define SSI_SFCSR_TFCNT0        (0xf << 8)
1102 #define SSI_SFCSR_TFCNT0w(x)    (((x) << 8) & SSI_SFCSR_TFCNT0)
1103 #define SSI_SFCSR_TFCNT0r(x)    (((x) & SSI_SFCSR_TFCNT0) >> 8)
1104
1105 #define SSI_SFCSR_RFWM0         (0xf << 4)
1106 #define SSI_SFCSR_RFWM0w(x)     (((x) << 4) & SSI_SFCSR_RFWM0)
1107 #define SSI_SFCSR_RFWM0r(x)     (((x) & SSI_SFCSR_RFWM0) >> 4)
1108
1109 #define SSI_SFCSR_TFWM0         (0xf << 0)
1110 #define SSI_SFCSR_TFWM0w(x)     (((x) << 0) & SSI_SFCSR_TFWM0)
1111 #define SSI_SFCSR_TFWM0r(x)     (((x) & SSI_SFCSR_TFWM0) >> 0)
1112
1113 /* SACNT */
1114 #define SSI_SACNT_FRDIV         (0x3f << 5)
1115 #define SSI_SACNT_FRDIVw(x)     (((x) << 5) & SSI_SACNT_FRDIV)
1116 #define SSI_SACNT_FRDIVr(x)     (((x) & SSI_SACNT_FRDIV) >> 5)
1117
1118 #define SSI_SACNT_WR            (0x1 << 4)
1119 #define SSI_SACNT_RD            (0x1 << 3)
1120 #define SSI_SACNT_TIF           (0x1 << 2)
1121 #define SSI_SACNT_FV            (0x1 << 1)
1122 #define SSI_SACNT_AC97EN        (0x1 << 0)
1123
1124 /* RTC */
1125 #define RTC_HOURMIN             (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00))
1126 #define RTC_SECONDS             (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04))
1127 #define RTC_ALRM_HM             (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08))
1128 #define RTC_ALRM_SEC            (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C))
1129 #define RTC_CTL                 (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10))
1130 #define RTC_ISR                 (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14))
1131 #define RTC_IENR                (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18))
1132 #define RTC_STPWCH              (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C))
1133 #define RTC_DAYR                (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20))
1134 #define RTC_DAYALARM            (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24))
1135
1136 /* Watchdog */
1137 #define WDOG_WCR                (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x00))
1138 #define WDOG_WSR                (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x02))
1139 #define WDOG_WRSR               (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x04))
1140
1141 #define WDOG_WCR_WT             (0xff << 8)
1142 #define WDOG_WCR_WTw(x)         (((x) << 8) & WDOG_WCR_WT)
1143 #define WDOG_WCR_WTr(x)         (((x) & WDOG_WCR_WT) >> 8)
1144
1145 #define WDOG_WCR_WOE            (0x1 << 6)
1146 #define WDOG_WCR_WDA            (0x1 << 5)
1147 #define WDOG_WCR_SRS            (0x1 << 4)
1148 #define WDOG_WCR_WRE            (0x1 << 3)
1149 #define WDOG_WCR_WDE            (0x1 << 2)
1150 #define WDOG_WCR_WDBG           (0x1 << 1)
1151 #define WDOG_WCR_WDZST          (0x1 << 0)
1152
1153 #define WDOG_WRSR_JRST          (0x1 << 5)
1154 #define WDOG_WRSR_PWR           (0x1 << 4)
1155 #define WDOG_WRSR_EXT           (0x1 << 3)
1156 #define WDOG_WRSR_CMON          (0x1 << 2)
1157 #define WDOG_WRSR_TOUT          (0x1 << 1)
1158 #define WDOG_WRSR_SFTW          (0x1 << 0)
1159
1160 /* Keypad */
1161 #define KPP_KPCR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x0))
1162 #define KPP_KPSR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x2))
1163 #define KPP_KDDR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4))
1164 #define KPP_KPDR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6))
1165
1166 /* KPP_KPSR bits */
1167 #define KPP_KPSR_KRIE           (1 << 9)
1168 #define KPP_KPSR_KDIE           (1 << 8)
1169 #define KPP_KPSR_KRSS           (1 << 3)
1170 #define KPP_KPSR_KDSC           (1 << 2)
1171 #define KPP_KPSR_KPKR           (1 << 1)
1172 #define KPP_KPSR_KPKD           (1 << 0)
1173
1174 /* SDHC */
1175 #define SDHC1_CLOCK_CONTROL     (*(REG32_PTR_T)(MMC_SDHC1_BASE_ADDR+0x00))
1176 #define SDHC2_CLOCK_CONTROL     (*(REG32_PTR_T)(MMC_SDHC2_BASE_ADDR+0x00))
1177
1178 /* SDHC bits */
1179 #define STOP_CLK                (1 << 0)
1180
1181 /* ROMPATCH and AVIC */
1182 #define ROMPATCH_BASE_ADDR      0x60000000
1183
1184 /* Since AVIC vector registers are NOT used, we reserve some for various
1185  * purposes. Copied from Linux source code. */
1186 #define CHIP_REV_1_0            0x10
1187 #define CHIP_REV_2_0            0x20
1188 #define SYSTEM_REV_ID_REG       (AVIC_BASE_ADDR + AVIC_VEC_1)
1189 #define SYSTEM_REV_ID_MAG       0xF00C
1190
1191 /*
1192  * NAND, SDRAM, WEIM, M3IF, EMI controllers
1193  */
1194 #define EXT_MEM_CTRL_BASE       0xB8000000
1195 #define NFC_BASE                EXT_MEM_CTRL_BASE
1196 #define ESDCTL_BASE             0xB8001000
1197 #define WEIM_BASE_ADDR          0xB8002000
1198 #define WEIM_CTRL_CS0           (WEIM_BASE_ADDR+0x00)
1199 #define WEIM_CTRL_CS1           (WEIM_BASE_ADDR+0x10)
1200 #define WEIM_CTRL_CS2           (WEIM_BASE_ADDR+0x20)
1201 #define WEIM_CTRL_CS3           (WEIM_BASE_ADDR+0x30)
1202 #define WEIM_CTRL_CS4           (WEIM_BASE_ADDR+0x40)
1203 #define M3IF_BASE               0xB8003000
1204 #define PCMCIA_CTL_BASE         0xB8004000
1205
1206 /*
1207  * Memory regions and CS
1208  */
1209 #define IPU_MEM_BASE_ADDR       0x70000000
1210 #define CSD0_BASE_ADDR          0x80000000
1211 #define CSD1_BASE_ADDR          0x90000000
1212 #define CS0_BASE_ADDR           0xA0000000
1213 #define CS1_BASE_ADDR           0xA8000000
1214 #define CS2_BASE_ADDR           0xB0000000
1215 #define CS3_BASE_ADDR           0xB2000000
1216 #define CS4_BASE_ADDR           0xB4000000
1217 #define CS4_BASE_PSRAM          0xB5000000
1218 #define CS5_BASE_ADDR           0xB6000000
1219 #define PCMCIA_MEM_BASE_ADDR    0xC0000000
1220
1221 #define INTERNAL_ROM_VA         0xF0000000
1222
1223 /*
1224  * SDRAM
1225  */
1226 #define RAM_BANK0_BASE          SDRAM_BASE_ADDR
1227
1228 /*
1229  * IRQ Controller Register Definitions.
1230  */
1231 #define AVIC_BASE_ADDR         0x68000000
1232 #define INTCNTL                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
1233 #define NIMASK                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
1234 #define INTENNUM               (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
1235 #define INTDISNUM              (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
1236 #define INTENABLEH             (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
1237 #define INTENABLEL             (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
1238 #define INTTYPEH               (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
1239 #define INTTYPEL               (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
1240 #define NIPRIORITY(n)          (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n])
1241 #define NIPRIORITY7            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
1242 #define NIPRIORITY6            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
1243 #define NIPRIORITY5            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
1244 #define NIPRIORITY4            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
1245 #define NIPRIORITY3            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
1246 #define NIPRIORITY2            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
1247 #define NIPRIORITY1            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
1248 #define NIPRIORITY0            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
1249 #define NIVECSR                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
1250 #define FIVECSR                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
1251 #define INTSRCH                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
1252 #define INTSRCL                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
1253 #define INTFRCH                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
1254 #define INTFRCL                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
1255 #define NIPNDH                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
1256 #define NIPNDL                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
1257 #define FIPNDH                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
1258 #define FIPNDL                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
1259 #define VECTOR_BASE_ADDR       (AVIC_BASE_ADDR+0x100)
1260 #define VECTOR(n)              (((REG32_PTR_T)VECTOR_BASE_ADDR)[n])
1261
1262 /* The vectors go all the way up to 63. 4 bytes for each */
1263 #define INTCNTL_ABFLAG         (1 << 25)
1264 #define INTCNTL_ABFEN          (1 << 24)
1265 #define INTCNTL_NIDIS          (1 << 22)
1266 #define INTCNTL_FIDIS          (1 << 21)
1267 #define INTCNTL_NIAD           (1 << 20)
1268 #define INTCNTL_FIAD           (1 << 19)
1269 #define INTCNTL_NM             (1 << 18)
1270
1271 /* L210 */
1272 #define L2CC_BASE_ADDR                  0x30000000
1273 #define L2_CACHE_LINE_SIZE              32
1274 #define L2_CACHE_CTL_REG                0x100
1275 #define L2_CACHE_AUX_CTL_REG            0x104
1276 #define L2_CACHE_SYNC_REG               0x730
1277 #define L2_CACHE_INV_LINE_REG           0x770
1278 #define L2_CACHE_INV_WAY_REG            0x77C
1279 #define L2_CACHE_CLEAN_LINE_REG         0x7B0
1280 #define L2_CACHE_CLEAN_INV_LINE_REG     0x7F0
1281
1282 #define L2CC_CACHE_SYNC                 (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG))
1283
1284 /* CCM */
1285 #define CLKCTL_CCMR                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
1286 #define CLKCTL_PDR0                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
1287 #define CLKCTL_PDR1                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
1288 #define CLKCTL_RCSR                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
1289 #define CLKCTL_MPCTL                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
1290 #define CLKCTL_UPCTL                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
1291 #define CLKCTL_SPCTL                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
1292 #define CLKCTL_COSR                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
1293 #define CLKCTL_CGR0                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
1294 #define CLKCTL_CGR1                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
1295 #define CLKCTL_CGR2                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
1296 #define CLKCTL_WIMR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
1297 #define CLKCTL_LDC                      (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30))
1298 #define CLKCTL_DCVR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34))
1299 #define CLKCTL_DCVR1                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38))
1300 #define CLKCTL_DCVR2                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C))
1301 #define CLKCTL_DCVR3                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40))
1302 #define CLKCTL_LTR0                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44))
1303 #define CLKCTL_LTR1                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48))
1304 #define CLKCTL_LTR2                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C))
1305 #define CLKCTL_LTR3                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50))
1306 #define CLKCTL_LTBR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54))
1307 #define CLKCTL_LTBR1                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58))
1308 #define CLKCTL_PMCR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
1309 #define CLKCTL_PMCR1                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60))
1310 #define CLKCTL_PDR2                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
1311
1312 /* CCMR */
1313 #define CCMR_L2PG                       (0x1 << 29)
1314 #define CCMR_VSTBY                      (0x1 << 28)
1315 #define CCMR_WBEN                       (0x1 << 27)
1316 #define CCMR_FPMF                       (0x1 << 26)
1317 #define CCMR_CSCS                       (0x1 << 25)
1318 #define CCMR_PERCS                      (0x1 << 24)
1319
1320 #define CCMR_SSI2S                      (0x3 << 21)
1321 #define CCMR_SSI2S_MCU_CLK              (0x0 << 21)
1322 #define CCMR_SSI2S_USB_CLK              (0x1 << 21)
1323 #define CCMR_SSI2S_SERIAL_CLK           (0x2 << 21) /* default */
1324
1325 #define CCMR_SSI1S                      (0x3 << 18)
1326 #define CCMR_SSI1S_MCU_CLK              (0x0 << 18)
1327 #define CCMR_SSI1S_USB_CLK              (0x1 << 18)
1328 #define CCMR_SSI1S_SERIAL_CLK           (0x2 << 18) /* default */
1329
1330 #define CCMR_RAMW                       (0x3 << 16)
1331 #define CCMR_RAMW_0ARM_0ALTMS           (0x0 << 16)
1332 #define CCMR_RAMW_0ARM_1ALTMS           (0x1 << 16) /* Not recommended */
1333 #define CCMR_RAMW_1ARM_0ALTMS           (0x2 << 16) /* Not recommended */
1334 #define CCMR_RAMW_1ARM_1ALTMS           (0x3 << 16)
1335
1336 #define CCMR_LPM                        (0x3 << 14)
1337 #define CCMR_LPM_WAIT_MODE              (0x0 << 14)
1338 #define CCMR_LPM_DOZE_MODE              (0x1 << 14)
1339 #define CCMR_LPM_SRM                    (0x2 << 14) /* State retention mode */
1340 #define CCMR_LPM_DSM                    (0x3 << 14) /* Deep sleep mode */
1341
1342 #define CCMR_FIRS                       (0x3 << 11)
1343 #define CCMR_FIRS_MCU_CLK               (0x0 << 11)
1344 #define CCMR_FIRS_USB_CLK               (0x1 << 11)
1345 #define CCMR_FIRS_SERIAL_CLK            (0x2 << 11)
1346
1347 #define CCMR_WAMO                       (0x1 << 10)
1348 #define CCMR_UPE                        (0x1 << 9)
1349 #define CCMR_SPE                        (0x1 << 8)
1350 #define CCMR_MDS                        (0x1 << 7)
1351
1352 #define CCMR_ROMW                       (0x3 << 5)
1353 #define CCMR_ROMW_0ARM_0ALTMS           (0x0 << 5)
1354 #define CCMR_ROMW_0ARM_1ALTMS           (0x1 << 5) /* Not recommended */
1355 #define CCMR_ROMW_1ARM_0ALTMS           (0x2 << 5) /* Not recommended */
1356 #define CCMR_ROMW_1ARM_1ALTMS           (0x3 << 5)
1357
1358 #define CCMR_SBYCS                      (0x1 << 4)
1359 #define CCMR_MPE                        (0x1 << 3)
1360
1361 #define CCMR_PRCS                       (0x3 << 1)
1362 #define CCMR_PRCS_FPM                   (0x1 << 1)
1363 #define CCMR_PRCS_CKIH                  (0x2 << 1)
1364
1365 #define CCMR_FPME                       (0x1 << 0)
1366
1367 /* PDR0 */
1368 #define PDR0_CSI_PODF                   (0x1ff << 23)
1369 #define PDR0_CSI_PODFw(x)               (((x) << 23) & PDR0_CSI_PODF)
1370 #define PDR0_CSI_PODFr(x)               (((x) & PDR0_CSI_PODF) >> 23)
1371
1372 #define PDR0_PER_PODF                   (0x1f << 16)
1373 #define PDR0_PER_PODFw(x)               (((x) << 16) & PDR0_PER_PODF)
1374 #define PDR0_PER_PODFr(x)               (((x) & PDR0_PER_PODF) >> 16)
1375
1376 #define PDR0_HSP_PODF                   (0x7 << 11)
1377 #define PDR0_HSP_PODFw(x)               (((x) << 11) & PDR0_HSP_PODF)
1378 #define PDR0_HSP_PODFr(x)               (((x) & PDR0_HSP_PODF) >> 11)
1379
1380 #define PDR0_NFC_PODF                   (0x7 << 8)
1381 #define PDR0_NFC_PODFw(x)               (((x) << 8) & PDR0_NFC_PODF)
1382 #define PDR0_NFC_PODFr(x)               (((x) & PDR0_NFC_PODF) >> 8)
1383
1384 #define PDR0_IPG_PODF                   (0x3 << 6)
1385 #define PDR0_IPG_PODFw(x)               (((x) << 6) & PDR0_IPG_PODF)
1386 #define PDR0_IPG_PODFr(x)               (((x) & PDR0_IPG_PODF) >> 6)
1387
1388 #define PDR0_MAX_PODF                   (0x7 << 3)
1389 #define PDR0_MAX_PODFw(x)               (((x) << 3) & PDR0_MAX_PODF)
1390 #define PDR0_MAX_PODFr(x)               (((x) & PDR0_MAX_PODF) >> 3)
1391
1392 #define PDR0_MCU_PODF                   (0x7 << 0)
1393 #define PDR0_MCU_PODFw(x)               (((x) << 0) & PDR0_MCU_PODF)
1394 #define PDR0_MCU_PODFr(x)               (((x) & PDR0_MCU_PODF) >> 0)
1395
1396 /* PDR1 */
1397 #define PDR1_USB_PRDF                   (0x3 << 30)
1398 #define PDR1_USB_PRDFw(x)               (((x) << 30) & PDR1_USB_PRDF)
1399 #define PDR1_USB_PRDFr(x)               (((x) & PDR1_USB_PRDF) >> 30)
1400
1401 #define PDR1_USB_PODF                   (0x7 << 27)
1402 #define PDR1_USB_PODFw(x)               (((x) << 27) & PDR1_USB_PODF)
1403 #define PDR1_USB_PODFr(x)               (((x) & PDR1_USB_PODF) >> 27)
1404
1405 #define PDR1_FIRI_PRE_PODF              (0x7 << 24)
1406 #define PDR1_FIRI_PRE_PODFw(x)          (((x) << 24) & PDR1_FIRI_PRE_PODF)
1407 #define PDR1_FIRI_PRE_PODFr(x)          (((x) & PDR1_FIRI_PRE_PODF) >> 24)
1408
1409 #define PDR1_FIRI_PODF                  (0x3f << 18)
1410 #define PDR1_FIRI_PODFw(x)              (((x) << 18) & PDR1_FIRI_PODF)
1411 #define PDR1_FIRI_PODFr(x)              (((x) & PDR1_FIRI_PODF) >> 18)
1412
1413 #define PDR1_SSI2_PRE_PODF              (0x7 << 15)
1414 #define PDR1_SSI2_PRE_PODFw(x)          (((x) << 15) & PDR1_SSI2_PRE_PODF)
1415 #define PDR1_SSI2_PRE_PODFr(x)          (((x) & PDR1_SSI2_PRE_PODF) >> 15)
1416
1417 #define PDR1_SSI2_PODF                  (0x3f << 9)
1418 #define PDR1_SSI2_PODFw(x)              (((x) << 9) & PDR1_SSI2_PODF)
1419 #define PDR1_SSI2_PODFr(x)              (((x) & PDR1_SSI2_PODF) >> 9)
1420
1421 #define PDR1_SSI1_PRE_PODF              (0x7 << 6)
1422 #define PDR1_SSI1_PRE_PODFw(x)          (((x) << 6) & PDR1_SSI1_PRE_PODF)
1423 #define PDR1_SSI1_PRE_PODFr(x)          (((x) & PDR1_SSI1_PRE_PODF) >> 6)
1424
1425 #define PDR1_SSI1_PODF                  (0x3f << 0)
1426 #define PDR1_SSI1_PODFw(x)              (((x) << 0) & PDR1_SSI1_PODF)
1427 #define PDR1_SSI1_PODFr(x)              (((x) & PDR1_SSI1_PODF) >> 0)
1428
1429 #define CGR0_SD_MMC1(cg)                ((cg) << 0*2)
1430 #define CGR0_SD_MMC2(cg)                ((cg) << 1*2)
1431 #define CGR0_GPT(cg)                    ((cg) << 2*2)
1432 #define CGR0_EPIT1(cg)                  ((cg) << 3*2)
1433 #define CGR0_EPIT2(cg)                  ((cg) << 4*2)
1434 #define CGR0_IIM(cg)                    ((cg) << 5*2)
1435 #define CGR0_ATA(cg)                    ((cg) << 6*2)
1436 #define CGR0_SDMA(cg)                   ((cg) << 7*2)
1437 #define CGR0_CSPI3(cg)                  ((cg) << 8*2)
1438 #define CGR0_RNG(cg)                    ((cg) << 9*2)
1439 #define CGR0_UART1(cg)                  ((cg) << 10*2)
1440 #define CGR0_UART2(cg)                  ((cg) << 11*2)
1441 #define CGR0_SSI1(cg)                   ((cg) << 12*2)
1442 #define CGR0_I2C1(cg)                   ((cg) << 13*2)
1443 #define CGR0_I2C2(cg)                   ((cg) << 14*2)
1444 #define CGR0_I2C3(cg)                   ((cg) << 15*2)
1445
1446 #define CGR1_HANTRO(cg)                 ((cg) << 0*2)
1447 #define CGR1_MEMSTICK1(cg)              ((cg) << 1*2)
1448 #define CGR1_MEMSTICK2(cg)              ((cg) << 2*2)
1449 #define CGR1_CSI(cg)                    ((cg) << 3*2)
1450 #define CGR1_RTC(cg)                    ((cg) << 4*2)
1451 #define CGR1_WDOG(cg)                   ((cg) << 5*2)
1452 #define CGR1_PWM(cg)                    ((cg) << 6*2)
1453 #define CGR1_SIM(cg)                    ((cg) << 7*2)
1454 #define CGR1_ECT(cg)                    ((cg) << 8*2)
1455 #define CGR1_USBOTG(cg)                 ((cg) << 9*2)
1456 #define CGR1_KPP(cg)                    ((cg) << 10*2)
1457 #define CGR1_IPU(cg)                    ((cg) << 11*2)
1458 #define CGR1_UART3(cg)                  ((cg) << 12*2)
1459 #define CGR1_UART4(cg)                  ((cg) << 13*2)
1460 #define CGR1_UART5(cg)                  ((cg) << 14*2)
1461 #define CGR1_1_WIRE(cg)                 ((cg) << 15*2)
1462
1463 #define CGR2_SSI2(cg)                   ((cg) << 0*2)
1464 #define CGR2_CSPI1(cg)                  ((cg) << 1*2)
1465 #define CGR2_CSPI2(cg)                  ((cg) << 2*2)
1466 #define CGR2_GACC(cg)                   ((cg) << 3*2)
1467 #define CGR2_EMI(cg)                    ((cg) << 4*2)
1468 #define CGR2_RTIC(cg)                   ((cg) << 5*2)
1469 #define CGR2_FIR(cg)                    ((cg) << 6*2)
1470
1471 #define WIM_GPIO3                       (1 << 0)
1472 #define WIM_GPIO2                       (1 << 1)
1473 #define WIM_GPIO1                       (1 << 2)
1474 #define WIM_PCMCIA                      (1 << 3)
1475 #define WIM_WDT                         (1 << 4)
1476 #define WIM_USB_OTG                     (1 << 5)
1477 #define WIM_IPI_INT_UH2                 (1 << 6)
1478 #define WIM_IPI_INT_UH1                 (1 << 7)
1479 #define WIM_IPI_INT_UART5_ANDED         (1 << 8)
1480 #define WIM_IPI_INT_UART4_ANDED         (1 << 9)
1481 #define WIM_IPI_INT_UART3_ANDED         (1 << 10)
1482 #define WIM_IPI_INT_UART2_ANDED         (1 << 11)
1483 #define WIM_IPI_INT_UART1_ANDED         (1 << 12)
1484 #define WIM_IPI_INT_SIM_DATA_IRQ        (1 << 13)
1485 #define WIM_IPI_INT_SDHC2               (1 << 14)
1486 #define WIM_IPI_INT_SDHC1               (1 << 15)
1487 #define WIM_IPI_INT_RTC                 (1 << 16)
1488 #define WIM_IPI_INT_PWM                 (1 << 17)
1489 #define WIM_IPI_INT_KPP                 (1 << 18)
1490 #define WIM_IPI_INT_IIM                 (1 << 19)
1491 #define WIM_IPI_INT_GPT                 (1 << 20)
1492 #define WIM_IPI_INT_FIR                 (1 << 21)
1493 #define WIM_IPI_INT_EPIT2               (1 << 22)
1494 #define WIM_IPI_INT_EPIT1               (1 << 23)
1495 #define WIM_IPI_INT_CSPI2               (1 << 24)
1496 #define WIM_IPI_INT_CSPI1               (1 << 25)
1497 #define WIM_IPI_INT_POWER_FAIL          (1 << 26)
1498 #define WIM_IPI_INT_CSPI3               (1 << 27)
1499 #define WIM_RESERVED28                  (1 << 28)
1500 #define WIM_RESERVED29                  (1 << 29)
1501 #define WIM_RESERVED30                  (1 << 30)
1502 #define WIM_RESERVED31                  (1 << 31)
1503
1504 /* WEIM - CS0 */
1505 #define CSCRU                           0x00
1506 #define CSCRL                           0x04
1507 #define CSCRA                           0x08
1508
1509 /* ESDCTL */
1510 #define ESDCTL_ESDCTL0                  0x00
1511 #define ESDCTL_ESDCFG0                  0x04
1512 #define ESDCTL_ESDCTL1                  0x08
1513 #define ESDCTL_ESDCFG1                  0x0C
1514 #define ESDCTL_ESDMISC                  0x10
1515
1516 /* More UART 1 Register defines */
1517 #define URXD1                           (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00))
1518 #define UTXD1                           (*(REG32_PTR_T)(UART1_BASE_ADDR+0x40))
1519 #define UCR1_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x80))
1520 #define UCR2_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x84))
1521 #define UCR3_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x88))
1522 #define UCR4_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x8C))
1523 #define UFCR1                           (*(REG32_PTR_T)(UART1_BASE_ADDR+0x90))
1524 #define USR1_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x94))
1525 #define USR2_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x98))
1526 #define UTS1                            (*(REG32_PTR_T)(UART1_BASE_ADDR+0xB4))
1527
1528 #define UCR1_2                          (*(REG32_PTR_T)(UART2_BASE_ADDR+0x80))
1529 #define UCR1_3                          (*(REG32_PTR_T)(UART3_BASE_ADDR+0x80))
1530 #define UCR1_4                          (*(REG32_PTR_T)(UART4_BASE_ADDR+0x80))
1531 #define UCR1_5                          (*(REG32_PTR_T)(UART5_BASE_ADDR+0x80))
1532
1533 /*
1534  * UART Control Register 0 Bit Fields.
1535  */
1536 #define EUARTUCR1_ADEN      (1 << 15)   // Auto detect interrupt
1537 #define EUARTUCR1_ADBR      (1 << 14)   // Auto detect baud rate
1538 #define EUARTUCR1_TRDYEN    (1 << 13)   // Transmitter ready interrupt enable
1539 #define EUARTUCR1_IDEN      (1 << 12)   // Idle condition interrupt
1540 #define EUARTUCR1_RRDYEN    (1 << 9)    // Recv ready interrupt enable
1541 #define EUARTUCR1_RDMAEN    (1 << 8)    // Recv ready DMA enable
1542 #define EUARTUCR1_IREN      (1 << 7)    // Infrared interface enable
1543 #define EUARTUCR1_TXMPTYEN  (1 << 6)    // Transimitter empt  interrupt enable
1544 #define EUARTUCR1_RTSDEN    (1 << 5)    // RTS delta interrupt enable
1545 #define EUARTUCR1_SNDBRK    (1 << 4)    // Send break
1546 #define EUARTUCR1_TDMAEN    (1 << 3)    // Transmitter ready DMA enable
1547 #define EUARTUCR1_DOZE      (1 << 1)    // Doze
1548 #define EUARTUCR1_UARTEN    (1 << 0)    // UART enabled
1549 #define EUARTUCR2_ESCI      (1 << 15)   // Escape seq interrupt enable
1550 #define EUARTUCR2_IRTS      (1 << 14)   // Ignore RTS pin
1551 #define EUARTUCR2_CTSC      (1 << 13)   // CTS pin control
1552 #define EUARTUCR2_CTS       (1 << 12)   // Clear to send
1553 #define EUARTUCR2_ESCEN     (1 << 11)   // Escape enable
1554 #define EUARTUCR2_PREN      (1 << 8)    // Parity enable
1555 #define EUARTUCR2_PROE      (1 << 7)    // Parity odd/even
1556 #define EUARTUCR2_STPB      (1 << 6)    // Stop
1557 #define EUARTUCR2_WS        (1 << 5)    // Word size
1558 #define EUARTUCR2_RTSEN     (1 << 4)    // Request to send interrupt enable
1559 #define EUARTUCR2_ATEN      (1 << 3)    // Aging timer enable
1560 #define EUARTUCR2_TXEN      (1 << 2)    // Transmitter enabled
1561 #define EUARTUCR2_RXEN      (1 << 1)    // Receiver enabled
1562 #define EUARTUCR2_SRST_     (1 << 0)    // SW reset
1563 #define EUARTUCR3_PARERREN  (1 << 12)   // Parity enable
1564 #define EUARTUCR3_FRAERREN  (1 << 11)   // Frame error interrupt enable
1565 #define EUARTUCR3_ADNIMP    (1 << 7)    // Autobaud detection not improved
1566 #define EUARTUCR3_RXDSEN    (1 << 6)    // Receive status interrupt  enable
1567 #define EUARTUCR3_AIRINTEN  (1 << 5)    // Async IR wake interrupt enable
1568 #define EUARTUCR3_AWAKEN    (1 << 4)    // Async wake interrupt enable
1569 #define EUARTUCR3_RXDMUXSEL (1 << 2)    // RXD muxed input selected
1570 #define EUARTUCR3_INVT      (1 << 1)    // Inverted Infrared transmission
1571 #define EUARTUCR3_ACIEN     (1 << 0)    // Autobaud counter interrupt  enable
1572 #define EUARTUCR4_CTSTL_32  (32 << 10)  // CTS trigger level (32 chars)
1573 #define EUARTUCR4_INVR      (1 << 9)    // Inverted infrared reception
1574 #define EUARTUCR4_ENIRI     (1 << 8)    // Serial infrared interrupt enable
1575 #define EUARTUCR4_WKEN      (1 << 7)    // Wake interrupt enable
1576 #define EUARTUCR4_IRSC      (1 << 5)    // IR special case
1577 #define EUARTUCR4_LPBYP     (1 << 4)    // Low power bypass
1578 #define EUARTUCR4_TCEN      (1 << 3)    // Transmit complete interrupt  enable
1579 #define EUARTUCR4_BKEN      (1 << 2)    // Break condition interrupt enable
1580 #define EUARTUCR4_OREN      (1 << 1)    // Receiver overrun interrupt enable
1581 #define EUARTUCR4_DREN      (1 << 0)    // Recv data ready interrupt enable
1582 #define EUARTUFCR_RXTL_SHF  0           // Receiver trigger level shift
1583 #define EUARTUFCR_RFDIV_1   (5 << 7)    // Reference freq divider (div> 1)
1584 #define EUARTUFCR_RFDIV_2   (4 << 7)    // Reference freq divider (div> 2)
1585 #define EUARTUFCR_RFDIV_3   (3 << 7)    // Reference freq  divider (div 3)
1586 #define EUARTUFCR_RFDIV_4   (2 << 7)    // Reference freq divider (div 4)
1587 #define EUARTUFCR_RFDIV_5   (1 << 7)    // Reference freq divider (div 5)
1588 #define EUARTUFCR_RFDIV_6   (0 << 7)    // Reference freq divider (div 6)
1589 #define EUARTUFCR_RFDIV_7   (6 << 7)    // Reference freq divider (div 7)
1590 #define EUARTUFCR_TXTL_SHF  10          // Transmitter trigger level shift
1591 #define EUARTUSR1_PARITYERR (1 << 15)   // Parity error interrupt flag
1592 #define EUARTUSR1_RTSS      (1 << 14)   // RTS pin status
1593 #define EUARTUSR1_TRDY      (1 << 13)   // Transmitter ready interrupt/dma flag
1594 #define EUARTUSR1_RTSD      (1 << 12)   // RTS delta
1595 #define EUARTUSR1_ESCF      (1 << 11)   // Escape seq interrupt flag
1596 #define EUARTUSR1_FRAMERR   (1 << 10)   // Frame error interrupt flag
1597 #define EUARTUSR1_RRDY      (1 << 9)    // Receiver ready  interrupt/dma flag
1598 #define EUARTUSR1_AGTIM     (1 << 8)    // Aging timeout interrupt status
1599 #define EUARTUSR1_RXDS      (1 << 6)    // Receiver idle interrupt flag
1600 #define EUARTUSR1_AIRINT    (1 << 5)    // Async IR wake interrupt flag
1601 #define EUARTUSR1_AWAKE     (1 << 4)    // Aysnc wake interrupt flag
1602 #define EUARTUSR2_ADET      (1 << 15)   // Auto baud rate detect  complete
1603 #define EUARTUSR2_TXFE      (1 << 14)   // Transmit buffer FIFO empty
1604 #define EUARTUSR2_IDLE      (1 << 12)   // Idle condition
1605 #define EUARTUSR2_ACST      (1 << 11)   // Autobaud counter stopped
1606 #define EUARTUSR2_IRINT     (1 << 8)    // Serial infrared interrupt flag
1607 #define EUARTUSR2_WAKE      (1 << 7)    // Wake
1608 #define EUARTUSR2_RTSF      (1 << 4)    // RTS edge interrupt flag
1609 #define EUARTUSR2_TXDC      (1 << 3)    // Transmitter complete
1610 #define EUARTUSR2_BRCD      (1 << 2)    // Break condition
1611 #define EUARTUSR2_ORE       (1 << 1)    // Overrun error
1612 #define EUARTUSR2_RDR       (1 << 0)    // Recv data ready
1613 #define EUARTUTS_FRCPERR    (1 << 13)   // Force parity error
1614 #define EUARTUTS_LOOP       (1 << 12)   // Loop tx and rx
1615 #define EUARTUTS_TXEMPTY    (1 << 6)    // TxFIFO empty
1616 #define EUARTUTS_RXEMPTY    (1 << 5)    // RxFIFO empty
1617 #define EUARTUTS_TXFULL     (1 << 4)    // TxFIFO full
1618 #define EUARTUTS_RXFULL     (1 << 3)    // RxFIFO full
1619 #define EUARTUTS_SOFTRST    (1 << 0)    // Software reset
1620
1621 #define L2CC_ENABLED
1622
1623 /* Assuming 26MHz input clock */
1624 /*                         PD          MFD           MFI          MFN */
1625 #define MPCTL_PARAM_208  ((1 << 26) + (0   << 16) + (8  << 10) + (0 << 0))
1626 #define MPCTL_PARAM_399  ((0 << 26) + (51  << 16) + (7  << 10) + (35 << 0))
1627 #define MPCTL_PARAM_532  ((0 << 26) + (51  << 16) + (10 << 10) + (12 << 0))
1628
1629 /* UPCTL                   PD             MFD              MFI          MFN */
1630 #define UPCTL_PARAM_288  (((1-1) << 26) + ((13-1) << 16) + (5  << 10) + (7  << 0))
1631 #define UPCTL_PARAM_240  (((2-1) << 26) + ((13-1) << 16) + (9  << 10) + (3  << 0))
1632
1633 /* PDR0 */
1634 #define PDR0_208_104_52     0xFF870D48  /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
1635 #define PDR0_399_66_66      0xFF872B28  /* ARM=399MHz, HCLK=IPG=66.5MHz */
1636 #define PDR0_399_133_66     0xFF871650  /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
1637 #define PDR0_532_133_66     0xFF871E58  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1638 #define PDR0_665_83_66      0xFF873D78  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1639 #define PDR0_665_133_66     0xFF872660  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1640
1641 #define PBC_BASE            CS4_BASE_ADDR    /* Peripheral Bus Controller */
1642
1643 #define PBC_BSTAT2                  0x2
1644 #define PBC_BCTRL1                  0x4
1645 #define PBC_BCTRL1_CLR              0x6
1646 #define PBC_BCTRL2                  0x8
1647 #define PBC_BCTRL2_CLR              0xA
1648 #define PBC_BCTRL3                  0xC
1649 #define PBC_BCTRL3_CLR              0xE
1650 #define PBC_BCTRL4                  0x10
1651 #define PBC_BCTRL4_CLR              0x12
1652 #define PBC_BSTAT1                  0x14
1653 #define MX31EVB_CS_LAN_BASE         (CS4_BASE_ADDR + 0x00020000 +  0x300)
1654 #define MX31EVB_CS_UART_BASE        (CS4_BASE_ADDR + 0x00010000)
1655
1656 #define REDBOOT_IMAGE_SIZE              0x40000
1657
1658 #define SDRAM_WORKAROUND_FULL_PAGE
1659
1660 #define ARMHIPG_208_52_52         /* ARM: 208MHz, HCLK=IPG=52MHz*/
1661 #define ARMHIPG_52_52_52          /* ARM: 52MHz, HCLK=IPG=52MHz*/
1662 #define ARMHIPG_399_66_66
1663 #define ARMHIPG_399_133_66
1664
1665 /* MX31 EVB SDRAM is from 0x80000000, 64M */
1666 #define SDRAM_BASE_ADDR                 CSD0_BASE_ADDR
1667 #define SDRAM_SIZE                      0x04000000
1668
1669 #define UART_WIDTH_32         /* internal UART is 32bit access only */
1670 #define EXT_UART_x16
1671
1672 #define UART_WIDTH_32         /* internal UART is 32bit access only */
1673
1674 #define FLASH_BURST_MODE_ENABLE 1
1675 #define SDRAM_COMPARE_CONST1    0x55555555
1676 #define SDRAM_COMPARE_CONST2    0xAAAAAAAA
1677 #define UART_FIFO_CTRL          0x881
1678 #define TIMEOUT                 1000
1679
1680 #endif /* __IMX31L_H__ */