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Fix endpoint allocation
[kugel-rb.git] / firmware / target / arm / usb-drv-arc.c
blob973a227423d1f5bd41f20728899a16fe5ba42e7a
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Driver for ARC USBOTG Device Controller
11 *
12 * Copyright (C) 2007 by Björn Stenberg
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version 2
17 * of the License, or (at your option) any later version.
18 *
19 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
20 * KIND, either express or implied.
21 *
22 ****************************************************************************/
23
24 #include "system.h"
25 #include "config.h"
26 #include "string.h"
27 #include "usb_ch9.h"
28 #include "usb_core.h"
29 #include "kernel.h"
30 #include "panic.h"
31 #include "usb_drv.h"
32
33 //#define LOGF_ENABLE
34 #include "logf.h"
35
36 /* USB device mode registers (Little Endian) */
37
38 #define REG_ID (*(volatile unsigned int *)(USB_BASE+0x000))
39 #define REG_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x004))
40 #define REG_HWHOST (*(volatile unsigned int *)(USB_BASE+0x008))
41 #define REG_HWDEVICE (*(volatile unsigned int *)(USB_BASE+0x00c))
42 #define REG_TXBUF (*(volatile unsigned int *)(USB_BASE+0x010))
43 #define REG_RXBUF (*(volatile unsigned int *)(USB_BASE+0x014))
44 #define REG_CAPLENGTH (*(volatile unsigned char*)(USB_BASE+0x100))
45 #define REG_DCIVERSION (*(volatile unsigned int *)(USB_BASE+0x120))
46 #define REG_DCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x124))
47 #define REG_USBCMD (*(volatile unsigned int *)(USB_BASE+0x140))
48 #define REG_USBSTS (*(volatile unsigned int *)(USB_BASE+0x144))
49 #define REG_USBINTR (*(volatile unsigned int *)(USB_BASE+0x148))
50 #define REG_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x14c))
51 #define REG_DEVICEADDR (*(volatile unsigned int *)(USB_BASE+0x154))
52 #define REG_ENDPOINTLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158))
53 #define REG_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x160))
54 #define REG_ULPI (*(volatile unsigned int *)(USB_BASE+0x170))
55 #define REG_CONFIGFLAG (*(volatile unsigned int *)(USB_BASE+0x180))
56 #define REG_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x184))
57 #define REG_OTGSC (*(volatile unsigned int *)(USB_BASE+0x1a4))
58 #define REG_USBMODE (*(volatile unsigned int *)(USB_BASE+0x1a8))
59 #define REG_ENDPTSETUPSTAT (*(volatile unsigned int *)(USB_BASE+0x1ac))
60 #define REG_ENDPTPRIME (*(volatile unsigned int *)(USB_BASE+0x1b0))
61 #define REG_ENDPTFLUSH (*(volatile unsigned int *)(USB_BASE+0x1b4))
62 #define REG_ENDPTSTATUS (*(volatile unsigned int *)(USB_BASE+0x1b8))
63 #define REG_ENDPTCOMPLETE (*(volatile unsigned int *)(USB_BASE+0x1bc))
64 #define REG_ENDPTCTRL0 (*(volatile unsigned int *)(USB_BASE+0x1c0))
65 #define REG_ENDPTCTRL1 (*(volatile unsigned int *)(USB_BASE+0x1c4))
66 #define REG_ENDPTCTRL2 (*(volatile unsigned int *)(USB_BASE+0x1c8))
67 #define REG_ENDPTCTRL(_x_) (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(_x_)))
68
69 /* Frame Index Register Bit Masks */
70 #define USB_FRINDEX_MASKS (0x3fff)
71
72 /* USB CMD Register Bit Masks */
73 #define USBCMD_RUN (0x00000001)
74 #define USBCMD_CTRL_RESET (0x00000002)
75 #define USBCMD_PERIODIC_SCHEDULE_EN (0x00000010)
76 #define USBCMD_ASYNC_SCHEDULE_EN (0x00000020)
77 #define USBCMD_INT_AA_DOORBELL (0x00000040)
78 #define USBCMD_ASP (0x00000300)
79 #define USBCMD_ASYNC_SCH_PARK_EN (0x00000800)
80 #define USBCMD_SUTW (0x00002000)
81 #define USBCMD_ATDTW (0x00004000)
82 #define USBCMD_ITC (0x00FF0000)
83
84 /* bit 15,3,2 are frame list size */
85 #define USBCMD_FRAME_SIZE_1024 (0x00000000)
86 #define USBCMD_FRAME_SIZE_512 (0x00000004)
87 #define USBCMD_FRAME_SIZE_256 (0x00000008)
88 #define USBCMD_FRAME_SIZE_128 (0x0000000C)
89 #define USBCMD_FRAME_SIZE_64 (0x00008000)
90 #define USBCMD_FRAME_SIZE_32 (0x00008004)
91 #define USBCMD_FRAME_SIZE_16 (0x00008008)
92 #define USBCMD_FRAME_SIZE_8 (0x0000800C)
93
94 /* bit 9-8 are async schedule park mode count */
95 #define USBCMD_ASP_00 (0x00000000)
96 #define USBCMD_ASP_01 (0x00000100)
97 #define USBCMD_ASP_10 (0x00000200)
98 #define USBCMD_ASP_11 (0x00000300)
99 #define USBCMD_ASP_BIT_POS (8)
100
101 /* bit 23-16 are interrupt threshold control */
102 #define USBCMD_ITC_NO_THRESHOLD (0x00000000)
103 #define USBCMD_ITC_1_MICRO_FRM (0x00010000)
104 #define USBCMD_ITC_2_MICRO_FRM (0x00020000)
105 #define USBCMD_ITC_4_MICRO_FRM (0x00040000)
106 #define USBCMD_ITC_8_MICRO_FRM (0x00080000)
107 #define USBCMD_ITC_16_MICRO_FRM (0x00100000)
108 #define USBCMD_ITC_32_MICRO_FRM (0x00200000)
109 #define USBCMD_ITC_64_MICRO_FRM (0x00400000)
110 #define USBCMD_ITC_BIT_POS (16)
111
112 /* USB STS Register Bit Masks */
113 #define USBSTS_INT (0x00000001)
114 #define USBSTS_ERR (0x00000002)
115 #define USBSTS_PORT_CHANGE (0x00000004)
116 #define USBSTS_FRM_LST_ROLL (0x00000008)
117 #define USBSTS_SYS_ERR (0x00000010) /* not used */
118 #define USBSTS_IAA (0x00000020)
119 #define USBSTS_RESET (0x00000040)
120 #define USBSTS_SOF (0x00000080)
121 #define USBSTS_SUSPEND (0x00000100)
122 #define USBSTS_HC_HALTED (0x00001000)
123 #define USBSTS_RCL (0x00002000)
124 #define USBSTS_PERIODIC_SCHEDULE (0x00004000)
125 #define USBSTS_ASYNC_SCHEDULE (0x00008000)
126
127 /* USB INTR Register Bit Masks */
128 #define USBINTR_INT_EN (0x00000001)
129 #define USBINTR_ERR_INT_EN (0x00000002)
130 #define USBINTR_PTC_DETECT_EN (0x00000004)
131 #define USBINTR_FRM_LST_ROLL_EN (0x00000008)
132 #define USBINTR_SYS_ERR_EN (0x00000010)
133 #define USBINTR_ASYN_ADV_EN (0x00000020)
134 #define USBINTR_RESET_EN (0x00000040)
135 #define USBINTR_SOF_EN (0x00000080)
136 #define USBINTR_DEVICE_SUSPEND (0x00000100)
137
138 /* ULPI Register Bit Masks */
139 #define ULPI_ULPIWU (0x80000000)
140 #define ULPI_ULPIRUN (0x40000000)
141 #define ULPI_ULPIRW (0x20000000)
142 #define ULPI_ULPISS (0x08000000)
143 #define ULPI_ULPIPORT (0x07000000)
144 #define ULPI_ULPIADDR (0x00FF0000)
145 #define ULPI_ULPIDATRD (0x0000FF00)
146 #define ULPI_ULPIDATWR (0x000000FF)
147
148 /* Device Address bit masks */
149 #define USBDEVICEADDRESS_MASK (0xFE000000)
150 #define USBDEVICEADDRESS_BIT_POS (25)
151
152 /* endpoint list address bit masks */
153 #define USB_EP_LIST_ADDRESS_MASK (0xfffff800)
154
155 /* PORTSCX Register Bit Masks */
156 #define PORTSCX_CURRENT_CONNECT_STATUS (0x00000001)
157 #define PORTSCX_CONNECT_STATUS_CHANGE (0x00000002)
158 #define PORTSCX_PORT_ENABLE (0x00000004)
159 #define PORTSCX_PORT_EN_DIS_CHANGE (0x00000008)
160 #define PORTSCX_OVER_CURRENT_ACT (0x00000010)
161 #define PORTSCX_OVER_CURRENT_CHG (0x00000020)
162 #define PORTSCX_PORT_FORCE_RESUME (0x00000040)
163 #define PORTSCX_PORT_SUSPEND (0x00000080)
164 #define PORTSCX_PORT_RESET (0x00000100)
165 #define PORTSCX_LINE_STATUS_BITS (0x00000C00)
166 #define PORTSCX_PORT_POWER (0x00001000)
167 #define PORTSCX_PORT_INDICTOR_CTRL (0x0000C000)
168 #define PORTSCX_PORT_TEST_CTRL (0x000F0000)
169 #define PORTSCX_WAKE_ON_CONNECT_EN (0x00100000)
170 #define PORTSCX_WAKE_ON_CONNECT_DIS (0x00200000)
171 #define PORTSCX_WAKE_ON_OVER_CURRENT (0x00400000)
172 #define PORTSCX_PHY_LOW_POWER_SPD (0x00800000)
173 #define PORTSCX_PORT_FORCE_FULL_SPEED (0x01000000)
174 #define PORTSCX_PORT_SPEED_MASK (0x0C000000)
175 #define PORTSCX_PORT_WIDTH (0x10000000)
176 #define PORTSCX_PHY_TYPE_SEL (0xC0000000)
177
178 /* bit 11-10 are line status */
179 #define PORTSCX_LINE_STATUS_SE0 (0x00000000)
180 #define PORTSCX_LINE_STATUS_JSTATE (0x00000400)
181 #define PORTSCX_LINE_STATUS_KSTATE (0x00000800)
182 #define PORTSCX_LINE_STATUS_UNDEF (0x00000C00)
183 #define PORTSCX_LINE_STATUS_BIT_POS (10)
184
185 /* bit 15-14 are port indicator control */
186 #define PORTSCX_PIC_OFF (0x00000000)
187 #define PORTSCX_PIC_AMBER (0x00004000)
188 #define PORTSCX_PIC_GREEN (0x00008000)
189 #define PORTSCX_PIC_UNDEF (0x0000C000)
190 #define PORTSCX_PIC_BIT_POS (14)
191
192 /* bit 19-16 are port test control */
193 #define PORTSCX_PTC_DISABLE (0x00000000)
194 #define PORTSCX_PTC_JSTATE (0x00010000)
195 #define PORTSCX_PTC_KSTATE (0x00020000)
196 #define PORTSCX_PTC_SE0NAK (0x00030000)
197 #define PORTSCX_PTC_PACKET (0x00040000)
198 #define PORTSCX_PTC_FORCE_EN (0x00050000)
199 #define PORTSCX_PTC_BIT_POS (16)
200
201 /* bit 27-26 are port speed */
202 #define PORTSCX_PORT_SPEED_FULL (0x00000000)
203 #define PORTSCX_PORT_SPEED_LOW (0x04000000)
204 #define PORTSCX_PORT_SPEED_HIGH (0x08000000)
205 #define PORTSCX_PORT_SPEED_UNDEF (0x0C000000)
206 #define PORTSCX_SPEED_BIT_POS (26)
207
208 /* bit 28 is parallel transceiver width for UTMI interface */
209 #define PORTSCX_PTW (0x10000000)
210 #define PORTSCX_PTW_8BIT (0x00000000)
211 #define PORTSCX_PTW_16BIT (0x10000000)
212
213 /* bit 31-30 are port transceiver select */
214 #define PORTSCX_PTS_UTMI (0x00000000)
215 #define PORTSCX_PTS_CLASSIC (0x40000000)
216 #define PORTSCX_PTS_ULPI (0x80000000)
217 #define PORTSCX_PTS_FSLS (0xC0000000)
218 #define PORTSCX_PTS_BIT_POS (30)
219
220 /* USB MODE Register Bit Masks */
221 #define USBMODE_CTRL_MODE_IDLE (0x00000000)
222 #define USBMODE_CTRL_MODE_DEVICE (0x00000002)
223 #define USBMODE_CTRL_MODE_HOST (0x00000003)
224 #define USBMODE_CTRL_MODE_RSV (0x00000001)
225 #define USBMODE_SETUP_LOCK_OFF (0x00000008)
226 #define USBMODE_STREAM_DISABLE (0x00000010)
227
228 /* Endpoint Flush Register */
229 #define EPFLUSH_TX_OFFSET (0x00010000)
230 #define EPFLUSH_RX_OFFSET (0x00000000)
231
232 /* Endpoint Setup Status bit masks */
233 #define EPSETUP_STATUS_MASK (0x0000003F)
234 #define EPSETUP_STATUS_EP0 (0x00000001)
235
236 /* ENDPOINTCTRLx Register Bit Masks */
237 #define EPCTRL_TX_ENABLE (0x00800000)
238 #define EPCTRL_TX_DATA_TOGGLE_RST (0x00400000) /* Not EP0 */
239 #define EPCTRL_TX_DATA_TOGGLE_INH (0x00200000) /* Not EP0 */
240 #define EPCTRL_TX_TYPE (0x000C0000)
241 #define EPCTRL_TX_DATA_SOURCE (0x00020000) /* Not EP0 */
242 #define EPCTRL_TX_EP_STALL (0x00010000)
243 #define EPCTRL_RX_ENABLE (0x00000080)
244 #define EPCTRL_RX_DATA_TOGGLE_RST (0x00000040) /* Not EP0 */
245 #define EPCTRL_RX_DATA_TOGGLE_INH (0x00000020) /* Not EP0 */
246 #define EPCTRL_RX_TYPE (0x0000000C)
247 #define EPCTRL_RX_DATA_SINK (0x00000002) /* Not EP0 */
248 #define EPCTRL_RX_EP_STALL (0x00000001)
249
250 /* bit 19-18 and 3-2 are endpoint type */
251 #define EPCTRL_TX_EP_TYPE_SHIFT (18)
252 #define EPCTRL_RX_EP_TYPE_SHIFT (2)
253
254 /* pri_ctrl Register Bit Masks */
255 #define PRI_CTRL_PRI_LVL1 (0x0000000C)
256 #define PRI_CTRL_PRI_LVL0 (0x00000003)
257
258 /* si_ctrl Register Bit Masks */
259 #define SI_CTRL_ERR_DISABLE (0x00000010)
260 #define SI_CTRL_IDRC_DISABLE (0x00000008)
261 #define SI_CTRL_RD_SAFE_EN (0x00000004)
262 #define SI_CTRL_RD_PREFETCH_DISABLE (0x00000002)
263 #define SI_CTRL_RD_PREFEFETCH_VAL (0x00000001)
264
265 /* control Register Bit Masks */
266 #define USB_CTRL_IOENB (0x00000004)
267 #define USB_CTRL_ULPI_INT0EN (0x00000001)
268
269 /* OTGSC Register Bit Masks */
270 #define OTGSC_B_SESSION_VALID (0x00000800)
271 #define OTGSC_A_VBUS_VALID (0x00000200)
272
273 #define QH_MULT_POS (30)
274 #define QH_ZLT_SEL (0x20000000)
275 #define QH_MAX_PKT_LEN_POS (16)
276 #define QH_IOS (0x00008000)
277 #define QH_NEXT_TERMINATE (0x00000001)
278 #define QH_IOC (0x00008000)
279 #define QH_MULTO (0x00000C00)
280 #define QH_STATUS_HALT (0x00000040)
281 #define QH_STATUS_ACTIVE (0x00000080)
282 #define EP_QUEUE_CURRENT_OFFSET_MASK (0x00000FFF)
283 #define EP_QUEUE_HEAD_NEXT_POINTER_MASK (0xFFFFFFE0)
284 #define EP_QUEUE_FRINDEX_MASK (0x000007FF)
285 #define EP_MAX_LENGTH_TRANSFER (0x4000)
286
287 #define DTD_NEXT_TERMINATE (0x00000001)
288 #define DTD_IOC (0x00008000)
289 #define DTD_STATUS_ACTIVE (0x00000080)
290 #define DTD_STATUS_HALTED (0x00000040)
291 #define DTD_STATUS_DATA_BUFF_ERR (0x00000020)
292 #define DTD_STATUS_TRANSACTION_ERR (0x00000008)
293 #define DTD_RESERVED_FIELDS (0x80007300)
294 #define DTD_ADDR_MASK (0xFFFFFFE0)
295 #define DTD_PACKET_SIZE (0x7FFF0000)
296 #define DTD_LENGTH_BIT_POS (16)
297 #define DTD_ERROR_MASK (DTD_STATUS_HALTED | \
298 DTD_STATUS_DATA_BUFF_ERR | \
299 DTD_STATUS_TRANSACTION_ERR)
300
301 #define DTD_RESERVED_LENGTH_MASK 0x0001ffff
302 #define DTD_RESERVED_IN_USE 0x80000000
303 #define DTD_RESERVED_PIPE_MASK 0x0ff00000
304 #define DTD_RESERVED_PIPE_OFFSET 20
305 /*-------------------------------------------------------------------------*/
306
307 /* 4 transfer descriptors per endpoint allow 64k transfers, which is the usual MSC
308 transfer size, so it seems like a good size */
309 #define NUM_TDS_PER_EP 4
310
311 typedef struct usb_endpoint
312 {
313 bool allocated[2];
314 short type[2];
315 short max_pkt_size[2];
316 } usb_endpoint_t;
317 static usb_endpoint_t endpoints[USB_NUM_ENDPOINTS];
318
319 /* manual: 32.13.2 Endpoint Transfer Descriptor (dTD) */
320 struct transfer_descriptor {
321 unsigned int next_td_ptr; /* Next TD pointer(31-5), T(0) set
322 indicate invalid */
323 unsigned int size_ioc_sts; /* Total bytes (30-16), IOC (15),
324 MultO(11-10), STS (7-0) */
325 unsigned int buff_ptr0; /* Buffer pointer Page 0 */
326 unsigned int buff_ptr1; /* Buffer pointer Page 1 */
327 unsigned int buff_ptr2; /* Buffer pointer Page 2 */
328 unsigned int buff_ptr3; /* Buffer pointer Page 3 */
329 unsigned int buff_ptr4; /* Buffer pointer Page 4 */
330 unsigned int reserved;
331 } __attribute__ ((packed));
332
333 static struct transfer_descriptor td_array[USB_NUM_ENDPOINTS*2*NUM_TDS_PER_EP]
334 USB_DEVBSS_ATTR __attribute__((aligned(32)));
335
336 /* manual: 32.13.1 Endpoint Queue Head (dQH) */
337 struct queue_head {
338 unsigned int max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len
339 and IOS(15) */
340 unsigned int curr_dtd_ptr; /* Current dTD Pointer(31-5) */
341 struct transfer_descriptor dtd; /* dTD overlay */
342 unsigned int setup_buffer[2]; /* Setup data 8 bytes */
343 unsigned int reserved; /* for software use, pointer to the first TD */
344 unsigned int status; /* for software use, status of chain in progress */
345 unsigned int length; /* for software use, transfered bytes of chain in progress */
346 unsigned int wait; /* for softwate use, indicates if the transfer is blocking */
347 } __attribute__((packed));
348
349 static struct queue_head qh_array[USB_NUM_ENDPOINTS*2]
350 USB_QHARRAY_ATTR;
351
352 static struct wakeup transfer_completion_signal[USB_NUM_ENDPOINTS*2]
353 SHAREDBSS_ATTR;
354
355 static const unsigned int pipe2mask[] = {
356 0x01, 0x010000,
357 0x02, 0x020000,
358 0x04, 0x040000,
359 0x08, 0x080000,
360 0x10, 0x100000,
361 };
362
363 /*-------------------------------------------------------------------------*/
364 static void transfer_completed(void);
365 static void control_received(void);
366 static int prime_transfer(int ep_num, void* ptr, int len, bool send, bool wait);
367 static void prepare_td(struct transfer_descriptor* td,
368 struct transfer_descriptor* previous_td, void *ptr, int len,int pipe);
369 static void bus_reset(void);
370 static void init_control_queue_heads(void);
371 static void init_bulk_queue_heads(void);
372 static void init_endpoints(void);
373 /*-------------------------------------------------------------------------*/
374 static void usb_drv_stop(void)
375 {
376 /* disable interrupts */
377 REG_USBINTR = 0;
378 /* stop usb controller (disconnect) */
379 REG_USBCMD &= ~USBCMD_RUN;
380 }
381
382 void usb_drv_reset(void)
383 {
384 int oldlevel = disable_irq_save();
385 REG_USBCMD &= ~USBCMD_RUN;
386 restore_irq(oldlevel);
387
388 #ifdef USB_PORTSCX_PHY_TYPE
389 /* If a PHY type is specified, set it now */
390 REG_PORTSC1 = (REG_PORTSC1 & ~PORTSCX_PHY_TYPE_SEL) | USB_PORTSCX_PHY_TYPE;
391 #endif
392 sleep(HZ/20);
393 REG_USBCMD |= USBCMD_CTRL_RESET;
394 while (REG_USBCMD & USBCMD_CTRL_RESET);
395
396 #if CONFIG_CPU == PP5022 || CONFIG_CPU == PP5024
397 /* On a CPU which identifies as a PP5022, this
398 initialization must be done after USB is reset.
399 */
400 outl(inl(0x70000060) | 0xF, 0x70000060);
401 outl(inl(0x70000028) | 0x10000, 0x70000028);
402 outl(inl(0x70000028) & ~0x10000, 0x70000028);
403 outl(inl(0x70000060) & ~0x20, 0x70000060);
404 udelay(10);
405 outl(inl(0x70000060) | 0x20, 0x70000060);
406 udelay(10);
407 outl((inl(0x70000060) & ~0xF) | 4, 0x70000060);
408 udelay(10);
409 outl(inl(0x70000060) & ~0x20, 0x70000060);
410 udelay(10);
411 outl(inl(0x70000060) & ~0xF, 0x70000060);
412 udelay(10);
413 outl(inl(0x70000060) | 0x20, 0x70000060);
414 udelay(10);
415 outl(inl(0x70000028) | 0x800, 0x70000028);
416 outl(inl(0x70000028) & ~0x800, 0x70000028);
417 while ((inl(0x70000028) & 0x80) == 0);
418 #endif
419 }
420
421 /* One-time driver startup init */
422 void usb_drv_startup(void)
423 {
424 /* Initialize all the signal objects once */
425 int i;
426 for(i=0;i<USB_NUM_ENDPOINTS*2;i++) {
427 wakeup_init(&transfer_completion_signal[i]);
428 }
429 }
430
431 /* manual: 32.14.1 Device Controller Initialization */
432 static void _usb_drv_init(bool attach)
433 {
434 usb_drv_reset();
435
436 REG_USBMODE = USBMODE_CTRL_MODE_DEVICE;
437
438 #ifdef USB_NO_HIGH_SPEED
439 /* Force device to full speed */
440 /* See 32.9.5.9.2 */
441 REG_PORTSC1 |= PORTSCX_PORT_FORCE_FULL_SPEED;
442 #endif
443
444 init_control_queue_heads();
445 memset(td_array, 0, sizeof td_array);
446
447 REG_ENDPOINTLISTADDR = (unsigned int)qh_array;
448 REG_DEVICEADDR = 0;
449
450 if (!attach) {
451 /* enable RESET interrupt */
452 REG_USBINTR = USBINTR_RESET_EN;
453 }
454 else
455 {
456 /* enable USB interrupts */
457 REG_USBINTR =
458 USBINTR_INT_EN |
459 USBINTR_ERR_INT_EN |
460 USBINTR_PTC_DETECT_EN |
461 USBINTR_RESET_EN;
462 }
463
464 usb_drv_int_enable(true);
465
466 /* go go go */
467 REG_USBCMD |= USBCMD_RUN;
468
469 logf("usb_drv_init() finished");
470 logf("usb id %x", REG_ID);
471 logf("usb dciversion %x", REG_DCIVERSION);
472 logf("usb dccparams %x", REG_DCCPARAMS);
473
474 /* now a bus reset will occur. see bus_reset() */
475 (void)attach;
476 }
477
478 #ifdef LOGF_ENABLE
479 #define XFER_DIR_STR(dir) ((dir) ? "IN" : "OUT")
480 #define XFER_TYPE_STR(type) \
481 ((type) == USB_ENDPOINT_XFER_CONTROL ? "CTRL" : \
482 ((type) == USB_ENDPOINT_XFER_ISOC ? "ISOC" : \
483 ((type) == USB_ENDPOINT_XFER_BULK ? "BULK" : \
484 ((type) == USB_ENDPOINT_XFER_INT ? "INTR" : "INVL"))))
485
486 static void log_ep(int ep_num, int ep_dir, char* prefix)
487 {
488 usb_endpoint_t* endpoint = &endpoints[ep_num];
489
490 logf("%s: ep%d %s %s %d", prefix, ep_num, XFER_DIR_STR(ep_dir),
491 XFER_TYPE_STR(endpoint->type[ep_dir]),
492 endpoint->max_pkt_size[ep_dir]);
493 }
494 #else
495 #undef log_ep
496 #define log_ep(...)
497 #endif
498
499 void usb_drv_init(void)
500 {
501 _usb_drv_init(false);
502 }
503
504 /* fully enable driver */
505 void usb_drv_attach(void)
506 {
507 logf("usb_drv_attach");
508 sleep(HZ/10);
509 _usb_drv_init(true);
510 }
511
512 void usb_drv_exit(void)
513 {
514 usb_drv_stop();
515
516 /* TODO : is one of these needed to save power ?
517 REG_PORTSC1 |= PORTSCX_PHY_LOW_POWER_SPD;
518 REG_USBCMD |= USBCMD_CTRL_RESET;
519 */
520
521 usb_drv_int_enable(false);
522 }
523
524 void usb_drv_int(void)
525 {
526 unsigned int usbintr = REG_USBINTR; /* Only watch enabled ints */
527 unsigned int status = REG_USBSTS & usbintr;
528
529 #if 0
530 if (status & USBSTS_INT) logf("int: usb ioc");
531 if (status & USBSTS_ERR) logf("int: usb err");
532 if (status & USBSTS_PORT_CHANGE) logf("int: portchange");
533 if (status & USBSTS_RESET) logf("int: reset");
534 #endif
535
536 /* usb transaction interrupt */
537 if (status & USBSTS_INT) {
538 REG_USBSTS = USBSTS_INT;
539
540 /* a control packet? */
541 if (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0) {
542 control_received();
543 }
544
545 if (REG_ENDPTCOMPLETE)
546 transfer_completed();
547 }
548
549 /* error interrupt */
550 if (status & USBSTS_ERR) {
551 REG_USBSTS = USBSTS_ERR;
552 logf("usb error int");
553 }
554
555 /* reset interrupt */
556 if (status & USBSTS_RESET) {
557 REG_USBSTS = USBSTS_RESET;
558
559 if (UNLIKELY(usbintr == USBINTR_RESET_EN)) {
560 /* USB detected - detach and inform */
561 usb_drv_stop();
562 usb_drv_usb_detect_event();
563 }
564 else
565 {
566 bus_reset();
567 usb_core_bus_reset(); /* tell mom */
568 }
569 }
570
571 /* port change */
572 if (status & USBSTS_PORT_CHANGE) {
573 REG_USBSTS = USBSTS_PORT_CHANGE;
574 }
575 }
576
577 bool usb_drv_stalled(int endpoint,bool in)
578 {
579 if(in) {
580 return ((REG_ENDPTCTRL(EP_NUM(endpoint)) & EPCTRL_TX_EP_STALL)!=0);
581 }
582 else {
583 return ((REG_ENDPTCTRL(EP_NUM(endpoint)) & EPCTRL_RX_EP_STALL)!=0);
584 }
585
586 }
587 void usb_drv_stall(int endpoint, bool stall, bool in)
588 {
589 int ep_num = EP_NUM(endpoint);
590
591 logf("%sstall %d", stall ? "" : "un", ep_num);
592
593 if(in) {
594 if (stall) {
595 REG_ENDPTCTRL(ep_num) |= EPCTRL_TX_EP_STALL;
596 }
597 else {
598 REG_ENDPTCTRL(ep_num) &= ~EPCTRL_TX_EP_STALL;
599 }
600 }
601 else {
602 if (stall) {
603 REG_ENDPTCTRL(ep_num) |= EPCTRL_RX_EP_STALL;
604 }
605 else {
606 REG_ENDPTCTRL(ep_num) &= ~EPCTRL_RX_EP_STALL;
607 }
608 }
609 }
610
611 int usb_drv_send_nonblocking(int endpoint, void* ptr, int length)
612 {
613 return prime_transfer(EP_NUM(endpoint), ptr, length, true, false);
614 }
615
616 int usb_drv_send(int endpoint, void* ptr, int length)
617 {
618 return prime_transfer(EP_NUM(endpoint), ptr, length, true, true);
619 }
620
621 int usb_drv_recv(int endpoint, void* ptr, int length)
622 {
623 //logf("usbrecv(%x, %d)", ptr, length);
624 return prime_transfer(EP_NUM(endpoint), ptr, length, false, false);
625 }
626
627 int usb_drv_port_speed(void)
628 {
629 return (REG_PORTSC1 & 0x08000000) ? 1 : 0;
630 }
631
632 bool usb_drv_connected(void)
633 {
634 return (REG_PORTSC1 &
635 (PORTSCX_PORT_SUSPEND | PORTSCX_CURRENT_CONNECT_STATUS))
636 == PORTSCX_CURRENT_CONNECT_STATUS;
637 }
638
639 bool usb_drv_powered(void)
640 {
641 /* true = bus 4V4 ok */
642 return (REG_OTGSC & OTGSC_A_VBUS_VALID) ? true : false;
643 }
644
645 void usb_drv_set_address(int address)
646 {
647 REG_DEVICEADDR = address << USBDEVICEADDRESS_BIT_POS;
648 init_bulk_queue_heads();
649 init_endpoints();
650 }
651
652 void usb_drv_reset_endpoint(int endpoint, bool send)
653 {
654 int pipe = EP_NUM(endpoint) * 2 + (send ? 1 : 0);
655 unsigned int mask = pipe2mask[pipe];
656 REG_ENDPTFLUSH = mask;
657 while (REG_ENDPTFLUSH & mask);
658 }
659
660 void usb_drv_set_test_mode(int mode)
661 {
662 switch(mode){
663 case 0:
664 REG_PORTSC1 &= ~PORTSCX_PORT_TEST_CTRL;
665 break;
666 case 1:
667 REG_PORTSC1 |= PORTSCX_PTC_JSTATE;
668 break;
669 case 2:
670 REG_PORTSC1 |= PORTSCX_PTC_KSTATE;
671 break;
672 case 3:
673 REG_PORTSC1 |= PORTSCX_PTC_SE0NAK;
674 break;
675 case 4:
676 REG_PORTSC1 |= PORTSCX_PTC_PACKET;
677 break;
678 case 5:
679 REG_PORTSC1 |= PORTSCX_PTC_FORCE_EN;
680 break;
681 }
682 usb_drv_reset();
683 REG_USBCMD |= USBCMD_RUN;
684 }
685
686 /*-------------------------------------------------------------------------*/
687
688 /* manual: 32.14.5.2 */
689 static int prime_transfer(int ep_num, void* ptr, int len, bool send, bool wait)
690 {
691 int rc = 0;
692 int pipe = ep_num * 2 + (send ? 1 : 0);
693 unsigned int mask = pipe2mask[pipe];
694 struct queue_head* qh = &qh_array[pipe];
695 static long last_tick;
696 struct transfer_descriptor *new_td, *cur_td, *prev_td;
697
698 int oldlevel = disable_irq_save();
699 /*
700 if (send && ep_num > EP_CONTROL) {
701 logf("usb: sent %d bytes", len);
702 }
703 */
704 qh->status = 0;
705 qh->wait = wait;
706
707 new_td=&td_array[pipe*NUM_TDS_PER_EP];
708 cur_td=new_td;
709 prev_td=0;
710 int tdlen;
711
712 do
713 {
714 tdlen=MIN(len,16384);
715 prepare_td(cur_td, prev_td, ptr, tdlen,pipe);
716 ptr+=tdlen;
717 prev_td=cur_td;
718 cur_td++;
719 len-=tdlen;
720 }
721 while(len>0);
722 //logf("starting ep %d %s",ep_num,send?"send":"receive");
723
724 qh->dtd.next_td_ptr = (unsigned int)new_td;
725 qh->dtd.size_ioc_sts &= ~(QH_STATUS_HALT | QH_STATUS_ACTIVE);
726
727 REG_ENDPTPRIME |= mask;
728
729 if(ep_num == EP_CONTROL && (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0)) {
730 /* 32.14.3.2.2 */
731 logf("new setup arrived");
732 rc = -4;
733 goto pt_error;
734 }
735
736 last_tick = current_tick;
737 while ((REG_ENDPTPRIME & mask)) {
738 if (REG_USBSTS & USBSTS_RESET) {
739 rc = -1;
740 goto pt_error;
741 }
742
743 if (TIME_AFTER(current_tick, last_tick + HZ/4)) {
744 logf("prime timeout");
745 rc = -2;
746 goto pt_error;
747 }
748 }
749
750 if (!(REG_ENDPTSTATUS & mask)) {
751 logf("no prime! %d %d %x", ep_num, pipe, qh->dtd.size_ioc_sts & 0xff);
752 rc = -3;
753 goto pt_error;
754 }
755 if(ep_num == EP_CONTROL && (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0)) {
756 /* 32.14.3.2.2 */
757 logf("new setup arrived");
758 rc = -4;
759 goto pt_error;
760 }
761
762 restore_irq(oldlevel);
763
764 if (wait) {
765 /* wait for transfer to finish */
766 wakeup_wait(&transfer_completion_signal[pipe], TIMEOUT_BLOCK);
767 if(qh->status!=0) {
768 /* No need to cancel wait here since it was done and the signal
769 * came. */
770 return -5;
771 }
772 //logf("all tds done");
773 }
774
775 pt_error:
776 if(rc<0)
777 restore_irq(oldlevel);
778
779 /* Error status must make sure an abandoned wakeup signal isn't left */
780 if (rc < 0 && wait) {
781 /* Cancel wait */
782 qh->wait = 0;
783 /* Make sure to remove any signal if interrupt fired before we zeroed
784 * qh->wait. Could happen during a bus reset for example. */
785 wakeup_wait(&transfer_completion_signal[pipe], TIMEOUT_NOBLOCK);
786 }
787
788 return rc;
789 }
790
791 void usb_drv_cancel_all_transfers(void)
792 {
793 int i;
794 REG_ENDPTFLUSH = ~0;
795 while (REG_ENDPTFLUSH);
796
797 memset(td_array, 0, sizeof td_array);
798 for(i=0;i<USB_NUM_ENDPOINTS*2;i++) {
799 if(qh_array[i].wait) {
800 qh_array[i].wait=0;
801 qh_array[i].status=DTD_STATUS_HALTED;
802 wakeup_signal(&transfer_completion_signal[i]);
803 }
804 }
805 }
806
807 int usb_drv_request_endpoint(int type, int dir)
808 {
809 int ep_num, ep_dir;
810 short ep_type;
811
812 /* Safety */
813 ep_dir = EP_DIR(dir);
814 ep_type = type & USB_ENDPOINT_XFERTYPE_MASK;
815
816 logf("req: %s %s", XFER_DIR_STR(ep_dir), XFER_TYPE_STR(ep_type));
817
818 /* Find an available ep/dir pair */
819 for (ep_num=1;ep_num<USB_NUM_ENDPOINTS;ep_num++) {
820 usb_endpoint_t* endpoint=&endpoints[ep_num];
821 int other_dir=(ep_dir ? 0:1);
822
823 if (endpoint->allocated[ep_dir])
824 continue;
825
826 if (endpoint->allocated[other_dir] &&
827 endpoint->type[other_dir] != ep_type) {
828 logf("ep of different type!");
829 continue;
830 }
831
832
833 endpoint->allocated[ep_dir] = 1;
834 endpoint->type[ep_dir] = ep_type;
835
836 log_ep(ep_num, ep_dir, "add");
837 return (ep_num | (dir & USB_ENDPOINT_DIR_MASK));
838 }
839
840 return -1;
841 }
842
843 void usb_drv_release_endpoint(int ep)
844 {
845 int ep_num = EP_NUM(ep);
846 int ep_dir = EP_DIR(ep);
847
848 log_ep(ep_num, ep_dir, "rel");
849 endpoints[ep_num].allocated[ep_dir] = 0;
850 }
851
852
853 static void prepare_td(struct transfer_descriptor* td,
854 struct transfer_descriptor* previous_td,
855 void *ptr, int len,int pipe)
856 {
857 //logf("adding a td : %d",len);
858 memset(td, 0, sizeof(struct transfer_descriptor));
859 td->next_td_ptr = DTD_NEXT_TERMINATE;
860 td->size_ioc_sts = (len<< DTD_LENGTH_BIT_POS) |
861 DTD_STATUS_ACTIVE | DTD_IOC;
862 td->buff_ptr0 = (unsigned int)ptr;
863 td->buff_ptr1 = ((unsigned int)ptr & 0xfffff000) + 0x1000;
864 td->buff_ptr2 = ((unsigned int)ptr & 0xfffff000) + 0x2000;
865 td->buff_ptr3 = ((unsigned int)ptr & 0xfffff000) + 0x3000;
866 td->buff_ptr4 = ((unsigned int)ptr & 0xfffff000) + 0x4000;
867 td->reserved |= DTD_RESERVED_LENGTH_MASK & len;
868 td->reserved |= DTD_RESERVED_IN_USE;
869 td->reserved |= (pipe << DTD_RESERVED_PIPE_OFFSET);
870
871 if (previous_td != 0) {
872 previous_td->next_td_ptr=(unsigned int)td;
873 previous_td->size_ioc_sts&=~DTD_IOC;
874 }
875 }
876
877 static void control_received(void)
878 {
879 int i;
880 /* copy setup data from packet */
881 static unsigned int tmp[2];
882 tmp[0] = qh_array[0].setup_buffer[0];
883 tmp[1] = qh_array[0].setup_buffer[1];
884
885 /* acknowledge packet recieved */
886 REG_ENDPTSETUPSTAT = EPSETUP_STATUS_EP0;
887
888 /* Stop pending control transfers */
889 for(i=0;i<2;i++) {
890 if(qh_array[i].wait) {
891 qh_array[i].wait=0;
892 qh_array[i].status=DTD_STATUS_HALTED;
893 wakeup_signal(&transfer_completion_signal[i]);
894 }
895 }
896
897 usb_core_control_request((struct usb_ctrlrequest*)tmp);
898 }
899
900 static void transfer_completed(void)
901 {
902 int ep;
903 unsigned int mask = REG_ENDPTCOMPLETE;
904 REG_ENDPTCOMPLETE = mask;
905
906 for (ep=0; ep<USB_NUM_ENDPOINTS; ep++) {
907 int dir;
908 for (dir=0; dir<2; dir++) {
909 int pipe = ep * 2 + dir;
910 if (mask & pipe2mask[pipe]) {
911 struct queue_head* qh = &qh_array[pipe];
912 if(qh->wait) {
913 qh->wait=0;
914 wakeup_signal(&transfer_completion_signal[pipe]);
915 }
916 int length=0;
917 struct transfer_descriptor* td=&td_array[pipe*NUM_TDS_PER_EP];
918 while(td!=(struct transfer_descriptor*)DTD_NEXT_TERMINATE && td!=0)
919 {
920 length += ((td->reserved & DTD_RESERVED_LENGTH_MASK) -
921 ((td->size_ioc_sts & DTD_PACKET_SIZE) >> DTD_LENGTH_BIT_POS));
922 td=(struct transfer_descriptor*) td->next_td_ptr;
923 }
924 usb_core_transfer_complete(ep, dir?USB_DIR_IN:USB_DIR_OUT,
925 qh->status, length);
926 }
927 }
928 }
929 }
930
931 /* manual: 32.14.2.1 Bus Reset */
932 static void bus_reset(void)
933 {
934 int i;
935 logf("usb bus_reset");
936
937 REG_DEVICEADDR = 0;
938 REG_ENDPTSETUPSTAT = REG_ENDPTSETUPSTAT;
939 REG_ENDPTCOMPLETE = REG_ENDPTCOMPLETE;
940
941 for (i=0; i<100; i++) {
942 if (!REG_ENDPTPRIME)
943 break;
944
945 if (REG_USBSTS & USBSTS_RESET) {
946 logf("usb: double reset");
947 return;
948 }
949
950 udelay(100);
951 }
952 if (REG_ENDPTPRIME) {
953 logf("usb: short reset timeout");
954 }
955
956 usb_drv_cancel_all_transfers();
957
958 if (!(REG_PORTSC1 & PORTSCX_PORT_RESET)) {
959 logf("usb: slow reset!");
960 }
961 }
962
963 /* manual: 32.14.4.1 Queue Head Initialization */
964 static void init_control_queue_heads(void)
965 {
966 memset(qh_array, 0, sizeof qh_array);
967
968 /*** control ***/
969 qh_array[EP_CONTROL].max_pkt_length = 64 << QH_MAX_PKT_LEN_POS | QH_IOS;
970 qh_array[EP_CONTROL].dtd.next_td_ptr = QH_NEXT_TERMINATE;
971 qh_array[EP_CONTROL+1].max_pkt_length = 64 << QH_MAX_PKT_LEN_POS;
972 qh_array[EP_CONTROL+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
973 }
974 /* manual: 32.14.4.1 Queue Head Initialization */
975 static void init_bulk_queue_heads(void)
976 {
977 int packetsize = (usb_drv_port_speed() ? 512 : 64);
978 int i;
979
980 /* TODO: this should take ep_allocation into account */
981 for (i=1;i<USB_NUM_ENDPOINTS;i++) {
982 qh_array[i*2].max_pkt_length = packetsize << QH_MAX_PKT_LEN_POS |
983 QH_ZLT_SEL;
984 qh_array[i*2].dtd.next_td_ptr = QH_NEXT_TERMINATE;
985 qh_array[i*2+1].max_pkt_length = packetsize << QH_MAX_PKT_LEN_POS |
986 QH_ZLT_SEL;
987 qh_array[i*2+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
988 }
989 }
990
991 static void init_endpoints(void)
992 {
993 int ep_num;
994
995 logf("init_endpoints");
996 /* RX/TX from the device POV: OUT/IN, respectively */
997 for(ep_num=1;ep_num<USB_NUM_ENDPOINTS;ep_num++) {
998 usb_endpoint_t *endpoint = &endpoints[ep_num];
999
1000 /* manual: 32.9.5.18 (Caution): Leaving an unconfigured endpoint control
1001 * will cause undefined behavior for the data pid tracking on the active
1002 * endpoint/direction. */
1003 if (!endpoint->allocated[DIR_OUT])
1004 endpoint->type[DIR_OUT] = USB_ENDPOINT_XFER_BULK;
1005 if (!endpoint->allocated[DIR_IN])
1006 endpoint->type[DIR_IN] = USB_ENDPOINT_XFER_BULK;
1007
1008 REG_ENDPTCTRL(ep_num) =
1009 EPCTRL_RX_DATA_TOGGLE_RST | EPCTRL_RX_ENABLE |
1010 EPCTRL_TX_DATA_TOGGLE_RST | EPCTRL_TX_ENABLE |
1011 (endpoint->type[DIR_OUT] << EPCTRL_RX_EP_TYPE_SHIFT) |
1012 (endpoint->type[DIR_IN] << EPCTRL_TX_EP_TYPE_SHIFT);
1013 }
1014 }
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