firmware/target/arm/as3525/usb-drv-as3525.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2010 Tobias Diedrich
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef __USB_DRV_AS3525_H__
  22 #define __USB_DRV_AS3525_H__
  23
  24 #include "as3525.h"
  25
  26 #define USB_NUM_EPS         4
  27
  28 typedef struct {
  29     volatile unsigned long offset[4096];
  30 } __regbase;
  31
  32 /*
  33  * This generates better code.
  34  * Stripped object size with __regbase construct:  5192
  35  * Stripped object size with *((volatile int)(x)): 5228
  36  */
  37 #define USB_REG(x)    ((__regbase *)(USB_BASE))->offset[(x)>>2]
  38
  39 /* 4 input endpoints */
  40 #define USB_IEP_CTRL(i)         USB_REG(0x0000 + i*0x20)
  41 #define USB_IEP_STS(i)          USB_REG(0x0004 + i*0x20)
  42 /* txfsize: bits 0-15 */
  43 #define USB_IEP_TXFSIZE(i)      USB_REG(0x0008 + i*0x20)
  44 /* mps: bits 0-10 (max 2047) */
  45 #define USB_IEP_MPS(i)          USB_REG(0x000C + i*0x20)
  46 #define USB_IEP_DESC_PTR(i)     USB_REG(0x0014 + i*0x20)
  47 #define USB_IEP_STS_MASK(i)     USB_REG(0x0018 + i*0x20)
  48
  49 /* 4 output endpoints */
  50 #define USB_OEP_CTRL(i)         USB_REG(0x0200 + i*0x20)
  51 #define USB_OEP_STS(i)          USB_REG(0x0204 + i*0x20)
  52 /* 'rx packet frame number' */
  53 #define USB_OEP_RXFR(i)         USB_REG(0x0208 + i*0x20)
  54 /* mps: bits 0-10 (max 2047), bits 23-31 are fifo size */
  55 #define USB_OEP_MPS(i)          USB_REG(0x020C + i*0x20)
  56 #define USB_OEP_SUP_PTR(i)      USB_REG(0x0210 + i*0x20)
  57 #define USB_OEP_DESC_PTR(i)     USB_REG(0x0214 + i*0x20)
  58 #define USB_OEP_STS_MASK(i)     USB_REG(0x0218 + i*0x20)
  59
  60 /* more general macro */
  61 /* d: true => IN, false => OUT */
  62 #define USB_EP_CTRL(i,d)        USB_REG(0x0000 + i*0x20 + (!d)*0x0200)
  63 #define USB_EP_STS(i,d)         USB_REG(0x0004 + i*0x20 + (!d)*0x0200)
  64 #define USB_EP_TXFSIZE(i,d)     USB_REG(0x0008 + i*0x20 + (!d)*0x0200)
  65 #define USB_EP_MPS(i,d)         USB_REG(0x000C + i*0x20 + (!d)*0x0200)
  66 #define USB_EP_DESC_PTR(i,d)    USB_REG(0x0014 + i*0x20 + (!d)*0x0200)
  67 #define USB_EP_STS_MASK(i,d)    USB_REG(0x0018 + i*0x20 + (!d)*0x0200)
  68
  69 #define USB_DEV_CFG             USB_REG(0x0400)
  70 #define USB_DEV_CTRL            USB_REG(0x0404)
  71 #define USB_DEV_STS             USB_REG(0x0408)
  72 #define USB_DEV_INTR            USB_REG(0x040C)
  73 #define USB_DEV_INTR_MASK       USB_REG(0x0410)
  74 #define USB_DEV_EP_INTR         USB_REG(0x0414)
  75 #define USB_DEV_EP_INTR_MASK    USB_REG(0x0418)
  76
  77 /* NOTE: Not written to in OF, most lied in host mode? */
  78 #define USB_PHY_EP0_INFO        USB_REG(0x0504)
  79 #define USB_PHY_EP1_INFO        USB_REG(0x0508)
  80 #define USB_PHY_EP2_INFO        USB_REG(0x050C)
  81 #define USB_PHY_EP3_INFO        USB_REG(0x0510)
  82 #define USB_PHY_EP4_INFO        USB_REG(0x0514)
  83 #define USB_PHY_EP5_INFO        USB_REG(0x0518)
  84
  85 /* 4 channels */
  86 #define USB_HOST_CH_SPLT(i)     USB_REG(0x1000 + i*0x20)
  87 #define USB_HOST_CH_STS(i)      USB_REG(0x1004 + i*0x20)
  88 #define USB_HOST_CH_TXFSIZE(i)  USB_REG(0x1008 + i*0x20)
  89 #define USB_HOST_CH_REQ(i)      USB_REG(0x100C + i*0x20)
  90 #define USB_HOST_CH_PER_INFO(i) USB_REG(0x1010 + i*0x20)
  91 #define USB_HOST_CH_DESC_PTR(i) USB_REG(0x1014 + i*0x20)
  92 #define USB_HOST_CH_STS_MASK(i) USB_REG(0x1018 + i*0x20)
  93
  94 #define USB_HOST_CFG            USB_REG(0x1400)
  95 #define USB_HOST_CTRL           USB_REG(0x1404)
  96 #define USB_HOST_INTR           USB_REG(0x140C)
  97 #define USB_HOST_INTR_MASK      USB_REG(0x1410)
  98 #define USB_HOST_CH_INTR        USB_REG(0x1414)
  99 #define USB_HOST_CH_INTR_MASK   USB_REG(0x1418)
 100 #define USB_HOST_FRAME_INT      USB_REG(0x141C)
 101 #define USB_HOST_FRAME_REM      USB_REG(0x1420)
 102 #define USB_HOST_FRAME_NUM      USB_REG(0x1424)
 103
 104 #define USB_HOST_PORT0_CTRL_STS USB_REG(0x1500)
 105
 106 #define USB_OTG_CSR             USB_REG(0x2000)
 107 #define USB_I2C_CSR             USB_REG(0x2004)
 108 #define USB_GPIO_CSR            USB_REG(0x2008)
 109 #define USB_SNPSID_CSR          USB_REG(0x200C)
 110 #define USB_USERID_CSR          USB_REG(0x2010)
 111 #define USB_USER_CONF1          USB_REG(0x2014)
 112 #define USB_USER_CONF2          USB_REG(0x2018)
 113 #define USB_USER_CONF3          USB_REG(0x201C)
 114 #define USB_USER_CONF4          USB_REG(0x2020)
 115 /* USER_CONF5 seems to the same as USBt least on read */
 116 #define USB_USER_CONF5          USB_REG(0x2024)
 117
 118 #define USB_CSR_NUM_MASK        0x0000000f
 119 #define USB_CSR_DIR_MASK        0x00000010
 120 #define USB_CSR_DIR_IN            0x00000010
 121 #define USB_CSR_DIR_OUT           0x00000000
 122 #define USB_CSR_TYPE_MASK       0x00000060
 123 #define USB_CSR_TYPE_CTL          0x00000000
 124 #define USB_CSR_TYPE_ISO          0x00000020
 125 #define USB_CSR_TYPE_BULK         0x00000040
 126 #define USB_CSR_TYPE_INT          0x00000060
 127 #define USB_CSR_CFG_MASK        0x00000780
 128 #define USB_CSR_INTF_MASK       0x00007800
 129 #define USB_CSR_ALT_MASK        0x00078000
 130 #define USB_CSR_MAXPKT_MASK     0x3ff80000
 131 #define USB_CSR_ISOMULT_MASK    0xc0000000
 132
 133 /* write bits 31..16 */
 134 #define USB_GPIO_IDDIG_SEL        (1<<30)
 135 #define USB_GPIO_FS_DATA_EXT      (1<<29)
 136 #define USB_GPIO_FS_SE0_EXT       (1<<28)
 137 #define USB_GPIO_FS_XCVR_OWNER    (1<<27)
 138 #define USB_GPIO_TX_ENABLE_N      (1<<26)
 139 #define USB_GPIO_TX_BIT_STUFF_EN  (1<<25)
 140 #define USB_GPIO_BSESSVLD_EXT     (1<<24)
 141 #define USB_GPIO_ASESSVLD_EXT     (1<<23)
 142 #define USB_GPIO_VBUS_VLD_EXT     (1<<22)
 143 #define USB_GPIO_VBUS_VLD_EXT_SEL (1<<21)
 144 #define USB_GPIO_XO_ON            (1<<20)
 145 #define USB_GPIO_CLK_SEL11        (3<<18)
 146 #define USB_GPIO_CLK_SEL10        (2<<18)
 147 #define USB_GPIO_CLK_SEL01        (1<<18)
 148 #define USB_GPIO_CLK_SEL00        (0<<18)
 149 #define USB_GPIO_XO_EXT_CLK_ENBN  (1<<17)
 150 #define USB_GPIO_XO_REFCLK_ENB    (1<<16)
 151 /* readronly bits 15..0 */
 152 #define USB_GPIO_PHY_VBUSDRV      (1<< 1)
 153 #define USB_GPIO_HS_INTR          (1<< 0)
 154
 155 /* Device Control Register and bit fields */
 156 #define USB_DEV_CTRL_REMOTE_WAKEUP      0x00000001  // set remote wake-up signal
 157 #define USB_DEV_CTRL_RESERVED0          0x00000002  // reserved, ro, read as 0
 158 #define USB_DEV_CTRL_RDE                0x00000004  // receive dma enable
 159 #define USB_DEV_CTRL_TDE                0x00000008  // transmit dma enable
 160 #define USB_DEV_CTRL_DESC_UPDATE        0x00000010  // update desc after dma
 161 #define USB_DEV_CTRL_BE                 0x00000020  // big endian when set (ro)
 162 #define USB_DEV_CTRL_BUFFER_FULL        0x00000040
 163 #define USB_DEV_CTRL_THRES_ENABLE       0x00000080  // threshold enable
 164 #define USB_DEV_CTRL_BURST_ENABLE       0x00000100  // ahb burst enable
 165 #define USB_DEV_CTRL_MODE               0x00000200  // 0=slave, 1=dma
 166 #define USB_DEV_CTRL_SOFT_DISCONN       0x00000400  // soft disconnect
 167 #define USB_DEV_CTRL_SCALEDOWN          0x00000800  // for simulation speedup
 168 #define USB_DEV_CTRL_DEVNAK             0x00001000  // set nak on all OUT EPs
 169 #define USB_DEV_CTRL_APCSR_DONE           0x00002000  // set to signal CSR update
 170 #define USB_DEV_CTRL_MASK_BURST_LEN     0x000f0000  // mask for burst length
 171 #define USB_DEV_CTRL_MASK_THRESHOLD_LEN 0xff000000  // mask for threshold length
 172
 173 /* settings of burst length for maskBurstLen_c field */
 174 /* amd 5536 datasheet: (BLEN+1) dwords */
 175 #define USB_DEV_CTRL_BLEN_1DWORD        0x00000000
 176 #define USB_DEV_CTRL_BLEN_2DWORDS       0x00010000
 177 #define USB_DEV_CTRL_BLEN_4DWORDS       0x00020000
 178 #define USB_DEV_CTRL_BLEN_8DWORDS       0x00030000
 179 #define USB_DEV_CTRL_BLEN_16DWORDS      0x00040000
 180 #define USB_DEV_CTRL_BLEN_32DWORDS      0x00050000
 181 #define USB_DEV_CTRL_BLEN_64DWORDS      0x00060000
 182 #define USB_DEV_CTRL_BLEN_128DWORDS     0x00070000
 183 #define USB_DEV_CTRL_BLEN_256DWORDS     0x00080000
 184 #define USB_DEV_CTRL_BLEN_512DWORDS     0x00090000
 185
 186 /* settings of threshold length for maskThresholdLen_c field */
 187 /* amd 5536 datasheet: (TLEN+1) dwords */
 188 #define USB_DEV_CTRL_TLEN_1DWORD        0x00000000
 189 #define USB_DEV_CTRL_TLEN_HALFMAXSIZE   0x01000000
 190 #define USB_DEV_CTRL_TLEN_4THMAXSIZE    0x02000000
 191 #define USB_DEV_CTRL_TLEN_8THMAXSIZE    0x03000000
 192
 193 #define USB_DEV_CFG_HS                  0x00000000
 194 #define USB_DEV_CFG_FS                  0x00000001 /* 30 or 60MHz */
 195 #define USB_DEV_CFG_LS                  0x00000002
 196 #define USB_DEV_CFG_FS_48               0x00000003 /* 48MHz */
 197 #define USB_DEV_CFG_REMOTE_WAKEUP       0x00000004
 198 #define USB_DEV_CFG_SELF_POWERED        0x00000008
 199 #define USB_DEV_CFG_SYNC_FRAME          0x00000010
 200 #define USB_DEV_CFG_PI_16BIT            0x00000000
 201 #define USB_DEV_CFG_PI_8BIT             0x00000020
 202 #define USB_DEV_CFG_UNI_DIR             0x00000000
 203 #define USB_DEV_CFG_BI_DIR              0x00000040
 204 #define USB_DEV_CFG_STAT_ACK            0x00000000
 205 #define USB_DEV_CFG_STAT_STALL          0x00000080
 206 #define USB_DEV_CFG_PHY_ERR_DETECT      0x00000200 /* monitor phy for errors */
 207 #define USB_DEV_CFG_HALT_STAT           0x00010000 /* ENDPOINT_HALT supported */
 208     /* 0: ACK, 1: STALL */
 209 #define USB_DEV_CFG_CSR_PRG             0x00020000
 210 #define USB_DEV_CFG_SET_DESC            0x00040000 /* SET_DESCRIPTOR supported */
 211     /* 0: STALL, 1: pass on setup packet */
 212 #define USB_DEV_CFG_DMA_RESET           0x20000000
 213 #define USB_DEV_CFG_HNPSFEN             0x40000000
 214 #define USB_DEV_CFG_SOFT_RESET          0x80000000
 215
 216 /* Device Status Register and bit fields */
 217 #define USB_DEV_STS_MASK_CFG            0x0000000f
 218 #define USB_DEV_STS_MASK_IF             0x000000f0
 219 #define USB_DEV_STS_MASK_ALT_SET        0x00000f00
 220 #define USB_DEV_STS_SUSPEND_STAT        0x00001000
 221 #define USB_DEV_STS_MASK_SPD            0x00006000 /* Enumerated Speed */
 222 #define USB_DEV_STS_SPD_HS                0x00000000
 223 #define USB_DEV_STS_SPD_FS                0x00002000
 224 #define USB_DEV_STS_SPD_LS                0x00004000
 225 #define USB_DEV_STS_RXF_EMPTY           0x00008000
 226 #define USB_DEV_STS_PHY_ERROR           0x00010000
 227 #define USB_DEV_STS_SESSVLD             0x00020000 /* session valid (vbus>1.2V) */
 228 #define USB_DEV_STS_MASK_FRM_NUM        0xfffc0000 /* SOF frame number */
 229
 230
 231 /* Device Intr Register and bit fields */
 232 #define USB_DEV_INTR_SET_CONFIG         0x00000001  /* set configuration cmd rcvd */
 233 #define USB_DEV_INTR_SET_INTERFACE      0x00000002  /* set interface command rcvd */
 234 #define USB_DEV_INTR_EARLY_SUSPEND      0x00000004  /* idle on usb for 3ms */
 235 #define USB_DEV_INTR_USB_RESET          0x00000008  /* usb bus reset req */
 236 #define USB_DEV_INTR_USB_SUSPEND        0x00000010  /* usb bus suspend req */
 237 #define USB_DEV_INTR_SOF                0x00000020  /* SOF seen on bus */
 238 #define USB_DEV_INTR_ENUM_DONE          0x00000040  /* usb speed enum done */
 239 #define USB_DEV_INTR_SVC                0x00000080  /* USB_DEV_STS changed */
 240 #define USB_DEV_INTR_MYSTERY            0x00000200  /* Unknown, maybe Host Error */
 241
 242 /* EP Control Register Fields */
 243 #define USB_EP_CTRL_STALL               0x00000001
 244 #define USB_EP_CTRL_FLUSH               0x00000002     /* EP In data fifo Flush */
 245 #define USB_EP_CTRL_SNOOP_MODE          0x00000004     // snoop mode for out endpoint
 246 #define USB_EP_CTRL_PD                  0x00000008     /* EP Poll Demand */
 247 #define USB_EP_CTRL_EPTYPE_MASK         0x00000030     // bit 5-4: endpoint types
 248 #define USB_EP_TYPE_CONTROL               0x00000000   // control endpoint
 249 #define USB_EP_TYPE_ISO                   0x00000010   // isochronous endpoint
 250 #define USB_EP_TYPE_BULK                  0x00000020   // bulk endpoint
 251 #define USB_EP_TYPE_INTERRUPT             0x00000030   // interrupt endpoint
 252 #define USB_EP_CTRL_NAK                 0x00000040     /* EP NAK Status */
 253 #define USB_EP_CTRL_SNAK                0x00000080     /* EP Set NAK Bit */
 254 #define USB_EP_CTRL_CNAK                0x00000100     /* EP Clr NAK Bit */
 255 #define USB_EP_CTRL_ACT                 0x00000400     /* EP Clr NAK Bit */
 256
 257 /* bit fields in EP Status Register */
 258 #define USB_EP_STAT_OUT_RCVD            0x00000010     /* OUT token received */
 259 #define USB_EP_STAT_SETUP_RCVD          0x00000020     /* SETUP token received */
 260 #define USB_EP_STAT_IN                  0x00000040     /* IN token received? */
 261 #define USB_EP_STAT_BNA                 0x00000080     /* Buffer Not Available */
 262 #define USB_EP_STAT_BUFF_ERROR          0x00000100
 263 #define USB_EP_STAT_HERR                0x00000200     /* Host Error */
 264 #define USB_EP_STAT_AHB_ERROR           0x00000200
 265 #define USB_EP_STAT_TDC                 0x00000400     /* Transmit DMA Complete */
 266
 267 /*-------------------------*/
 268 /* DMA Related Definitions */
 269 /*-------------------------*/
 270
 271 /* dma status */
 272 #define USB_DMA_DESC_BUFF_STS           0x80000000    /* Buffer Status */
 273 #define USB_DMA_DESC_BS_HST_RDY         0x80000000    /* Host Ready */
 274 #define USB_DMA_DESC_BS_DMA_DONE        0x00000000    /* DMA Done */
 275 #define USB_DMA_DESC_ZERO_LEN           0x40000000    /* zero length packet */
 276 #define USB_DMA_DESC_EARY_INTR          0x20000000    /* early interrupt */
 277 #define USB_DMA_DESC_RXTX_STS           0x10000000
 278 #define USB_DMA_DESC_RTS_SUCC           0x00000000    /* Success */
 279 #define USB_DMA_DESC_RTS_BUFERR         0x10000000    /* Buffer Error */
 280 #define USB_DMA_DESC_LAST               0x08000000
 281 #define USB_DMA_DESC_MASK_FRAM_NUM      0x07ff0000    // bits 26-16: frame number for iso
 282 #define USB_DMA_DESC_RXTX_BYTES         0x0000FFFF
 283
 284 /* setup descriptor */
 285 #define SETUP_MASK_CONFIG_STAT          0x0fff0000
 286 #define SETUP_MASK_CONFIG_NUM           0x0f000000
 287 #define SETUP_MASK_IF_NUM               0x00f00000
 288 #define SETUP_MASK_ALT_SETNUM           0x000f0000
 289
 290 #define EP_STATE_ALLOCATED              0x00000001
 291 #define EP_STATE_BUSY                   0x00000002
 292 #define EP_STATE_ASYNC                  0x00000004
 293
 294 struct usb_dev_dma_desc {
 295     int   status;
 296     int   resv;
 297     void  *data_ptr;
 298     void  *next_desc;
 299 };
 300
 301 struct usb_dev_setup_buf {
 302     int   status;
 303     int   resv;
 304     int   data1; /* first 4 bytes of data */
 305     int   data2; /* last 4 bytes of data */
 306 };
 307
 308 struct usb_endpoint
 309 {
 310     unsigned int len;
 311     volatile unsigned int state;
 312     int rc;
 313     struct wakeup complete;
 314     struct usb_dev_dma_desc *uc_desc;
 315 };
 316
 317 #endif /* __USB_DRV_AS3525_H__ */