firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2008 by Maurus Cuelenaere
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "config.h"
  23 #include "jz4740.h"
  24 #include "ata.h"
  25 #include "ata-sd-target.h"
  26 #include "logf.h"
  27 #include "sd.h"
  28 #include "system.h"
  29 #include "kernel.h"
  30 #include "panic.h"
  31 #include "debug.h"
  32 #include "storage.h"
  33 #include "string.h"
  34 #include "led.h"
  35
  36 static struct wakeup sd_wakeup;
  37 static long last_disk_activity = -1;
  38 static tCardInfo card;
  39
  40 //#define SD_DMA_ENABLE
  41 #define SD_DMA_INTERRUPT 0
  42
  43 #define DEBUG(x...)         logf(x)
  44
  45 #define SD_INSERT_STATUS() __gpio_get_pin(MMC_CD_PIN)
  46 #define SD_RESET()         __msc_reset()
  47
  48 #define SD_IRQ_MASK()              \
  49 do {                               \
  50           REG_MSC_IMASK = 0xffff;  \
  51           REG_MSC_IREG = 0xffff;   \
  52 } while (0)
  53
  54 /* Error codes */
  55 enum sd_result_t
  56 {
  57     SD_NO_RESPONSE        = -1,
  58     SD_NO_ERROR           = 0,
  59     SD_ERROR_OUT_OF_RANGE,
  60     SD_ERROR_ADDRESS,
  61     SD_ERROR_BLOCK_LEN,
  62     SD_ERROR_ERASE_SEQ,
  63     SD_ERROR_ERASE_PARAM,
  64     SD_ERROR_WP_VIOLATION,
  65     SD_ERROR_CARD_IS_LOCKED,
  66     SD_ERROR_LOCK_UNLOCK_FAILED,
  67     SD_ERROR_COM_CRC,
  68     SD_ERROR_ILLEGAL_COMMAND,
  69     SD_ERROR_CARD_ECC_FAILED,
  70     SD_ERROR_CC,
  71     SD_ERROR_GENERAL,
  72     SD_ERROR_UNDERRUN,
  73     SD_ERROR_OVERRUN,
  74     SD_ERROR_CID_CSD_OVERWRITE,
  75     SD_ERROR_STATE_MISMATCH,
  76     SD_ERROR_HEADER_MISMATCH,
  77     SD_ERROR_TIMEOUT,
  78     SD_ERROR_CRC,
  79     SD_ERROR_DRIVER_FAILURE,
  80 };
  81
  82 /* Standard MMC/SD clock speeds */
  83 #define MMC_CLOCK_SLOW    400000      /* 400 kHz for initial setup */
  84 #define SD_CLOCK_FAST   24000000      /* 24 MHz for SD Cards */
  85 #define SD_CLOCK_HIGH   48000000      /* 48 MHz for SD Cards */
  86
  87 /* Extra commands for state control */
  88 /* Use negative numbers to disambiguate */
  89 #define SD_CIM_RESET            -1
  90
  91 /* Proprietary commands, illegal/reserved according to SD Specification 2.00 */
  92     /* class 1 */
  93 #define SD_READ_DAT_UNTIL_STOP  11   /* adtc [31:0]  dadr       R1  */
  94
  95     /* class 3 */
  96 #define SD_WRITE_DAT_UNTIL_STOP 20   /* adtc [31:0]  data addr  R1  */
  97
  98     /* class 4 */
  99 #define SD_PROGRAM_CID          26   /* adtc                    R1  */
 100 #define SD_PROGRAM_CSD          27   /* adtc                    R1  */
 101
 102     /* class 9 */
 103 #define SD_GO_IRQ_STATE         40   /* bcr                     R5  */
 104
 105 /* Don't change the order of these; they are used in dispatch tables */
 106 enum sd_rsp_t
 107 {
 108     RESPONSE_NONE    = 0,
 109     RESPONSE_R1      = 1,
 110     RESPONSE_R1B     = 2,
 111     RESPONSE_R2_CID  = 3,
 112     RESPONSE_R2_CSD  = 4,
 113     RESPONSE_R3      = 5,
 114     RESPONSE_R4      = 6,
 115     RESPONSE_R5      = 7,
 116     RESPONSE_R6      = 8,
 117     RESPONSE_R7      = 9,
 118 };
 119
 120
 121 /*
 122   MMC status in R1
 123   Type
 124     e : error bit
 125     s : status bit
 126     r : detected and set for the actual command response
 127     x : detected and set during command execution. the host must poll
 128         the card by sending status command in order to read these bits.
 129   Clear condition
 130     a : according to the card state
 131     b : always related to the previous command. Reception of
 132         a valid command will clear it (with a delay of one command)
 133     c : clear by read
 134  */
 135
 136 #define R1_OUT_OF_RANGE        (1 << 31)    /* er, c */
 137 #define R1_ADDRESS_ERROR       (1 << 30)    /* erx, c */
 138 #define R1_BLOCK_LEN_ERROR     (1 << 29)    /* er, c */
 139 #define R1_ERASE_SEQ_ERROR     (1 << 28)    /* er, c */
 140 #define R1_ERASE_PARAM         (1 << 27)    /* ex, c */
 141 #define R1_WP_VIOLATION        (1 << 26)    /* erx, c */
 142 #define R1_CARD_IS_LOCKED      (1 << 25)    /* sx, a */
 143 #define R1_LOCK_UNLOCK_FAILED  (1 << 24)    /* erx, c */
 144 #define R1_COM_CRC_ERROR       (1 << 23)    /* er, b */
 145 #define R1_ILLEGAL_COMMAND     (1 << 22)    /* er, b */
 146 #define R1_CARD_ECC_FAILED     (1 << 21)    /* ex, c */
 147 #define R1_CC_ERROR            (1 << 20)    /* erx, c */
 148 #define R1_ERROR               (1 << 19)    /* erx, c */
 149 #define R1_UNDERRUN            (1 << 18)    /* ex, c */
 150 #define R1_OVERRUN             (1 << 17)    /* ex, c */
 151 #define R1_CID_CSD_OVERWRITE   (1 << 16)    /* erx, c, CID/CSD overwrite */
 152 #define R1_WP_ERASE_SKIP       (1 << 15)    /* sx, c */
 153 #define R1_CARD_ECC_DISABLED   (1 << 14)    /* sx, a */
 154 #define R1_ERASE_RESET         (1 << 13)    /* sr, c */
 155 #define R1_STATUS(x)           (x & 0xFFFFE000)
 156 #define R1_CURRENT_STATE(x)    ((x & 0x00001E00) >> 9)    /* sx, b (4 bits) */
 157 #define R1_READY_FOR_DATA      (1 << 8)     /* sx, a */
 158 #define R1_APP_CMD             (1 << 7)     /* sr, c */
 159
 160 /* These are unpacked versions of the actual responses */
 161 struct sd_response_r1
 162 {
 163     unsigned char  cmd;
 164     unsigned int   status;
 165 };
 166
 167 struct sd_response_r3
 168 {
 169     unsigned int ocr;
 170 };
 171
 172 #define SD_CARD_BUSY    0x80000000    /* Card Power up status bit */
 173
 174 struct sd_request
 175 {
 176     int               index;      /* Slot index - used for CS lines */
 177     int               cmd;        /* Command to send */
 178     unsigned int      arg;        /* Argument to send */
 179     enum sd_rsp_t    rtype;      /* Response type expected */
 180
 181     /* Data transfer (these may be modified at the low level) */
 182     unsigned short    nob;        /* Number of blocks to transfer*/
 183     unsigned short    block_len;  /* Block length */
 184     unsigned char     *buffer;    /* Data buffer */
 185     unsigned int      cnt;        /* Data length, for PIO */
 186
 187     /* Results */
 188     unsigned char     response[18]; /* Buffer to store response - CRC is optional */
 189     enum sd_result_t result;
 190 };
 191
 192 #define SD_OCR_ARG             0x00ff8000  /* Argument of OCR */
 193
 194 /***********************************************************************
 195  *  SD Events
 196  */
 197 #define SD_EVENT_NONE            0x00    /* No events */
 198 #define SD_EVENT_RX_DATA_DONE    0x01    /* Rx data done */
 199 #define SD_EVENT_TX_DATA_DONE    0x02    /* Tx data done */
 200 #define SD_EVENT_PROG_DONE       0x04    /* Programming is done */
 201
 202 static int use_4bit = 1;        /* Use 4-bit data bus */
 203 static int num_6 = 0;
 204 static int sd2_0 = 0;
 205
 206 /**************************************************************************
 207  * Utility functions
 208  **************************************************************************/
 209
 210 #define PARSE_U32(_buf,_index) \
 211     (((unsigned int)_buf[_index]) << 24) | (((unsigned int)_buf[_index+1]) << 16) | \
 212         (((unsigned int)_buf[_index+2]) << 8) | ((unsigned int)_buf[_index+3]);
 213
 214 #define PARSE_U16(_buf,_index) \
 215     (((unsigned short)_buf[_index]) << 8) | ((unsigned short)_buf[_index+1]);
 216
 217 int sd_unpack_r1(struct sd_request *request, struct sd_response_r1 *r1)
 218 {
 219     unsigned char *buf = request->response;
 220
 221     if (request->result)
 222         return request->result;
 223
 224     r1->cmd    = buf[0];
 225     r1->status = PARSE_U32(buf,1);
 226
 227     DEBUG("sd_unpack_r1: cmd=%d status=%08x", r1->cmd, r1->status);
 228
 229     if (R1_STATUS(r1->status)) {
 230         if (r1->status & R1_OUT_OF_RANGE)       return SD_ERROR_OUT_OF_RANGE;
 231         if (r1->status & R1_ADDRESS_ERROR)      return SD_ERROR_ADDRESS;
 232         if (r1->status & R1_BLOCK_LEN_ERROR)    return SD_ERROR_BLOCK_LEN;
 233         if (r1->status & R1_ERASE_SEQ_ERROR)    return SD_ERROR_ERASE_SEQ;
 234         if (r1->status & R1_ERASE_PARAM)        return SD_ERROR_ERASE_PARAM;
 235         if (r1->status & R1_WP_VIOLATION)       return SD_ERROR_WP_VIOLATION;
 236         //if (r1->status & R1_CARD_IS_LOCKED)     return SD_ERROR_CARD_IS_LOCKED;
 237         if (r1->status & R1_LOCK_UNLOCK_FAILED) return SD_ERROR_LOCK_UNLOCK_FAILED;
 238         if (r1->status & R1_COM_CRC_ERROR)      return SD_ERROR_COM_CRC;
 239         if (r1->status & R1_ILLEGAL_COMMAND)    return SD_ERROR_ILLEGAL_COMMAND;
 240         if (r1->status & R1_CARD_ECC_FAILED)    return SD_ERROR_CARD_ECC_FAILED;
 241         if (r1->status & R1_CC_ERROR)           return SD_ERROR_CC;
 242         if (r1->status & R1_ERROR)              return SD_ERROR_GENERAL;
 243         if (r1->status & R1_UNDERRUN)           return SD_ERROR_UNDERRUN;
 244         if (r1->status & R1_OVERRUN)            return SD_ERROR_OVERRUN;
 245         if (r1->status & R1_CID_CSD_OVERWRITE)  return SD_ERROR_CID_CSD_OVERWRITE;
 246     }
 247
 248     if (buf[0] != request->cmd)
 249         return SD_ERROR_HEADER_MISMATCH;
 250
 251     /* This should be last - it's the least dangerous error */
 252
 253     return 0;
 254 }
 255
 256 int sd_unpack_scr(struct sd_request *request, struct sd_response_r1 *r1, unsigned int *scr)
 257 {
 258     unsigned char *buf = request->response;
 259     if (request->result)
 260         return request->result;
 261
 262     *scr = PARSE_U32(buf, 5); /* Save SCR returned by the SD Card */
 263     return sd_unpack_r1(request, r1);
 264 }
 265
 266 static inline int sd_unpack_r6(struct sd_request *request, struct sd_response_r1 *r1, unsigned long *rca)
 267 {
 268     unsigned char *buf = request->response;
 269
 270     if (request->result)
 271         return request->result;
 272
 273     *rca = PARSE_U16(buf,1);  /* Save RCA returned by the SD Card */
 274
 275     *(buf+1) = 0;
 276     *(buf+2) = 0;
 277
 278     return sd_unpack_r1(request, r1);
 279 }
 280
 281 int sd_unpack_r3(struct sd_request *request, struct sd_response_r3 *r3)
 282 {
 283     unsigned char *buf = request->response;
 284
 285     if (request->result) return request->result;
 286
 287     r3->ocr = PARSE_U32(buf,1);
 288     DEBUG("sd_unpack_r3: ocr=%08x", r3->ocr);
 289
 290     if (buf[0] != 0x3f)  return SD_ERROR_HEADER_MISMATCH;
 291     return 0;
 292 }
 293
 294 /* Stop the MMC clock and wait while it happens */
 295 static inline int jz_sd_stop_clock(void)
 296 {
 297     register int timeout = 1000;
 298
 299     //DEBUG("stop MMC clock");
 300     REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP;
 301
 302     while (timeout && (REG_MSC_STAT & MSC_STAT_CLK_EN))
 303     {
 304         timeout--;
 305         if (timeout == 0)
 306         {
 307             DEBUG("Timeout on stop clock waiting");
 308             return SD_ERROR_TIMEOUT;
 309         }
 310         udelay(1);
 311     }
 312     //DEBUG("clock off time is %d microsec", timeout);
 313     return SD_NO_ERROR;
 314 }
 315
 316 /* Start the MMC clock and operation */
 317 static inline int jz_sd_start_clock(void)
 318 {
 319     REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START | MSC_STRPCL_START_OP;
 320     return SD_NO_ERROR;
 321 }
 322
 323 static int jz_sd_check_status(struct sd_request *request)
 324 {
 325     (void)request;
 326     unsigned int status = REG_MSC_STAT;
 327
 328     /* Checking for response or data timeout */
 329     if (status & (MSC_STAT_TIME_OUT_RES | MSC_STAT_TIME_OUT_READ))
 330     {
 331         DEBUG("SD timeout, MSC_STAT 0x%x CMD %d", status,
 332                request->cmd);
 333         return SD_ERROR_TIMEOUT;
 334     }
 335
 336     /* Checking for CRC error */
 337     if (status &
 338         (MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR |
 339          MSC_STAT_CRC_RES_ERR))
 340     {
 341         DEBUG("SD CRC error, MSC_STAT 0x%x", status);
 342         return SD_ERROR_CRC;
 343
 344     }
 345
 346
 347     /* Checking for FIFO empty */
 348     /*if(status & MSC_STAT_DATA_FIFO_EMPTY && request->rtype != RESPONSE_NONE)
 349     {
 350         DEBUG("SD FIFO empty, MSC_STAT 0x%x", status);
 351         return SD_ERROR_UNDERRUN;
 352     }*/
 353
 354     return SD_NO_ERROR;
 355 }
 356
 357 /* Obtain response to the command and store it to response buffer */
 358 static void jz_sd_get_response(struct sd_request *request)
 359 {
 360     int i;
 361     unsigned char *buf;
 362     unsigned int data;
 363
 364     DEBUG("fetch response for request %d, cmd %d", request->rtype,
 365           request->cmd);
 366     buf = request->response;
 367     request->result = SD_NO_ERROR;
 368
 369     switch (request->rtype)
 370     {
 371         case RESPONSE_R1:
 372         case RESPONSE_R1B:
 373         case RESPONSE_R7:
 374         case RESPONSE_R6:
 375         case RESPONSE_R3:
 376         case RESPONSE_R4:
 377         case RESPONSE_R5:
 378         {
 379             data = REG_MSC_RES;
 380             buf[0] = (data >> 8) & 0xff;
 381             buf[1] = data & 0xff;
 382             data = REG_MSC_RES;
 383             buf[2] = (data >> 8) & 0xff;
 384             buf[3] = data & 0xff;
 385             data = REG_MSC_RES;
 386             buf[4] = data & 0xff;
 387
 388             DEBUG("request %d, response [%02x %02x %02x %02x %02x]",
 389                   request->rtype, buf[0], buf[1], buf[2],
 390                   buf[3], buf[4]);
 391             break;
 392         }
 393         case RESPONSE_R2_CID:
 394         case RESPONSE_R2_CSD:
 395         {
 396             for (i = 0; i < 16; i += 2)
 397             {
 398                 data = REG_MSC_RES;
 399                 buf[i] = (data >> 8) & 0xff;
 400                 buf[i + 1] = data & 0xff;
 401             }
 402             DEBUG("request %d, response []", request->rtype);
 403             break;
 404         }
 405         case RESPONSE_NONE:
 406             DEBUG("No response");
 407             break;
 408
 409         default:
 410             DEBUG("unhandled response type for request %d",
 411                   request->rtype);
 412             break;
 413     }
 414 }
 415
 416 #ifdef SD_DMA_ENABLE
 417 static void jz_sd_receive_data_dma(struct sd_request *req)
 418 {
 419     unsigned int size = req->block_len * req->nob;
 420 #if MMC_DMA_INTERRUPT
 421     unsigned char err = 0;
 422 #endif
 423
 424     /* flush dcache */
 425     //dma_cache_wback_inv((unsigned long) req->buffer, size);
 426     /* setup dma channel */
 427     REG_DMAC_DSAR(DMA_SD_RX_CHANNEL) = PHYSADDR(MSC_RXFIFO);    /* DMA source addr */
 428     REG_DMAC_DTAR(DMA_SD_RX_CHANNEL) = PHYSADDR((unsigned long) req->buffer);    /* DMA dest addr */
 429     REG_DMAC_DTCR(DMA_SD_RX_CHANNEL) = (size + 3) / 4;    /* DMA transfer count */
 430     REG_DMAC_DRSR(DMA_SD_RX_CHANNEL) = DMAC_DRSR_RS_MSCIN;    /* DMA request type */
 431
 432 #if SD_DMA_INTERRUPT
 433     REG_DMAC_DCMD(DMA_SD_RX_CHANNEL) =
 434         DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
 435         DMAC_DCMD_DS_32BIT | DMAC_DCMD_TIE;
 436     REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
 437     OSSemPend(sd_dma_rx_sem, 100, &err);
 438 #else
 439     REG_DMAC_DCMD(DMA_SD_RX_CHANNEL) =
 440         DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
 441         DMAC_DCMD_DS_32BIT;
 442     REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
 443
 444     //while (REG_DMAC_DTCR(DMA_SD_RX_CHANNEL));
 445     while( !(REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) & DMAC_DCCSR_TT) );
 446 #endif
 447
 448     /* clear status and disable channel */
 449     REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = 0;
 450 }
 451
 452 static void jz_mmc_transmit_data_dma(struct mmc_request *req)
 453 {
 454     unsigned int size = req->block_len * req->nob;
 455 #if SD_DMA_INTERRUPT
 456     unsigned char err = 0;
 457 #endif
 458
 459     /* flush dcache */
 460     //dma_cache_wback_inv((unsigned long) req->buffer, size);
 461     /* setup dma channel */
 462     REG_DMAC_DSAR(DMA_SD_TX_CHANNEL) = PHYSADDR((unsigned long) req->buffer);    /* DMA source addr */
 463     REG_DMAC_DTAR(DMA_SD_TX_CHANNEL) = PHYSADDR(MSC_TXFIFO);    /* DMA dest addr */
 464     REG_DMAC_DTCR(DMA_SD_TX_CHANNEL) = (size + 3) / 4;    /* DMA transfer count */
 465     REG_DMAC_DRSR(DMA_SD_TX_CHANNEL) = DMAC_DRSR_RS_MSCOUT;    /* DMA request type */
 466
 467 #if SD_DMA_INTERRUPT
 468     REG_DMAC_DCMD(DMA_SD_TX_CHANNEL) =
 469         DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
 470         DMAC_DCMD_DS_32BIT | DMAC_DCMD_TIE;
 471     REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
 472     OSSemPend(sd_dma_tx_sem, 100, &err);
 473 #else
 474     REG_DMAC_DCMD(DMA_SD_TX_CHANNEL) =
 475         DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
 476         DMAC_DCMD_DS_32BIT;
 477     REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
 478     /* wait for dma completion */
 479     while( !(REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) & DMAC_DCCSR_TT) );
 480 #endif
 481     /* clear status and disable channel */
 482
 483     REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = 0;
 484 }
 485
 486 #else                /* SD_DMA_ENABLE */
 487
 488 static int jz_sd_receive_data(struct sd_request *req)
 489 {
 490     unsigned int nob = req->nob;
 491     unsigned int wblocklen = (unsigned int) (req->block_len + 3) >> 2;    /* length in word */
 492     unsigned char *buf = req->buffer;
 493     unsigned int *wbuf = (unsigned int *) buf;
 494     unsigned int waligned = (((unsigned int) buf & 0x3) == 0);    /* word aligned ? */
 495     unsigned int stat, timeout, data, cnt;
 496
 497     for (; nob >= 1; nob--)
 498     {
 499         timeout = 0x3FFFFFF;
 500
 501         while (timeout)
 502         {
 503             timeout--;
 504             stat = REG_MSC_STAT;
 505
 506             if (stat & MSC_STAT_TIME_OUT_READ)
 507                 return SD_ERROR_TIMEOUT;
 508             else if (stat & MSC_STAT_CRC_READ_ERROR)
 509                 return SD_ERROR_CRC;
 510             else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY)
 511                  || (stat & MSC_STAT_DATA_FIFO_AFULL))
 512                 /* Ready to read data */
 513                 break;
 514
 515             udelay(1);
 516         }
 517
 518         if (!timeout)
 519             return SD_ERROR_TIMEOUT;
 520
 521         /* Read data from RXFIFO. It could be FULL or PARTIAL FULL */
 522         DEBUG("Receive Data = %d", wblocklen);
 523         cnt = wblocklen;
 524         while (cnt)
 525         {
 526             data = REG_MSC_RXFIFO;
 527             if (waligned)
 528                 *wbuf++ = data;
 529             else
 530             {
 531                 *buf++ = (unsigned char) (data >> 0);
 532                 *buf++ = (unsigned char) (data >> 8);
 533                 *buf++ = (unsigned char) (data >> 16);
 534                 *buf++ = (unsigned char) (data >> 24);
 535             }
 536             cnt--;
 537             while (cnt
 538                    && (REG_MSC_STAT &
 539                    MSC_STAT_DATA_FIFO_EMPTY));
 540         }
 541     }
 542
 543     return SD_NO_ERROR;
 544 }
 545
 546 static int jz_sd_transmit_data(struct sd_request *req)
 547 {
 548     unsigned int nob = req->nob;
 549     unsigned int wblocklen = (unsigned int) (req->block_len + 3) >> 2;    /* length in word */
 550     unsigned char *buf = req->buffer;
 551     unsigned int *wbuf = (unsigned int *) buf;
 552     unsigned int waligned = (((unsigned int) buf & 0x3) == 0);    /* word aligned ? */
 553     unsigned int stat, timeout, data, cnt;
 554
 555     for (; nob >= 1; nob--)
 556     {
 557         timeout = 0x3FFFFFF;
 558
 559         while (timeout)
 560         {
 561             timeout--;
 562             stat = REG_MSC_STAT;
 563
 564             if (stat &
 565                 (MSC_STAT_CRC_WRITE_ERROR |
 566                  MSC_STAT_CRC_WRITE_ERROR_NOSTS))
 567                 return SD_ERROR_CRC;
 568             else if (!(stat & MSC_STAT_DATA_FIFO_FULL))
 569                 /* Ready to write data */
 570                 break;
 571
 572             udelay(1);
 573         }
 574
 575         if (!timeout)
 576             return SD_ERROR_TIMEOUT;
 577
 578         /* Write data to TXFIFO */
 579         cnt = wblocklen;
 580         while (cnt)
 581         {
 582             while (REG_MSC_STAT & MSC_STAT_DATA_FIFO_FULL);
 583
 584             if (waligned)
 585                 REG_MSC_TXFIFO = *wbuf++;
 586             else
 587             {
 588                 data = *buf++;
 589                 data |= *buf++ << 8;
 590                 data |= *buf++ << 16;
 591                 data |= *buf++ << 24;
 592                 REG_MSC_TXFIFO = data;
 593             }
 594
 595             cnt--;
 596         }
 597     }
 598
 599     return SD_NO_ERROR;
 600 }
 601 #endif
 602
 603 static inline unsigned int jz_sd_calc_clkrt(unsigned int rate)
 604 {
 605     unsigned int clkrt;
 606     unsigned int clk_src = sd2_0 ? SD_CLOCK_HIGH : SD_CLOCK_FAST;
 607
 608     clkrt = 0;
 609     while (rate < clk_src)
 610     {
 611         clkrt++;
 612         clk_src >>= 1;
 613     }
 614     return clkrt;
 615 }
 616
 617 static inline void cpm_select_msc_clk(unsigned int rate)
 618 {
 619     unsigned int div = __cpm_get_pllout2() / rate;
 620
 621     REG_CPM_MSCCDR = div - 1;
 622 }
 623
 624 /* Set the MMC clock frequency */
 625 static void jz_sd_set_clock(unsigned int rate)
 626 {
 627     int clkrt;
 628
 629     jz_sd_stop_clock();
 630
 631     /* select clock source from CPM */
 632     cpm_select_msc_clk(rate);
 633
 634     REG_CPM_CPCCR |= CPM_CPCCR_CE;
 635     clkrt = jz_sd_calc_clkrt(rate);
 636     REG_MSC_CLKRT = clkrt;
 637
 638     DEBUG("set clock to %u Hz clkrt=%d", rate, clkrt);
 639 }
 640
 641 /********************************************************************************************************************
 642 ** Name:      int jz_sd_exec_cmd()
 643 ** Function:  send command to the card, and get a response
 644 ** Input:     struct sd_request *req: SD request
 645 ** Output:    0:  right        >0:  error code
 646 ********************************************************************************************************************/
 647 static int jz_sd_exec_cmd(struct sd_request *request)
 648 {
 649     unsigned int cmdat = 0, events = 0;
 650     int retval, timeout = 0x3fffff;
 651
 652     /* Indicate we have no result yet */
 653     request->result = SD_NO_RESPONSE;
 654
 655     if (request->cmd == SD_CIM_RESET) {
 656         /* On reset, 1-bit bus width */
 657         use_4bit = 0;
 658
 659         /* Reset MMC/SD controller */
 660         __msc_reset();
 661
 662         /* On reset, drop SD clock down */
 663         jz_sd_set_clock(MMC_CLOCK_SLOW);
 664
 665         /* On reset, stop SD clock */
 666         jz_sd_stop_clock();
 667     }
 668     if (request->cmd == SD_SET_BUS_WIDTH)
 669     {
 670         if (request->arg == 0x2)
 671         {
 672             DEBUG("Use 4-bit bus width");
 673             use_4bit = 1;
 674         }
 675         else
 676         {
 677             DEBUG("Use 1-bit bus width");
 678             use_4bit = 0;
 679         }
 680     }
 681
 682     /* stop clock */
 683     jz_sd_stop_clock();
 684
 685     /* mask all interrupts */
 686     //REG_MSC_IMASK = 0xffff;
 687     /* clear status */
 688     REG_MSC_IREG = 0xffff;
 689     /*open interrupt */
 690     REG_MSC_IMASK = (~7);
 691     /* use 4-bit bus width when possible */
 692     if (use_4bit)
 693         cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT;
 694
 695     /* Set command type and events */
 696     switch (request->cmd)
 697     {
 698         /* SD core extra command */
 699         case SD_CIM_RESET:
 700             cmdat |= MSC_CMDAT_INIT; /* Initialization sequence sent prior to command */
 701             break;
 702             /* bc - broadcast - no response */
 703         case SD_GO_IDLE_STATE:
 704         case SD_SET_DSR:
 705             break;
 706
 707             /* bcr - broadcast with response */
 708         case SD_APP_OP_COND:
 709         case SD_ALL_SEND_CID:
 710         case SD_GO_IRQ_STATE:
 711             break;
 712
 713             /* adtc - addressed with data transfer */
 714         case SD_READ_DAT_UNTIL_STOP:
 715         case SD_READ_SINGLE_BLOCK:
 716         case SD_READ_MULTIPLE_BLOCK:
 717         case SD_SEND_SCR:
 718 #if defined(SD_DMA_ENABLE)
 719             cmdat |=
 720                 MSC_CMDAT_DATA_EN | MSC_CMDAT_READ | MSC_CMDAT_DMA_EN;
 721 #else
 722             cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ;
 723 #endif
 724             events = SD_EVENT_RX_DATA_DONE;
 725             break;
 726
 727         case 6:
 728             if (num_6 < 2)
 729             {
 730 #if defined(SD_DMA_ENABLE)
 731                 cmdat |=
 732                     MSC_CMDAT_DATA_EN | MSC_CMDAT_READ |
 733                     MSC_CMDAT_DMA_EN;
 734 #else
 735                 cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ;
 736 #endif
 737                 events = SD_EVENT_RX_DATA_DONE;
 738             }
 739             break;
 740
 741         case SD_WRITE_DAT_UNTIL_STOP:
 742         case SD_WRITE_BLOCK:
 743         case SD_WRITE_MULTIPLE_BLOCK:
 744         case SD_PROGRAM_CID:
 745         case SD_PROGRAM_CSD:
 746         case SD_LOCK_UNLOCK:
 747 #if defined(SD_DMA_ENABLE)
 748             cmdat |=
 749                 MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE | MSC_CMDAT_DMA_EN;
 750 #else
 751             cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE;
 752 #endif
 753             events = SD_EVENT_TX_DATA_DONE | SD_EVENT_PROG_DONE;
 754             break;
 755
 756         case SD_STOP_TRANSMISSION:
 757             events = SD_EVENT_PROG_DONE;
 758             break;
 759
 760         /* ac - no data transfer */
 761         default:
 762             break;
 763     }
 764
 765     /* Set response type */
 766     switch (request->rtype)
 767     {
 768         case RESPONSE_NONE:
 769             break;
 770         case RESPONSE_R1B:
 771             cmdat |= MSC_CMDAT_BUSY;
 772             /* FALLTHRU */
 773         case RESPONSE_R1:
 774         case RESPONSE_R7:
 775             cmdat |= MSC_CMDAT_RESPONSE_R1;
 776             break;
 777         case RESPONSE_R2_CID:
 778         case RESPONSE_R2_CSD:
 779             cmdat |= MSC_CMDAT_RESPONSE_R2;
 780             break;
 781         case RESPONSE_R3:
 782             cmdat |= MSC_CMDAT_RESPONSE_R3;
 783             break;
 784         case RESPONSE_R4:
 785             cmdat |= MSC_CMDAT_RESPONSE_R4;
 786             break;
 787         case RESPONSE_R5:
 788             cmdat |= MSC_CMDAT_RESPONSE_R5;
 789             break;
 790         case RESPONSE_R6:
 791             cmdat |= MSC_CMDAT_RESPONSE_R6;
 792             break;
 793         default:
 794             break;
 795     }
 796
 797     /* Set command index */
 798     if (request->cmd == SD_CIM_RESET)
 799         REG_MSC_CMD = SD_GO_IDLE_STATE;
 800     else
 801         REG_MSC_CMD = request->cmd;
 802
 803     /* Set argument */
 804     REG_MSC_ARG = request->arg;
 805
 806     /* Set block length and nob */
 807     if (request->cmd == SD_SEND_SCR)
 808     {    /* get SCR from DataFIFO */
 809         REG_MSC_BLKLEN = 8;
 810         REG_MSC_NOB = 1;
 811     }
 812     else
 813     {
 814         REG_MSC_BLKLEN = request->block_len;
 815         REG_MSC_NOB = request->nob;
 816     }
 817
 818     /* Set command */
 819     REG_MSC_CMDAT = cmdat;
 820
 821     DEBUG("Send cmd %d cmdat: %x arg: %x resp %d", request->cmd,
 822           cmdat, request->arg, request->rtype);
 823
 824     /* Start SD clock and send command to card */
 825     jz_sd_start_clock();
 826
 827     /* Wait for command completion */
 828     //__intc_unmask_irq(IRQ_MSC);
 829     //wakeup_wait(&sd_wakeup, 100);
 830     while (timeout-- && !(REG_MSC_STAT & MSC_STAT_END_CMD_RES));
 831
 832
 833     if (timeout == 0)
 834         return SD_ERROR_TIMEOUT;
 835
 836     REG_MSC_IREG = MSC_IREG_END_CMD_RES;    /* clear flag */
 837
 838     /* Check for status */
 839     retval = jz_sd_check_status(request);
 840     if (retval)
 841         return retval;
 842
 843     /* Complete command with no response */
 844     if (request->rtype == RESPONSE_NONE)
 845         return SD_NO_ERROR;
 846
 847     /* Get response */
 848     jz_sd_get_response(request);
 849
 850     /* Start data operation */
 851     if (events & (SD_EVENT_RX_DATA_DONE | SD_EVENT_TX_DATA_DONE))
 852     {
 853         if (events & SD_EVENT_RX_DATA_DONE)
 854         {
 855             if (request->cmd == SD_SEND_SCR)
 856             {
 857                 /* SD card returns SCR register as data.
 858                    SD core expect it in the response buffer,
 859                    after normal response. */
 860                 request->buffer =
 861                     (unsigned char *) ((unsigned int) request->response + 5);
 862             }
 863 #ifdef SD_DMA_ENABLE
 864             jz_sd_receive_data_dma(request);
 865 #else
 866             jz_sd_receive_data(request);
 867 #endif
 868         }
 869
 870         if (events & SD_EVENT_TX_DATA_DONE)
 871         {
 872 #ifdef SD_DMA_ENABLE
 873             jz_sd_transmit_data_dma(request);
 874 #else
 875             jz_sd_transmit_data(request);
 876 #endif
 877         }
 878         //__intc_unmask_irq(IRQ_MSC);
 879         //wakeup_wait(&sd_wakeup, 100);
 880         /* Wait for Data Done */
 881         while (!(REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE));
 882         REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE;    /* clear status */
 883     }
 884
 885     /* Wait for Prog Done event */
 886     if (events & SD_EVENT_PROG_DONE)
 887     {
 888         //__intc_unmask_irq(IRQ_MSC);
 889         //wakeup_wait(&sd_wakeup, 100);
 890         while (!(REG_MSC_IREG & MSC_IREG_PRG_DONE));
 891         REG_MSC_IREG = MSC_IREG_PRG_DONE;    /* clear status */
 892     }
 893
 894     /* Command completed */
 895
 896     return SD_NO_ERROR;    /* return successfully */
 897 }
 898
 899 /*******************************************************************************************************************
 900 ** Name:      int sd_chkcard()
 901 ** Function:  check whether card is insert entirely
 902 ** Input:     NULL
 903 ** Output:    1: insert entirely    0: not insert entirely
 904 ********************************************************************************************************************/
 905 static int jz_sd_chkcard(void)
 906 {
 907     return (SD_INSERT_STATUS() == 0 ? 1 : 0);
 908 }
 909
 910 #if SD_DMA_INTERRUPT
 911 static void jz_sd_tx_handler(unsigned int arg)
 912 {
 913     if (__dmac_channel_address_error_detected(arg))
 914     {
 915         DEBUG("%s: DMAC address error.", __FUNCTION__);
 916         __dmac_channel_clear_address_error(arg);
 917     }
 918     if (__dmac_channel_transmit_end_detected(arg))
 919     {
 920
 921         __dmac_channel_clear_transmit_end(arg);
 922         OSSemPost(sd_dma_tx_sem);
 923     }
 924 }
 925
 926 static void jz_sd_rx_handler(unsigned int arg)
 927 {
 928     if (__dmac_channel_address_error_detected(arg))
 929     {
 930         DEBUG("%s: DMAC address error.", __FUNCTION__);
 931         __dmac_channel_clear_address_error(arg);
 932     }
 933     if (__dmac_channel_transmit_end_detected(arg))
 934     {
 935         __dmac_channel_clear_transmit_end(arg);
 936         OSSemPost(sd_dma_rx_sem);
 937     }
 938 }
 939 #endif
 940
 941 /* MSC interrupt handler */
 942 void MSC(void)
 943 {
 944     //wakeup_signal(&sd_wakeup);
 945     logf("MSC interrupt");
 946 }
 947
 948 /*******************************************************************************************************************
 949 ** Name:      void sd_hardware_init()
 950 ** Function:  initialize the hardware condiction that access sd card
 951 ** Input:     NULL
 952 ** Output:    NULL
 953 ********************************************************************************************************************/
 954 static void jz_sd_hardware_init(void)
 955 {
 956     __cpm_start_msc();   /* enable mmc clock */
 957     mmc_init_gpio();     /* init GPIO */
 958 #ifdef SD_POWER_ON
 959     SD_POWER_ON();      /* turn on power of card */
 960 #endif
 961     SD_RESET();         /* reset mmc/sd controller */
 962     SD_IRQ_MASK();      /* mask all IRQs */
 963     jz_sd_stop_clock(); /* stop SD clock */
 964 #ifdef SD_DMA_ENABLE
 965 //    __cpm_start_dmac();
 966 //    __dmac_enable_module();
 967 //      REG_DMAC_DMACR = DMAC_DMACR_DME;
 968 #if SD_DMA_INTERRUPT
 969     sd_dma_rx_sem = OSSemCreate(0);
 970     sd_dma_tx_sem = OSSemCreate(0);
 971     request_irq(IRQ_DMA_0 + RX_DMA_CHANNEL, jz_sd_rx_handler,
 972             RX_DMA_CHANNEL);
 973     request_irq(IRQ_DMA_0 + TX_DMA_CHANNEL, jz_sd_tx_handler,
 974             TX_DMA_CHANNEL);
 975 #endif
 976 #endif
 977 }
 978
 979 static int sd_send_cmd(struct sd_request *request, int cmd, unsigned int arg,
 980                          unsigned short nob, unsigned short block_len,
 981                          enum sd_rsp_t rtype, unsigned char* buffer)
 982 {
 983     request->cmd = cmd;
 984     request->arg = arg;
 985     request->rtype = rtype;
 986     request->nob = nob;
 987     request->block_len = block_len;
 988     request->buffer = buffer;
 989     request->cnt = nob * block_len;
 990
 991     return jz_sd_exec_cmd(request);
 992 }
 993
 994 static void sd_simple_cmd(struct sd_request *request, int cmd, unsigned int arg,
 995                            enum sd_rsp_t rtype)
 996 {
 997     sd_send_cmd(request, cmd, arg, 0, 0, rtype, NULL);
 998 }
 999
1000 #define SD_INIT_DOING   0
1001 #define SD_INIT_PASSED  1
1002 #define SD_INIT_FAILED  2
1003
1004 static int sd_init_card_state(struct sd_request *request)
1005 {
1006     struct sd_response_r1 r1;
1007     struct sd_response_r3 r3;
1008     int retval, i, ocr = 0x40300000, limit_41 = 0;
1009
1010     switch (request->cmd)
1011     {
1012         case SD_GO_IDLE_STATE: /* No response to parse */
1013             sd_simple_cmd(request, SD_SEND_IF_COND, 0x1AA, RESPONSE_R1);
1014             break;
1015
1016         case SD_SEND_IF_COND:
1017             retval = sd_unpack_r1(request, &r1);
1018             sd_simple_cmd(request, SD_APP_CMD,  0, RESPONSE_R1);
1019             break;
1020
1021         case SD_APP_CMD:
1022             retval = sd_unpack_r1(request, &r1);
1023             if (retval & (limit_41 < 100))
1024             {
1025                 DEBUG("sd_init_card_state: unable to SD_APP_CMD error=%d",
1026                       retval);
1027                 limit_41++;
1028                 sd_simple_cmd(request, SD_APP_OP_COND, ocr, RESPONSE_R3);
1029             } else if (limit_41 < 100) {
1030                 limit_41++;
1031                 sd_simple_cmd(request, SD_APP_OP_COND, ocr, RESPONSE_R3);
1032             } else{
1033                 /* reset the card to idle*/
1034                 sd_simple_cmd(request, SD_GO_IDLE_STATE, 0, RESPONSE_NONE);
1035             }
1036             break;
1037
1038         case SD_APP_OP_COND:
1039             retval = sd_unpack_r3(request, &r3);
1040             if (retval)
1041             {
1042                 break;
1043             }
1044
1045             DEBUG("sd_init_card_state: read ocr value = 0x%08x", r3.ocr);
1046             card.ocr = r3.ocr;
1047
1048             if(!(r3.ocr & SD_CARD_BUSY || ocr == 0)){
1049                 udelay(10000);
1050                 sd_simple_cmd(request, SD_APP_CMD, 0, RESPONSE_R1);
1051             }
1052             else
1053             {
1054               /* Set the data bus width to 4 bits */
1055               use_4bit = 1;
1056               sd_simple_cmd(request, SD_ALL_SEND_CID, 0, RESPONSE_R2_CID);
1057             }
1058             break;
1059
1060         case SD_ALL_SEND_CID:
1061             for(i=0; i<4; i++)
1062                 card.cid[i] = ((request->response[1+i*4]<<24) | (request->response[2+i*4]<<16) |
1063                               (request->response[3+i*4]<< 8) | request->response[4+i*4]);
1064
1065             logf("CID: %08lx%08lx%08lx%08lx", card.cid[0], card.cid[1], card.cid[2], card.cid[3]);
1066             sd_simple_cmd(request, SD_SEND_RELATIVE_ADDR, 0, RESPONSE_R6);
1067             break;
1068         case SD_SEND_RELATIVE_ADDR:
1069             retval = sd_unpack_r6(request, &r1, &card.rca);
1070             card.rca = card.rca << 16;
1071             DEBUG("sd_init_card_state: Get RCA from SD: 0x%04x Status: %x", card.rca, r1.status);
1072             if (retval)
1073             {
1074                 DEBUG("sd_init_card_state: unable to SET_RELATIVE_ADDR error=%d",
1075                       retval);
1076                 return SD_INIT_FAILED;
1077             }
1078
1079             sd_simple_cmd(request, SD_SEND_CSD, card.rca, RESPONSE_R2_CSD);
1080             break;
1081
1082         case SD_SEND_CSD:
1083             for(i=0; i<4; i++)
1084                 card.csd[i] = ((request->response[1+i*4]<<24) | (request->response[2+i*4]<<16) |
1085                               (request->response[3+i*4]<< 8) | request->response[4+i*4]);
1086
1087             sd_parse_csd(&card);
1088             sd2_0 = (card_extract_bits(card.csd, 127, 2) == 1);
1089
1090             logf("CSD: %08lx%08lx%08lx%08lx", card.csd[0], card.csd[1], card.csd[2], card.csd[3]);
1091             DEBUG("SD card is ready");
1092             jz_sd_set_clock(SD_CLOCK_FAST);
1093             return SD_INIT_PASSED;
1094         default:
1095             DEBUG("sd_init_card_state: error!  Illegal last cmd %d", request->cmd);
1096             return SD_INIT_FAILED;
1097     }
1098
1099     return SD_INIT_DOING;
1100 }
1101
1102 static int sd_switch(struct sd_request *request, int mode, int group,
1103               unsigned char value, unsigned char * resp)
1104 {
1105     unsigned int arg;
1106
1107     mode = !!mode;
1108     value &= 0xF;
1109     arg = (mode << 31 | 0x00FFFFFF);
1110     arg &= ~(0xF << (group * 4));
1111     arg |= value << (group * 4);
1112     sd_send_cmd(request, 6, arg, 1, 64, RESPONSE_R1, resp);
1113
1114     return 0;
1115 }
1116
1117 /*
1118  * Fetches and decodes switch information
1119  */
1120 static int sd_read_switch(struct sd_request *request)
1121 {
1122     unsigned int status[64 / 4];
1123
1124     memset((unsigned char *)status, 0, 64);
1125     sd_switch(request, 0, 0, 1, (unsigned char*) status);
1126
1127     if (((unsigned char *)status)[13] & 0x02)
1128         return 0;
1129     else
1130         return 1;
1131 }
1132
1133 /*
1134  * Test if the card supports high-speed mode and, if so, switch to it.
1135  */
1136 static int sd_switch_hs(struct sd_request *request)
1137 {
1138     unsigned int status[64 / 4];
1139
1140     sd_switch(request, 1, 0, 1, (unsigned char*) status);
1141     return 0;
1142 }
1143
1144 int sd_select_card(void)
1145 {
1146     struct sd_request request;
1147     struct sd_response_r1 r1;
1148     int retval;
1149
1150     sd_simple_cmd(&request, SD_SELECT_CARD, card.rca,
1151                RESPONSE_R1B);
1152     retval = sd_unpack_r1(&request, &r1);
1153     if (retval)
1154         return retval;
1155
1156     if (sd2_0)
1157     {
1158         retval = sd_read_switch(&request);
1159         if (!retval)
1160         {
1161             sd_switch_hs(&request);
1162             jz_sd_set_clock(SD_CLOCK_HIGH);
1163         }
1164     }
1165     num_6 = 3;
1166     sd_simple_cmd(&request, SD_APP_CMD, card.rca,
1167                RESPONSE_R1);
1168     retval = sd_unpack_r1(&request, &r1);
1169     if (retval)
1170         return retval;
1171     sd_simple_cmd(&request, SD_SET_BUS_WIDTH, 2, RESPONSE_R1);
1172     retval = sd_unpack_r1(&request, &r1);
1173     if (retval)
1174         return retval;
1175
1176     return 0;
1177 }
1178
1179 int sd_init(void)
1180 {
1181     int retval;
1182     static bool inited = false;
1183     struct sd_request init_req;
1184     if(!inited)
1185     {
1186         jz_sd_hardware_init();
1187         wakeup_init(&sd_wakeup);
1188         num_6 = 0;
1189         inited = true;
1190     }
1191
1192     sd_simple_cmd(&init_req, SD_CIM_RESET,    0,     RESPONSE_NONE);
1193     sd_simple_cmd(&init_req, SD_GO_IDLE_STATE, 0,     RESPONSE_NONE);
1194
1195     while ((retval = sd_init_card_state(&init_req)) == SD_INIT_DOING);
1196
1197     if (retval == SD_INIT_PASSED)
1198         return sd_select_card();
1199     else
1200         return -1;
1201 }
1202
1203 static inline bool card_detect_target(void)
1204 {
1205     return (jz_sd_chkcard() == 1);
1206 }
1207
1208 #ifdef HAVE_HOTSWAP
1209 void card_enable_monitoring_target(bool on)
1210 {
1211     if(on)
1212     {
1213
1214     }
1215     else
1216     {
1217
1218     }
1219 }
1220 #endif
1221
1222 tCardInfo* card_get_info_target(int card_no)
1223 {
1224     (void)card_no;
1225     return &card;
1226 }
1227
1228 int sd_read_sectors(IF_MV2(int drive,) unsigned long start, int count, void* buf)
1229 {
1230 #ifdef HAVE_MULTIVOLUME
1231     (void)drive;
1232 #endif
1233     led(true);
1234
1235     struct sd_request request;
1236     struct sd_response_r1 r1;
1237     int retval;
1238
1239     if (!card_detect_target() || count == 0 || start > card.numblocks)
1240         return -1;
1241
1242     sd_simple_cmd(&request, SD_SEND_STATUS, card.rca, RESPONSE_R1);
1243     retval = sd_unpack_r1(&request, &r1);
1244     if (retval && (retval != SD_ERROR_STATE_MISMATCH))
1245         return retval;
1246
1247     sd_simple_cmd(&request, SD_SET_BLOCKLEN, SD_BLOCK_SIZE, RESPONSE_R1);
1248     if ((retval = sd_unpack_r1(&request, &r1)))
1249         return retval;
1250
1251     if (sd2_0)
1252     {
1253         sd_send_cmd(&request, SD_READ_MULTIPLE_BLOCK, start,
1254                      count, SD_BLOCK_SIZE, RESPONSE_R1, buf);
1255         if ((retval = sd_unpack_r1(&request, &r1)))
1256             return retval;
1257     }
1258     else
1259     {
1260         sd_send_cmd(&request, SD_READ_MULTIPLE_BLOCK,
1261                      start * SD_BLOCK_SIZE, count,
1262                      SD_BLOCK_SIZE, RESPONSE_R1, buf);
1263         if ((retval = sd_unpack_r1(&request, &r1)))
1264             return retval;
1265     }
1266
1267     last_disk_activity = current_tick;
1268
1269     sd_simple_cmd(&request, SD_STOP_TRANSMISSION, 0, RESPONSE_R1B);
1270     if ((retval = sd_unpack_r1(&request, &r1)))
1271         return retval;
1272
1273     led(false);
1274
1275     return retval;
1276 }
1277
1278 int sd_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const void* buf)
1279 {
1280 #ifdef HAVE_MULTIVOLUME
1281     (void)drive;
1282 #endif
1283     led(true);
1284
1285     struct sd_request request;
1286     struct sd_response_r1 r1;
1287     int retval;
1288
1289     if (!card_detect_target() || count == 0 || start > card.numblocks)
1290         return -1;
1291
1292     sd_simple_cmd(&request, SD_SEND_STATUS, card.rca, RESPONSE_R1);
1293     retval = sd_unpack_r1(&request, &r1);
1294     if (retval && (retval != SD_ERROR_STATE_MISMATCH))
1295         return retval;
1296
1297     sd_simple_cmd(&request, SD_SET_BLOCKLEN, SD_BLOCK_SIZE, RESPONSE_R1);
1298     if ((retval = sd_unpack_r1(&request, &r1)))
1299         return retval;
1300
1301     if (sd2_0)
1302     {
1303         sd_send_cmd(&request, SD_WRITE_MULTIPLE_BLOCK, start,
1304                  count, SD_BLOCK_SIZE, RESPONSE_R1,
1305                  (void*)buf);
1306         if ((retval = sd_unpack_r1(&request, &r1)))
1307             return retval;
1308     }
1309     else
1310     {
1311         sd_send_cmd(&request, SD_WRITE_MULTIPLE_BLOCK,
1312                  start * SD_BLOCK_SIZE, count,
1313                  SD_BLOCK_SIZE, RESPONSE_R1, (void*)buf);
1314         if ((retval = sd_unpack_r1(&request, &r1)))
1315             return retval;
1316     }
1317     sd_simple_cmd(&request, SD_STOP_TRANSMISSION, 0, RESPONSE_R1B);
1318     if ((retval = sd_unpack_r1(&request, &r1)))
1319         return retval;
1320
1321     led(false);
1322
1323     return retval;
1324 }
1325
1326 long sd_last_disk_activity(void)
1327 {
1328     return last_disk_activity;
1329 }
1330
1331 int sd_spinup_time(void)
1332 {
1333     return 0;
1334 }
1335
1336 void sd_enable(bool on)
1337 {
1338     (void)on;
1339 }
1340
1341 void sd_sleepnow(void)
1342 {
1343 }
1344
1345 /* TODO */
1346 bool sd_disk_is_active(void)
1347 {
1348     return false;
1349 }
1350
1351 int sd_soft_reset(void)
1352 {
1353     return 0;
1354 }
1355
1356 #ifdef HAVE_HOTSWAP
1357 bool sd_removable(IF_MV_NONVOID(int drive))
1358 {
1359 #ifdef HAVE_MULTIVOLUME
1360     (void)drive;
1361 #endif
1362     //return true;
1363     return false;
1364 }
1365 #endif
1366
1367 bool sd_present(IF_MV_NONVOID(int drive))
1368 {
1369 #ifdef HAVE_MULTIDRIVE
1370     (void)drive;
1371 #endif
1372     return card_detect_target();
1373 }
1374
1375 #ifdef CONFIG_STORAGE_MULTI
1376 int sd_num_drives(int first_drive)
1377 {
1378     /* We don't care which logical drive number(s) we have been assigned */
1379     (void)first_drive;
1380
1381     return 1;
1382 }
1383 #endif