firmware/target/arm/imx31/ccm-imx31.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (c) 2008 Michael Sevakis
  11  *
  12  * Clock control functions for IMX31 processor
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  20  * KIND, either express or implied.
  21  *
  22  ****************************************************************************/
  23 #include "system.h"
  24 #include "cpu.h"
  25 #include "ccm-imx31.h"
  26
  27 unsigned int ccm_get_src_pll(void)
  28 {
  29     return (CCM_PMCR0 & 0xC0000000) == 0 ? PLL_SERIAL : PLL_MCU;
  30 }
  31
  32 void ccm_module_clock_gating(enum IMX31_CG_LIST cg, enum IMX31_CG_MODES mode)
  33 {
  34     volatile unsigned long *reg;
  35     unsigned long mask;
  36     int shift;
  37
  38     if (cg >= CG_NUM_CLOCKS)
  39         return;
  40
  41     reg = &CCM_CGR0 + cg / 16;  /* Select CGR0, CGR1, CGR2 */
  42     shift = 2*(cg % 16);        /* Get field shift */
  43     mask = CG_MASK << shift;    /* Select field */
  44
  45     imx31_regmod32(reg, mode << shift, mask);
  46 }
  47
  48 /* Get the PLL reference clock frequency in HZ */
  49 unsigned int ccm_get_pll_ref_clk(void)
  50 {
  51     if ((CCM_CCMR & (3 << 1)) == (1 << 1))
  52         return CONFIG_CLK32_FREQ * 1024;
  53     else
  54         return CONFIG_HCLK_FREQ;
  55 }
  56
  57 /* Return PLL frequency in HZ */
  58 unsigned int ccm_get_pll(enum IMX31_PLLS pll)
  59 {
  60     uint32_t infreq = ccm_get_pll_ref_clk();
  61     uint32_t reg = (&CCM_MPCTL)[pll];
  62     uint32_t mfn = reg & 0x3ff;
  63     uint32_t pd  = ((reg >> 26) & 0xf) + 1;
  64     uint64_t mfd = ((reg >> 16) & 0x3ff) + 1;
  65     uint32_t mfi = (reg >> 10) & 0xf;
  66
  67     mfi = mfi <= 5 ? 5 : mfi;
  68
  69     return 2*infreq*(mfi * mfd + mfn) / (mfd * pd);
  70 }
  71
  72 unsigned int ccm_get_ipg_clk(void)
  73 {
  74     unsigned int pllnum = ccm_get_src_pll();
  75     unsigned int pll = ccm_get_pll(pllnum);
  76     uint32_t reg = CCM_PDR0;
  77     unsigned int max_pdf = ((reg >> 3) & 0x7) + 1;
  78     unsigned int ipg_pdf = ((reg >> 6) & 0x3) + 1;
  79
  80     return pll / (max_pdf * ipg_pdf);
  81 }
  82
  83 unsigned int ccm_get_ahb_clk(void)
  84 {
  85     unsigned int pllnum = ccm_get_src_pll();
  86     unsigned int pll = ccm_get_pll(pllnum);
  87     unsigned int max_pdf = ((CCM_PDR0 >> 3) & 0x7) + 1;
  88
  89     return pll / max_pdf;
  90 }
  91
  92 unsigned int ccm_get_ata_clk(void)
  93 {
  94     return ccm_get_ipg_clk();
  95 }