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i.MX31/Gigabeat S: Implement frequency and voltage scaling-- 1.6V for 528MHz, and...
[kugel-rb.git] / firmware / export / imx31l.h
blob66ae0acc4de7069e817bbd96cc784f2bdcb313b4
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2006 by James Espinoza
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21 #ifndef __IMX31L_H__
22 #define __IMX31L_H__
23
24 /* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/
25
26 #define REG8_PTR_T volatile unsigned char *
27 #define REG16_PTR_T volatile unsigned short *
28 #define REG32_PTR_T volatile unsigned long *
29
30 /* Place in the section with the framebuffer */
31 #define TTB_BASE_ADDR (CSD0_BASE_ADDR + (MEM*0x100000) - TTB_SIZE)
32 #define TTB_SIZE (0x4000)
33 #define IRAM_SIZE (0x4000)
34 #define TTB_BASE ((unsigned long *)TTB_BASE_ADDR)
35 #define FRAME_SIZE (240*320*2)
36 /* Rockbox framebuffer address, not retail OS */
37 #define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE)
38 #define FRAME ((void *)(FRAME_PHYS_ADDR-CSD0_BASE_ADDR))
39
40 #define DEVBSS_ATTR __attribute__((section(".devbss"),nocommon))
41 /* USBOTG */
42 #define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048)))
43 #define USB_NUM_ENDPOINTS 8
44 #define USB_DEVBSS_ATTR DEVBSS_ATTR
45 #define USB_BASE OTG_BASE_ADDR
46
47 /*
48 * AIPS 1
49 */
50 #define IRAM_BASE_ADDR 0x1fffc000
51 #define L2CC_BASE_ADDR 0x30000000
52 #define AIPS1_BASE_ADDR 0x43F00000
53 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
54 #define MAX_BASE_ADDR 0x43F04000
55 #define EVTMON_BASE_ADDR 0x43F08000
56 #define CLKCTL_BASE_ADDR 0x43F0C000
57 #define ETB_SLOT4_BASE_ADDR 0x43F10000
58 #define ETB_SLOT5_BASE_ADDR 0x43F14000
59 #define ECT_CTIO_BASE_ADDR 0x43F18000
60 #define I2C1_BASE_ADDR 0x43F80000
61 #define I2C3_BASE_ADDR 0x43F84000
62 #define OTG_BASE_ADDR 0x43F88000
63 #define ATA_BASE_ADDR 0x43F8C000
64 #define UART1_BASE_ADDR 0x43F90000
65 #define UART2_BASE_ADDR 0x43F94000
66 #define I2C2_BASE_ADDR 0x43F98000
67 #define OWIRE_BASE_ADDR 0x43F9C000
68 #define SSI1_BASE_ADDR 0x43FA0000
69 #define CSPI1_BASE_ADDR 0x43FA4000
70 #define KPP_BASE_ADDR 0x43FA8000
71 #define IOMUXC_BASE_ADDR 0x43FAC000
72 #define UART4_BASE_ADDR 0x43FB0000
73 #define UART5_BASE_ADDR 0x43FB4000
74 #define ECT_IP1_BASE_ADDR 0x43FB8000
75 #define ECT_IP2_BASE_ADDR 0x43FBC000
76
77 /*
78 * SPBA
79 */
80 #define SPBA_BASE_ADDR 0x50000000
81 #define MMC_SDHC1_BASE_ADDR 0x50004000
82 #define MMC_SDHC2_BASE_ADDR 0x50008000
83 #define UART3_BASE_ADDR 0x5000C000
84 #define CSPI2_BASE_ADDR 0x50010000
85 #define SSI2_BASE_ADDR 0x50014000
86 #define SIM_BASE_ADDR 0x50018000
87 #define IIM_BASE_ADDR 0x5001C000
88 #define ATA_DMA_BASE_ADDR 0x50020000
89 #define SPBA_CTRL_BASE_ADDR 0x5003C000
90
91 /*
92 * AIPS 2
93 */
94 #define AIPS2_BASE_ADDR 0x53F00000
95 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
96 #define CCM_BASE_ADDR 0x53F80000
97 #define CSPI3_BASE_ADDR 0x53F84000
98 #define FIRI_BASE_ADDR 0x53F8C000
99 #define GPT1_BASE_ADDR 0x53F90000
100 #define EPIT1_BASE_ADDR 0x53F94000
101 #define EPIT2_BASE_ADDR 0x53F98000
102 #define GPIO3_BASE_ADDR 0x53FA4000
103 #define SCC_BASE 0x53FAC000
104 #define SCM_BASE 0x53FAE000
105 #define SMN_BASE 0x53FAF000
106 #define RNGA_BASE_ADDR 0x53FB0000
107 #define IPU_CTRL_BASE_ADDR 0x53FC0000
108 #define AUDMUX_BASE 0x53FC4000
109 #define MPEG4_ENC_BASE 0x53FC8000
110 #define GPIO1_BASE_ADDR 0x53FCC000
111 #define GPIO2_BASE_ADDR 0x53FD0000
112 #define SDMA_BASE_ADDR 0x53FD4000
113 #define RTC_BASE_ADDR 0x53FD8000
114 #define WDOG_BASE_ADDR 0x53FDC000
115 #define PWM_BASE_ADDR 0x53FE0000
116 #define RTIC_BASE_ADDR 0x53FEC000
117
118 #define WDOG1_BASE_ADDR WDOG_BASE_ADDR
119 #define CRM_MCU_BASE_ADDR CCM_BASE_ADDR
120
121 /* IIM */
122 #define IIM_PREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x20))
123 #define IIM_PREV_SIG (0x1f << 3)
124 #define IIM_PREV_SIG_IMX31 (0x01 << 3) /* i.MX31 */
125 #define IIM_SREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x24))
126 #define IIM_SREV_SREV (0xff << 0)
127 #define IIM_SREV_1_0 0x00 /* i.MX31/L 1.0, L38W */
128 #define IIM_SREV_1_1 0x10 /* i.MX31 1.1, 2L38W */
129 #define IIM_SREV_1_1L 0x11 /* i.MX31L 1.1, 2L38W */
130 #define IIM_SREV_1_15 0x12 /* i.MX31 1.15, 2L38W/3L38W */
131 #define IIM_SREV_1_15L 0x13 /* i.MX31L 1.15, 2L38W/3L38W */
132 #define IIM_SREV_1_2 0x14 /* i.MX31 1.2, 3L38W, M45G */
133 #define IIM_SREV_1_2L 0x15 /* i.MX31L 1.2, 3L38W, M45G */
134 #define IIM_SREV_2_0_1 0x28 /* i.MX31 2.0/2.0.1, M91E */
135 #define IIM_SREV_2_0_1L 0x29 /* i.MX31L 2.0/2.0.1, M91E */
136
137 /* IOMUXC */
138 #define IOMUXC_GPR (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+0x008))
139
140 /* SW_MUX_CTL_* */
141 #define IOMUXC_MUX_OUT (0x7 << 4)
142 #define IOMUXC_MUX_OUT_POS (4)
143 #define IOMUXC_MUX_IN (0xf << 0)
144 #define IOMUXC_MUX_IN_POS (0)
145 #define IOMUXC_MUX_MASK (0x7f)
146
147 #define IOMUXC_MUX_OUT_GPIO (0x0 << IOMUXC_MUX_OUT_POS)
148 #define IOMUXC_MUX_OUT_FUNCTIONAL (0x1 << IOMUXC_MUX_OUT_POS)
149 #define IOMUXC_MUX_OUT_ALT1 (0x2 << IOMUXC_MUX_OUT_POS)
150 #define IOMUXC_MUX_OUT_ALT2 (0x3 << IOMUXC_MUX_OUT_POS)
151 #define IOMUXC_MUX_OUT_ALT3 (0x4 << IOMUXC_MUX_OUT_POS)
152 #define IOMUXC_MUX_OUT_ALT4 (0x5 << IOMUXC_MUX_OUT_POS)
153 #define IOMUXC_MUX_OUT_ALT5 (0x6 << IOMUXC_MUX_OUT_POS)
154 #define IOMUXC_MUX_OUT_ALT6 (0x7 << IOMUXC_MUX_OUT_POS)
155
156 #define IOMUXC_MUX_IN_NONE (0x0 << IOMUXC_MUX_IN_POS)
157 #define IOMUXC_MUX_IN_GPIO (0x1 << IOMUXC_MUX_IN_POS)
158 #define IOMUXC_MUX_IN_FUNCTIONAL (0x2 << IOMUXC_MUX_IN_POS)
159 #define IOMUXC_MUX_IN_ALT1 (0x4 << IOMUXC_MUX_IN_POS)
160 #define IOMUXC_MUX_IN_ALT2 (0x8 << IOMUXC_MUX_IN_POS)
161
162 /* SW_PAD_CTL_* */
163 #define IOMUXC_PAD_LOOPBACK (0x1 << 9) /* Route output to input */
164 /* Pullup, pulldown and keeper enable */
165 #define IOMUXC_PAD_PUE_PKE (0x3 << 7)
166 #define IOMUXC_PAD_PUE_PKE_DISABLE (0x0 << 7)
167 #define IOMUXC_PAD_PUE_PKE_DISABLE_2 (0x1 << 7) /* Same as 0x0 */
168 #define IOMUXC_PAD_PUE_PKE_KEEPER (0x2 << 7)
169 #define IOMUXC_PAD_PUE_PKE_PULLUPDOWN (0x3 << 7) /* Enb. Pull up or down */
170 /* Pullup/down resistance */
171 #define IOMUXC_PAD_PUS (0x3 << 5)
172 #define IOMUXC_PAD_PUS_DOWN_100K (0x0 << 5)
173 #define IOMUXC_PAD_PUS_UP_100K (0x1 << 5)
174 #if 0 /* Completeness */
175 #define IOMUXC_PAD_PUS_UP_47K (0x2 << 5) /* Not in IMX31/L */
176 #define IOMUXC_PAD_PUS_UP_22K (0x3 << 5) /* Not in IMX31/L */
177 #endif
178 #define IOMUXC_PAD_HYS (0x1 << 4) /* Schmitt trigger input */
179 #define IOMUXC_PAD_ODE (0x1 << 3) /* Open drain output 0=CMOS pushpull*/
180 #define IOMUXC_PAD_DSE (0x3 << 1)
181 #define IOMUXC_PAD_DSE_STD (0x0 << 1) /* Drive strength */
182 #define IOMUXC_PAD_DSE_HIGH (0x1 << 1)
183 #define IOMUXC_PAD_DSE_MAX (0x2 << 1)
184 #define IOMUXC_PAD_DSE_MAX_2 (0x3 << 1) /* Same as 0x2 */
185 #define IOMUXC_PAD_SRE (0x1 << 0) /* Slew rate, 1=fast */
186
187 #define IOMUXC_PAD_MASK (0x3ff)
188
189 /* RNGA */
190 #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00))
191
192 #define RNGA_CONTROL_SLEEP (1 << 4)
193
194 /* IPU */
195 #define IPU_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00))
196 #define IPU_CHA_BUF0_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04))
197 #define IPU_CHA_BUF1_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08))
198 #define IPU_CHA_DB_MODE_SEL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C))
199 #define IPU_CHA_CUR_BUF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10))
200 #define IPU_FS_PROC_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14))
201 #define IPU_FS_DISP_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18))
202 #define IPU_TASKS_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1C))
203 #define IPU_IMA_ADDR (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x20))
204 #define IPU_IMA_DATA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x24))
205 #define IPU_INT_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x28))
206 #define IPU_INT_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x2C))
207 #define IPU_INT_CTRL_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x30))
208 #define IPU_INT_CTRL_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x34))
209 #define IPU_INT_CTRL_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x38))
210 #define IPU_INT_STAT_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x3C))
211 #define IPU_INT_STAT_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x40))
212 #define IPU_INT_STAT_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x44))
213 #define IPU_INT_STAT_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x48))
214 #define IPU_INT_STAT_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x4C))
215 #define IPU_BRK_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x50))
216 #define IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54))
217 #define IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58))
218 #define IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60))
219 #define IPU_IDMAC_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA4))
220 #define IPU_IDMAC_CHA_EN (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA8))
221 #define IPU_IDMAC_CHA_PRI (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xAC))
222 #define IPU_IDMAC_CHA_BUSY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xB0))
223
224
225
226 /* ATA */
227 #define ATA_TIME_OFF (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00))
228 #define ATA_TIME_ON (*(REG8_PTR_T)(ATA_BASE_ADDR+0x01))
229 /* PIO */
230 #define ATA_TIME_1 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x02))
231 #define ATA_TIME_2W (*(REG8_PTR_T)(ATA_BASE_ADDR+0x03))
232 #define ATA_TIME_2R (*(REG8_PTR_T)(ATA_BASE_ADDR+0x04))
233 #define ATA_TIME_AX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x05))
234 #define ATA_TIME_PIO_RDX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x06))
235 #define ATA_TIME_4 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x07))
236 #define ATA_TIME_9 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x08))
237 /* MDMA */
238 #define ATA_TIME_M (*(REG8_PTR_T)(ATA_BASE_ADDR+0x09))
239 #define ATA_TIME_JN (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0A))
240 #define ATA_TIME_D (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0B))
241 #define ATA_TIME_K (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0C))
242 /* UDMA */
243 #define ATA_TIME_ACK (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0D))
244 #define ATA_TIME_ENV (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0E))
245 #define ATA_TIME_RPX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0F))
246 #define ATA_TIME_ZAH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x10))
247 #define ATA_TIME_MLIX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x11))
248 #define ATA_TIME_DVH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x12))
249 #define ATA_TIME_DZFS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x13))
250 #define ATA_TIME_DVS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x14))
251 #define ATA_TIME_CVH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x15))
252 #define ATA_TIME_SS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x16))
253 #define ATA_TIME_CYC (*(REG8_PTR_T)(ATA_BASE_ADDR+0x17))
254 /* */
255 #define ATA_FIFO_DATA_32 (*(REG32_PTR_T)(ATA_BASE_ADDR+0x18))
256 #define ATA_FIFO_DATA_16 (*(REG16_PTR_T)(ATA_BASE_ADDR+0x1c))
257 #define ATA_FIFO_FILL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x20))
258 /* Actually ATA_CONTROL but conflicts arise */
259 #define ATA_INTF_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x24))
260 #define ATA_INTERRUPT_PENDING (*(REG8_PTR_T)(ATA_BASE_ADDR+0x28))
261 #define ATA_INTERRUPT_ENABLE (*(REG8_PTR_T)(ATA_BASE_ADDR+0x2c))
262 #define ATA_INTERRUPT_CLEAR (*(REG8_PTR_T)(ATA_BASE_ADDR+0x30))
263 #define ATA_FIFO_ALARM (*(REG8_PTR_T)(ATA_BASE_ADDR+0x34))
264 #define ATA_DRIVE_DATA (*(REG16_PTR_T)(ATA_BASE_ADDR+0xA0))
265 #define ATA_DRIVE_FEATURES (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA4))
266 #define ATA_DRIVE_SECTOR_COUNT (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA8))
267 #define ATA_DRIVE_SECTOR_NUM (*(REG8_PTR_T)(ATA_BASE_ADDR+0xAC))
268 #define ATA_DRIVE_CYL_LOW (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB0))
269 #define ATA_DRIVE_CYL_HIGH (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB4))
270 #define ATA_DRIVE_CYL_HEAD (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB8))
271 #define ATA_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* rd */
272 #define ATA_DRIVE_COMMAND (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* wr */
273 #define ATA_ALT_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* rd */
274 #define ATA_DRIVE_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* wr */
275
276 /* ATA_INTF_CONTROL flags */
277 #define ATA_FIFO_RST (1 << 7)
278 #define ATA_ATA_RST (1 << 6)
279 #define ATA_FIFO_TX_EN (1 << 5)
280 #define ATA_FIFO_RCV_EN (1 << 4)
281 #define ATA_DMA_PENDING (1 << 3)
282 #define ATA_DMA_ULTRA_SELECTED (1 << 2)
283 #define ATA_DMA_WRITE (1 << 1)
284 #define ATA_IORDY_EN (1 << 0)
285
286 /* ATA_INTERRUPT_PENDING, ATA_INTERRUPT_ENABLE, ATA_INTERRUPT_CLEAR flags */
287 #define ATA_INTRQ1 (1 << 7) /* INTRQ to the DMA */
288 #define ATA_FIFO_UNDERFLOW (1 << 6)
289 #define ATA_FIFO_OVERFLOW (1 << 5)
290 #define ATA_CONTROLLER_IDLE (1 << 4)
291 #define ATA_INTRQ2 (1 << 3) /* INTRQ to the MCU */
292
293 /* EPIT */
294 #define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00))
295 #define EPITSR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x04))
296 #define EPITLR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x08))
297 #define EPITCMPR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x0C))
298 #define EPITCNT1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x10))
299
300 #define EPITCR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x00))
301 #define EPITSR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x04))
302 #define EPITLR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x08))
303 #define EPITCMPR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x0C))
304 #define EPITCNT2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x10))
305
306 #define EPITCR_CLKSRC_OFF (0 << 24)
307 #define EPITCR_CLKSRC_IPG_CLK (1 << 24)
308 #define EPITCR_CLKSRC_IPG_CLK_HIGHFREQ (2 << 24)
309 #define EPITCR_CLKSRC_IPG_CLK_32K (3 << 24)
310 #define EPITCR_OM_DISCONNECTED (0 << 22)
311 #define EPITCR_OM_TOGGLE (1 << 22)
312 #define EPITCR_OM_CLEAR (2 << 22)
313 #define EPITCR_OM_SET (3 << 22)
314 #define EPITCR_STOPEN (1 << 21)
315 #define EPITCR_DOZEN (1 << 20)
316 #define EPITCR_WAITEN (1 << 19)
317 #define EPITCR_DBGEN (1 << 18)
318 #define EPITCR_IOVW (1 << 17)
319 #define EPITCR_SWR (1 << 16)
320 #define EPITCR_PRESCALER (0xfff << 4) /* Divide by n+1 */
321 #define EPITCR_PRESCALER_POS (4)
322 #define EPITCR_RLD (1 << 3)
323 #define EPITCR_OCIEN (1 << 2)
324 #define EPITCR_ENMOD (1 << 1)
325 #define EPITCR_EN (1 << 0)
326
327 #define EPITSR_OCIF (1 << 0)
328
329 /* GPT */
330 #define GPTCR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x00))
331 #define GPTPR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x04))
332 #define GPTSR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x08))
333 #define GPTIR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x0C))
334 #define GPTOCR1 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x10))
335 #define GPTOCR2 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x14))
336 #define GPTOCR3 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x18))
337 #define GPTICR1 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x1C))
338 #define GPTICR2 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x20))
339 #define GPTCNT (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x24))
340
341 /* GPTCR */
342 #define GPTCR_FO3 (0x1 << 31)
343 #define GPTCR_FO2 (0x1 << 30)
344 #define GPTCR_FO1 (0x1 << 29)
345
346 #define GPTCR_OM3 (0x7 << 26)
347 #define GPTCR_OM3_DISCONNECTED (0x0 << 26)
348 #define GPTCR_OM3_TOGGLE (0x1 << 26)
349 #define GPTCR_OM3_CLEAR (0x2 << 26)
350 #define GPTCR_OM3_SET (0x3 << 26)
351 #define GPTCR_OM3_SINGLE_COUNT (0x4 << 26)
352 /* 0x5-0x7 same as 0x4 */
353
354 #define GPTCR_OM2 (0x7 << 23)
355 #define GPTCR_OM2_DISCONNECTED (0x0 << 23)
356 #define GPTCR_OM2_TOGGLE (0x1 << 23)
357 #define GPTCR_OM2_CLEAR (0x2 << 23)
358 #define GPTCR_OM2_SET (0x3 << 23)
359 #define GPTCR_OM2_SINGLE_COUNT (0x4 << 23)
360
361 /* 0x5-0x7 same as 0x4 */
362 #define GPTCR_OM1 (0x7 << 20)
363 #define GPTCR_OM1_DISCONNECTED (0x0 << 20)
364 #define GPTCR_OM1_TOGGLE (0x1 << 20)
365 #define GPTCR_OM1_CLEAR (0x2 << 20)
366 #define GPTCR_OM1_SET (0x3 << 20)
367 #define GPTCR_OM1_SINGLE_COUNT (0x4 << 20)
368
369 /* 0x5-0x7 same as 0x4 */
370 #define GPTCR_IM2 (0x3 << 18)
371 #define GPTCR_IM2_DISABLED (0x0 << 18)
372 #define GPTCR_IM2_RISING (0x1 << 18)
373 #define GPTCR_IM2_FALLING (0x2 << 18)
374 #define GPTCR_IM2_BOTH (0x3 << 18)
375
376 #define GPTCR_IM1 (0x3 << 16)
377 #define GPTCR_IM1_DISABLED (0x0 << 16)
378 #define GPTCR_IM1_RISING (0x1 << 16)
379 #define GPTCR_IM1_FALLING (0x2 << 16)
380 #define GPTCR_IM1_BOTH (0x3 << 16)
381
382 #define GPTCR_SWR (0x1 << 15)
383 #define GPTCR_FRR (0x1 << 9)
384
385 #define GPTCR_CLKSRC (0x7 << 6)
386 #define GPTCR_CLKSRC_NONE (0x0 << 6)
387 #define GPTCR_CLKSRC_IPG_CLK (0x1 << 6)
388 #define GPTCR_CLKSRC_IPG_CLK_HIGHFREQ (0x2 << 6)
389 #define GPTCR_CLKSRC_IPG_CLK_32K (0x4 << 6)
390 /* Other values not defined */
391
392 #define GPTCR_STOPEN (0x1 << 5)
393 #define GPTCR_DOZEN (0x1 << 4)
394 #define GPTCR_WAITEN (0x1 << 3)
395 #define GPTCR_DBGEN (0x1 << 2)
396 #define GPTCR_ENMODE (0x1 << 1)
397 #define GPTCR_EN (0x1 << 0)
398
399 /* GPTSR */
400 #define GPTSR_ROV (0x1 << 5)
401 #define GPTSR_IF2 (0x1 << 4)
402 #define GPTSR_IF1 (0x1 << 3)
403 #define GPTSR_OF3 (0x1 << 2)
404 #define GPTSR_OF2 (0x1 << 1)
405 #define GPTSR_OF1 (0x1 << 0)
406
407 /* GPTIR */
408 #define GPTIR_ROV (0x1 << 5)
409 #define GPTIR_IF2IE (0x1 << 4)
410 #define GPTIR_IF1IE (0x1 << 3)
411 #define GPTIR_OF3IE (0x1 << 2)
412 #define GPTIR_OF2IE (0x1 << 1)
413 #define GPTIR_OF1IE (0x1 << 0)
414
415 /* GPIO */
416 #define GPIO1_DR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00))
417 #define GPIO1_GDIR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04))
418 #define GPIO1_PSR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x08))
419 #define GPIO1_ICR1 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x0C))
420 #define GPIO1_ICR2 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x10))
421 #define GPIO1_IMR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x14))
422 #define GPIO1_ISR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x18))
423
424 #define GPIO2_DR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x00))
425 #define GPIO2_GDIR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x04))
426 #define GPIO2_PSR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x08))
427 #define GPIO2_ICR1 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x0C))
428 #define GPIO2_ICR2 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x10))
429 #define GPIO2_IMR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x14))
430 #define GPIO2_ISR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x18))
431
432 #define GPIO3_DR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x00))
433 #define GPIO3_GDIR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x04))
434 #define GPIO3_PSR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x08))
435 #define GPIO3_ICR1 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x0C))
436 #define GPIO3_ICR2 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x10))
437 #define GPIO3_IMR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14))
438 #define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18))
439
440 /* CSPI */
441 #define CSPI_RXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00))
442 #define CSPI_TXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04))
443 #define CSPI_CONREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08))
444 #define CSPI_INTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x0C))
445 #define CSPI_DMAREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x10))
446 #define CSPI_STATREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x14))
447 #define CSPI_PERIODREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x18))
448 #define CSPI_TESTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x1C0))
449
450 #define CSPI_RXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x00))
451 #define CSPI_TXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x04))
452 #define CSPI_CONREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x08))
453 #define CSPI_INTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x0C))
454 #define CSPI_DMAREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x10))
455 #define CSPI_STATREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x14))
456 #define CSPI_PERIODREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18))
457 #define CSPI_TESTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0))
458
459 #define CSPI_RXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x00))
460 #define CSPI_TXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x04))
461 #define CSPI_CONREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x08))
462 #define CSPI_INTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x0C))
463 #define CSPI_DMAREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x10))
464 #define CSPI_STATREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x14))
465 #define CSPI_PERIODREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x18))
466 #define CSPI_TESTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x1C0))
467
468 /* CSPI CONREG flags/fields */
469 #define CSPI_CONREG_CHIP_SELECT_SS0 (0 << 24)
470 #define CSPI_CONREG_CHIP_SELECT_SS1 (1 << 24)
471 #define CSPI_CONREG_CHIP_SELECT_SS2 (2 << 24)
472 #define CSPI_CONREG_CHIP_SELECT_SS3 (3 << 24)
473 #define CSPI_CONREG_CHIP_SELECT_MASK (3 << 24)
474 #define CSPI_CONREG_DRCTL_DONT_CARE (0 << 20)
475 #define CSPI_CONREG_DRCTL_TRIG_FALLING (1 << 20)
476 #define CSPI_CONREG_DRCTL_TRIG_LOW (2 << 20)
477 #define CSPI_CONREG_DRCTL_TRIG_RSV (3 << 20)
478 #define CSPI_CONREG_DRCTL_MASK (3 << 20)
479 #define CSPI_CONREG_DATA_RATE_DIV_4 (0 << 16)
480 #define CSPI_CONREG_DATA_RATE_DIV_8 (1 << 16)
481 #define CSPI_CONREG_DATA_RATE_DIV_16 (2 << 16)
482 #define CSPI_CONREG_DATA_RATE_DIV_32 (3 << 16)
483 #define CSPI_CONREG_DATA_RATE_DIV_64 (4 << 16)
484 #define CSPI_CONREG_DATA_RATE_DIV_128 (5 << 16)
485 #define CSPI_CONREG_DATA_RATE_DIV_256 (6 << 16)
486 #define CSPI_CONREG_DATA_RATE_DIV_512 (7 << 16)
487 #define CSPI_CONREG_DATA_RATE_DIV_MASK (7 << 16)
488 #define CSPI_BITCOUNT(n) ((n) << 8)
489 #define CSPI_CONREG_SSPOL (1 << 7)
490 #define CSPI_CONREG_SSCTL (1 << 6)
491 #define CSPI_CONREG_PHA (1 << 6)
492 #define CSPI_CONREG_POL (1 << 4)
493 #define CSPI_CONREG_SMC (1 << 3)
494 #define CSPI_CONREG_XCH (1 << 2)
495 #define CSPI_CONREG_MODE (1 << 1)
496 #define CSPI_CONREG_EN (1 << 0)
497
498 /* CSPI INTREG flags */
499 #define CSPI_INTREG_TCEN (1 << 8)
500 #define CSPI_INTREG_BOEN (1 << 7)
501 #define CSPI_INTREG_ROEN (1 << 6)
502 #define CSPI_INTREG_RFEN (1 << 5)
503 #define CSPI_INTREG_RHEN (1 << 4)
504 #define CSPI_INTREG_RREN (1 << 3)
505 #define CSPI_INTREG_TFEN (1 << 2)
506 #define CSPI_INTREG_THEN (1 << 1)
507 #define CSPI_INTREG_TEEN (1 << 0)
508
509 /* CSPI DMAREG flags */
510 #define CSPI_DMAREG_RFDEN (1 << 5)
511 #define CSPI_DMAREG_RHDEN (1 << 4)
512 #define CSPI_DMAREG_THDEN (1 << 1)
513 #define CSPI_DMAREG_TEDEN (1 << 0)
514
515 /* CSPI STATREG flags */
516 #define CSPI_STATREG_TC (1 << 8) /* w1c */
517 #define CSPI_STATREG_BO (1 << 7) /* w1c */
518 #define CSPI_STATREG_RO (1 << 6)
519 #define CSPI_STATREG_RF (1 << 5)
520 #define CSPI_STATREG_RH (1 << 4)
521 #define CSPI_STATREG_RR (1 << 3)
522 #define CSPI_STATREG_TF (1 << 2)
523 #define CSPI_STATREG_TH (1 << 1)
524 #define CSPI_STATREG_TE (1 << 0)
525
526 /* CSPI PERIODREG flags */
527 #define CSPI_PERIODREG_CSRC (1 << 15)
528
529 /* CSPI TESTREG flags */
530 #define CSPI_TESTREG_SWAP (1 << 15)
531 #define CSPI_TESTREG_LBC (1 << 14)
532
533 /* I2C */
534 #define I2C_IADR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x0))
535 #define I2C_IFDR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x4))
536 #define I2C_I2CR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x8))
537 #define I2C_I2SR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0xC))
538 #define I2C_I2DR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x10))
539
540 #define I2C_IADR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x0))
541 #define I2C_IFDR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x4))
542 #define I2C_I2CR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x8))
543 #define I2C_I2SR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0xC))
544 #define I2C_I2DR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x10))
545
546 #define I2C_IADR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x0))
547 #define I2C_IFDR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x4))
548 #define I2C_I2CR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x8))
549 #define I2C_I2SR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0xC))
550 #define I2C_I2DR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x10))
551
552 /* IADR - [7:1] Address */
553
554 /* IFDR */
555 #define I2C_IFDR_DIV30 0x00
556 #define I2C_IFDR_DIV32 0x01
557 #define I2C_IFDR_DIV36 0x02
558 #define I2C_IFDR_DIV42 0x03
559 #define I2C_IFDR_DIV48 0x04
560 #define I2C_IFDR_DIV52 0x05
561 #define I2C_IFDR_DIV60 0x06
562 #define I2C_IFDR_DIV72 0x07
563 #define I2C_IFDR_DIV80 0x08
564 #define I2C_IFDR_DIV88 0x09
565 #define I2C_IFDR_DIV104 0x0a
566 #define I2C_IFDR_DIV128 0x0b
567 #define I2C_IFDR_DIV144 0x0c
568 #define I2C_IFDR_DIV160 0x0d
569 #define I2C_IFDR_DIV192 0x0e
570 #define I2C_IFDR_DIV240 0x0f
571 #define I2C_IFDR_DIV288 0x10
572 #define I2C_IFDR_DIV320 0x11
573 #define I2C_IFDR_DIV384 0x12
574 #define I2C_IFDR_DIV480 0x13
575 #define I2C_IFDR_DIV576 0x14
576 #define I2C_IFDR_DIV640 0x15
577 #define I2C_IFDR_DIV768 0x16
578 #define I2C_IFDR_DIV960 0x17
579 #define I2C_IFDR_DIV1152 0x18
580 #define I2C_IFDR_DIV1280 0x19
581 #define I2C_IFDR_DIV1536 0x1a
582 #define I2C_IFDR_DIV1920 0x1b
583 #define I2C_IFDR_DIV2304 0x1c
584 #define I2C_IFDR_DIV2560 0x1d
585 #define I2C_IFDR_DIV3072 0x1e
586 #define I2C_IFDR_DIV3840 0x1f
587 #define I2C_IFDR_DIV22 0x20
588 #define I2C_IFDR_DIV24 0x21
589 #define I2C_IFDR_DIV26 0x22
590 #define I2C_IFDR_DIV28 0x23
591 #define I2C_IFDR_DIV32_2 0x24
592 #define I2C_IFDR_DIV36_2 0x25
593 #define I2C_IFDR_DIV40 0x26
594 #define I2C_IFDR_DIV44 0x27
595 #define I2C_IFDR_DIV48_2 0x28
596 #define I2C_IFDR_DIV56 0x29
597 #define I2C_IFDR_DIV64 0x2a
598 #define I2C_IFDR_DIV72_2 0x2b
599 #define I2C_IFDR_DIV80_2 0x2c
600 #define I2C_IFDR_DIV96 0x2d
601 #define I2C_IFDR_DIV112 0x2e
602 #define I2C_IFDR_DIV128_2 0x2f
603 #define I2C_IFDR_DIV160_2 0x30
604 #define I2C_IFDR_DIV192_2 0x31
605 #define I2C_IFDR_DIV224 0x32
606 #define I2C_IFDR_DIV256 0x33
607 #define I2C_IFDR_DIV320_2 0x34
608 #define I2C_IFDR_DIV384_2 0x35
609 #define I2C_IFDR_DIV448 0x36
610 #define I2C_IFDR_DIV512 0x37
611 #define I2C_IFDR_DIV640_2 0x38
612 #define I2C_IFDR_DIV768_2 0x39
613 #define I2C_IFDR_DIV896 0x3a
614 #define I2C_IFDR_DIV1024 0x3b
615 #define I2C_IFDR_DIV1280_2 0x3c
616 #define I2C_IFDR_DIV1536_2 0x3d
617 #define I2C_IFDR_DIV1792 0x3e
618 #define I2C_IFDR_DIV2048 0x3f
619
620 /* I2CR */
621 #define I2C_I2CR_IEN (1 << 7)
622 #define I2C_I2CR_IIEN (1 << 6)
623 #define I2C_I2CR_MSTA (1 << 5)
624 #define I2C_I2CR_MTX (1 << 4)
625 #define I2C_I2CR_TXAK (1 << 3)
626 #define I2C_I2CR_RSATA (1 << 2)
627
628 /* I2SR */
629 #define I2C_I2SR_ICF (1 << 7)
630 #define I2C_I2SR_IAAS (1 << 6)
631 #define I2C_I2SR_IBB (1 << 5)
632 #define I2C_I2SR_IAL (1 << 4)
633 #define I2C_I2SR_SRW (1 << 2)
634 #define I2C_I2SR_IIF (1 << 1)
635 #define I2C_I2SR_RXAK (1 << 0)
636
637 /* I2DR - [7:0] Data */
638
639 /* AUDMUX */
640 #define AUDMUX_PTCR1 (*(REG32_PTR_T)(AUDMUX_BASE+0x00))
641 #define AUDMUX_PDCR1 (*(REG32_PTR_T)(AUDMUX_BASE+0x04))
642 #define AUDMUX_PTCR2 (*(REG32_PTR_T)(AUDMUX_BASE+0x08))
643 #define AUDMUX_PDCR2 (*(REG32_PTR_T)(AUDMUX_BASE+0x0C))
644 #define AUDMUX_PTCR3 (*(REG32_PTR_T)(AUDMUX_BASE+0x10))
645 #define AUDMUX_PDCR3 (*(REG32_PTR_T)(AUDMUX_BASE+0x14))
646 #define AUDMUX_PTCR4 (*(REG32_PTR_T)(AUDMUX_BASE+0x18))
647 #define AUDMUX_PDCR4 (*(REG32_PTR_T)(AUDMUX_BASE+0x1C))
648 #define AUDMUX_PTCR5 (*(REG32_PTR_T)(AUDMUX_BASE+0x20))
649 #define AUDMUX_PDCR5 (*(REG32_PTR_T)(AUDMUX_BASE+0x24))
650 #define AUDMUX_PTCR6 (*(REG32_PTR_T)(AUDMUX_BASE+0x28))
651 #define AUDMUX_PDCR6 (*(REG32_PTR_T)(AUDMUX_BASE+0x2C))
652 #define AUDMUX_PTCR7 (*(REG32_PTR_T)(AUDMUX_BASE+0x30))
653 #define AUDMUX_PDCR7 (*(REG32_PTR_T)(AUDMUX_BASE+0x34))
654 #define AUDMUX_CNMCR (*(REG32_PTR_T)(AUDMUX_BASE+0x38))
655
656 #define AUDMUX_PTCR_TFS_DIR (1 << 31)
657
658 #define AUDMUX_PTCR_TFSEL (0xf << 27)
659 #define AUDMUX_PTCR_TFSEL_TXFS (0x0 << 27)
660 #define AUDMUX_PTCR_TFSEL_RXFS (0x8 << 27)
661 #define AUDMUX_PTCR_TFSEL_PORT1 (0x0 << 27)
662 #define AUDMUX_PTCR_TFSEL_PORT2 (0x1 << 27)
663 #define AUDMUX_PTCR_TFSEL_PORT3 (0x2 << 27)
664 #define AUDMUX_PTCR_TFSEL_PORT4 (0x3 << 27)
665 #define AUDMUX_PTCR_TFSEL_PORT5 (0x4 << 27)
666 #define AUDMUX_PTCR_TFSEL_PORT6 (0x5 << 27)
667 #define AUDMUX_PTCR_TFSEL_PORT7 (0x6 << 27)
668
669 #define AUDMUX_PTCR_TCLKDIR (1 << 26)
670
671 #define AUDMUX_PTCR_TCSEL (0xf << 22)
672 #define AUDMUX_PTCR_TCSEL_TXFS (0x0 << 22)
673 #define AUDMUX_PTCR_TCSEL_RXFS (0x8 << 22)
674 #define AUDMUX_PTCR_TCSEL_PORT1 (0x0 << 22)
675 #define AUDMUX_PTCR_TCSEL_PORT2 (0x1 << 22)
676 #define AUDMUX_PTCR_TCSEL_PORT3 (0x2 << 22)
677 #define AUDMUX_PTCR_TCSEL_PORT4 (0x3 << 22)
678 #define AUDMUX_PTCR_TCSEL_PORT5 (0x4 << 22)
679 #define AUDMUX_PTCR_TCSEL_PORT6 (0x5 << 22)
680 #define AUDMUX_PTCR_TCSEL_PORT7 (0x6 << 22)
681
682 #define AUDMUX_PTCR_RFS_DIR (1 << 21)
683
684 #define AUDMUX_PTCR_RFSSEL (0xf << 17)
685 #define AUDMUX_PTCR_RFSSEL_TXFS (0x0 << 17)
686 #define AUDMUX_PTCR_RFSSEL_RXFS (0x8 << 17)
687 #define AUDMUX_PTCR_RFSSEL_PORT1 (0x0 << 17)
688 #define AUDMUX_PTCR_RFSSEL_PORT2 (0x1 << 17)
689 #define AUDMUX_PTCR_RFSSEL_PORT3 (0x2 << 17)
690 #define AUDMUX_PTCR_RFSSEL_PORT4 (0x3 << 17)
691 #define AUDMUX_PTCR_RFSSEL_PORT5 (0x4 << 17)
692 #define AUDMUX_PTCR_RFSSEL_PORT6 (0x5 << 17)
693 #define AUDMUX_PTCR_RFSSEL_PORT7 (0x6 << 17)
694
695 #define AUDMUX_PTCR_RCLKDIR (1 << 16)
696
697 #define AUDMUX_PTCR_RCSEL (0xf << 12)
698 #define AUDMUX_PTCR_RCSEL_TXFS (0x0 << 12)
699 #define AUDMUX_PTCR_RCSEL_RXFS (0x8 << 12)
700 #define AUDMUX_PTCR_RCSEL_PORT1 (0x0 << 12)
701 #define AUDMUX_PTCR_RCSEL_PORT2 (0x1 << 12)
702 #define AUDMUX_PTCR_RCSEL_PORT3 (0x2 << 12)
703 #define AUDMUX_PTCR_RCSEL_PORT4 (0x3 << 12)
704 #define AUDMUX_PTCR_RCSEL_PORT5 (0x4 << 12)
705 #define AUDMUX_PTCR_RCSEL_PORT6 (0x5 << 12)
706 #define AUDMUX_PTCR_RCSEL_PORT7 (0x6 << 12)
707 #define AUDMUX_PTCR_SYN (1 << 11)
708
709 #define AUDMUX_PDCR_RXDSEL (0x7 << 13)
710 #define AUDMUX_PDCR_RXDSEL_PORT1 (0 << 13)
711 #define AUDMUX_PDCR_RXDSEL_PORT2 (1 << 13)
712 #define AUDMUX_PDCR_RXDSEL_PORT3 (2 << 13)
713 #define AUDMUX_PDCR_RXDSEL_PORT4 (3 << 13)
714 #define AUDMUX_PDCR_RXDSEL_PORT5 (4 << 13)
715 #define AUDMUX_PDCR_RXDSEL_PORT6 (5 << 13)
716 #define AUDMUX_PDCR_RXDSEL_PORT7 (6 << 13)
717 #define AUDMUX_PDCR_TXRXEN (1 << 12)
718
719 #define AUDMUX_CNMCR_BEN (1 << 18)
720 #define AUDMUX_CNMCR_FSPOL (1 << 17)
721 #define AUDMUX_CNMCR_CLKPOL (1 << 16)
722
723 #define AUDMUX_CNMCR_CNTHI (0xff << 8)
724 #define AUDMUX_CNMCR_CNTHI_POS (8)
725
726 #define AUDMUX_CNMCR_CNTLOW (0xff << 0)
727 #define AUDMUX_CNMCR_CNTLOW_POS (0)
728
729 /* SSI */
730 #define SSI_STX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x00))
731 #define SSI_STX1_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x04))
732 #define SSI_SRX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x08))
733 #define SSI_SRX1_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x0C))
734 #define SSI_SCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x10))
735 #define SSI_SISR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x14))
736 #define SSI_SIER1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x18))
737 #define SSI_STCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x1C))
738 #define SSI_SRCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x20))
739 #define SSI_STCCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x24))
740 #define SSI_SRCCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x28))
741 #define SSI_SFCSR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x2C))
742 #define SSI_SACNT1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x38))
743 #define SSI_SACADD1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x3C))
744 #define SSI_SACDAT1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x40))
745 #define SSI_SATAG1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x44))
746 #define SSI_STMSK1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x48))
747 #define SSI_SRMSK1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x4C))
748
749 #define SSI_STX0_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x00))
750 #define SSI_STX1_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x04))
751 #define SSI_SRX0_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x08))
752 #define SSI_SRX1_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x0C))
753 #define SSI_SCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x10))
754 #define SSI_SISR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x14))
755 #define SSI_SIER2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x18))
756 #define SSI_STCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x1C))
757 #define SSI_SRCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x20))
758 #define SSI_STCCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x24))
759 #define SSI_SRCCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x28))
760 #define SSI_SFCSR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x2C))
761 #define SSI_SACNT2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x38))
762 #define SSI_SACADD2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x3C))
763 #define SSI_SACDAT2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x40))
764 #define SSI_SATAG2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x44))
765 #define SSI_STMSK2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x48))
766 #define SSI_SRMSK2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x4C))
767
768 /* SSI SCR */
769 #define SSI_SCR_CLK_IST (0x1 << 9)
770 #define SSI_SCR_TCHN_EN (0x1 << 8)
771 #define SSI_SCR_SYS_CLK_EN (0x1 << 7)
772
773 #define SSI_SCR_I2S_MODE (0x3 << 5)
774 #define SSI_SCR_I2S_MODE_NORMAL (0x0 << 5)
775 #define SSI_SCR_I2S_MODE_MASTER (0x1 << 5)
776 #define SSI_SCR_I2S_MODE_SLAVE (0x2 << 5)
777 #define SSI_SCR_I2S_MODE_NOR2 (0x3 << 5)
778
779 #define SSI_SCR_SYN (0x1 << 4)
780 #define SSI_SCR_NET (0x1 << 3)
781 #define SSI_SCR_RE (0x1 << 2)
782 #define SSI_SCR_TE (0x1 << 1)
783 #define SSI_SCR_SSIEN (0x1 << 0)
784
785 /* SSI SISR */
786 #define SSI_SISR_CMDAU (0x1 << 18)
787 #define SSI_SISR_CMDDU (0x1 << 17)
788 #define SSI_SISR_RXT (0x1 << 16)
789 #define SSI_SISR_RDR1 (0x1 << 15)
790 #define SSI_SISR_RDR0 (0x1 << 14)
791 #define SSI_SISR_TDE1 (0x1 << 13)
792 #define SSI_SISR_TDE0 (0x1 << 12)
793 #define SSI_SISR_ROE1 (0x1 << 11)
794 #define SSI_SISR_ROE0 (0x1 << 10)
795 #define SSI_SISR_TUE1 (0x1 << 9)
796 #define SSI_SISR_TUE0 (0x1 << 8)
797 #define SSI_SISR_TFS (0x1 << 7)
798 #define SSI_SISR_RFS (0x1 << 6)
799 #define SSI_SISR_TLS (0x1 << 5)
800 #define SSI_SISR_RLS (0x1 << 4)
801 #define SSI_SISR_RFF1 (0x1 << 3)
802 #define SSI_SISR_RFF2 (0x1 << 2)
803 #define SSI_SISR_TFE1 (0x1 << 1)
804 #define SSI_SISR_TFE0 (0x1 << 0)
805
806 /* SSI SIER */
807 #define SSI_SIER_RDMAE (0x1 << 22)
808 #define SSI_SIER_RIE (0x1 << 21)
809 #define SSI_SIER_TDMAE (0x1 << 20)
810 #define SSI_SIER_TIE (0x1 << 19)
811 #define SSI_SIER_CMDAU (0x1 << 18)
812 #define SSI_SIER_CMDDU (0x1 << 17)
813 #define SSI_SIER_RXT (0x1 << 16)
814 #define SSI_SIER_RDR1 (0x1 << 15)
815 #define SSI_SIER_RDR0 (0x1 << 14)
816 #define SSI_SIER_TDE1 (0x1 << 13)
817 #define SSI_SIER_TDE0 (0x1 << 12)
818 #define SSI_SIER_ROE1 (0x1 << 11)
819 #define SSI_SIER_ROE0 (0x1 << 10)
820 #define SSI_SIER_TUE1 (0x1 << 9)
821 #define SSI_SIER_TUE0 (0x1 << 8)
822 #define SSI_SIER_TFS (0x1 << 7)
823 #define SSI_SIER_RFS (0x1 << 6)
824 #define SSI_SIER_TLS (0x1 << 5)
825 #define SSI_SIER_RLS (0x1 << 4)
826 #define SSI_SIER_RFF1 (0x1 << 3)
827 #define SSI_SIER_RFF0 (0x1 << 2)
828 #define SSI_SIER_TFE1 (0x1 << 1)
829 #define SSI_SIER_TFE0 (0x1 << 0)
830
831 /* SSI STCR */
832 #define SSI_STCR_TXBIT0 (0x1 << 9)
833 #define SSI_STCR_TFEN1 (0x1 << 8)
834 #define SSI_STCR_TFEN0 (0x1 << 7)
835 #define SSI_STCR_TFDIR (0x1 << 6)
836 #define SSI_STCR_TXDIR (0x1 << 5)
837 #define SSI_STCR_TSHFD (0x1 << 4)
838 #define SSI_STCR_TSCKP (0x1 << 3)
839 #define SSI_STCR_TFSI (0x1 << 2)
840 #define SSI_STCR_TFSL (0x1 << 1)
841 #define SSI_STCR_TEFS (0x1 << 0)
842
843 /* SSI SRCR */
844 #define SSI_SRCR_RXEXT (0x1 << 10)
845 #define SSI_SRCR_RXBIT0 (0x1 << 9)
846 #define SSI_SRCR_RFEN1 (0x1 << 8)
847 #define SSI_SRCR_RFEN0 (0x1 << 7)
848 #define SSI_SRCR_RFDIR (0x1 << 6)
849 #define SSI_SRCR_RXDIR (0x1 << 5)
850 #define SSI_SRCR_RSHFD (0x1 << 4)
851 #define SSI_SRCR_RSCKP (0x1 << 3)
852 #define SSI_SRCR_RFSI (0x1 << 2)
853 #define SSI_SRCR_RFSL (0x1 << 1)
854 #define SSI_SRCR_REFS (0x1 << 0)
855
856 /* SSI STCCR/SRCCR */
857 #define SSI_STRCCR_DIV2 (0x1 << 18)
858 #define SSI_STRCCR_PSR (0x1 << 17)
859
860 #define SSI_STRCCR_WL (0xf << 13)
861 #define SSI_STRCCR_WL8 (0x3 << 13)
862 #define SSI_STRCCR_WL10 (0x4 << 13)
863 #define SSI_STRCCR_WL12 (0x5 << 13)
864 #define SSI_STRCCR_WL16 (0x7 << 13)
865 #define SSI_STRCCR_WL18 (0x8 << 13)
866 #define SSI_STRCCR_WL20 (0x9 << 13)
867 #define SSI_STRCCR_WL22 (0xa << 13)
868 #define SSI_STRCCR_WL24 (0xb << 13)
869
870 #define SSI_STRCCR_DC (0x1f << 8)
871 #define SSI_STRCCR_DC_POS (8)
872
873 #define SSI_STRCCR_PM (0xf << 0)
874 #define SSI_STRCCR_PM_POS (0)
875
876 /* SSI SFCSR */
877 #define SSI_SFCSR_RFCNT1 (0xf << 28)
878 #define SSI_SFCSR_RFCNT1_POS (28)
879
880 #define SSI_SFCSR_TFCNT1 (0xf << 24)
881 #define SSI_SFCSR_TFCNN1_POS (24)
882
883 #define SSI_SFCSR_RFWM1 (0xf << 20)
884 #define SSI_SFCSR_RFWM1_POS (20)
885
886 #define SSI_SFCSR_TFWM1 (0xf << 16)
887 #define SSI_SFCSR_TFWM1_POS (16)
888
889 #define SSI_SFCSR_RFCNT0 (0xf << 12)
890 #define SSI_SFCSR_RFCNT0_POS (12)
891
892 #define SSI_SFCSR_TFCNT0 (0xf << 8)
893 #define SSI_SFCSR_TFCNT0_POS (8)
894
895 #define SSI_SFCSR_RFWM0 (0xf << 4)
896 #define SSI_SFCSR_RFWM0_POS (4)
897
898 #define SSI_SFCSR_TFWM0 (0xf << 0)
899 #define SSI_SFCSR_TFWM0_POS (0)
900
901 /* SACNT */
902 #define SSI_SACNT_FRDIV (0x3f << 5)
903 #define SSI_SACNT_FRDIV_POS (5)
904
905 #define SSI_SACNT_WR (0x1 << 4)
906 #define SSI_SACNT_RD (0x1 << 3)
907 #define SSI_SACNT_TIF (0x1 << 2)
908 #define SSI_SACNT_FV (0x1 << 1)
909 #define SSI_SACNT_AC97EN (0x1 << 0)
910
911 /* RTC */
912 #define RTC_HOURMIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00))
913 #define RTC_SECONDS (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04))
914 #define RTC_ALRM_HM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08))
915 #define RTC_ALRM_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C))
916 #define RTC_CTL (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10))
917 #define RTC_ISR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14))
918 #define RTC_IENR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18))
919 #define RTC_STPWCH (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C))
920 #define RTC_DAYR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20))
921 #define RTC_DAYALARM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24))
922
923 /* Watchdog */
924 #define WDOG_WCR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x00))
925 #define WDOG_WSR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x02))
926 #define WDOG_WRSR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x04))
927
928 #define WDOG_WCR_WT (0xff << 8)
929 #define WDOG_WCR_WT_POS (8)
930
931 #define WDOG_WCR_WOE (0x1 << 6)
932 #define WDOG_WCR_WDA (0x1 << 5)
933 #define WDOG_WCR_SRS (0x1 << 4)
934 #define WDOG_WCR_WRE (0x1 << 3)
935 #define WDOG_WCR_WDE (0x1 << 2)
936 #define WDOG_WCR_WDBG (0x1 << 1)
937 #define WDOG_WCR_WDZST (0x1 << 0)
938
939 #define WDOG_WRSR_JRST (0x1 << 5)
940 #define WDOG_WRSR_PWR (0x1 << 4)
941 #define WDOG_WRSR_EXT (0x1 << 3)
942 #define WDOG_WRSR_CMON (0x1 << 2)
943 #define WDOG_WRSR_TOUT (0x1 << 1)
944 #define WDOG_WRSR_SFTW (0x1 << 0)
945
946 /* Keypad */
947 #define KPP_KPCR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x0))
948 #define KPP_KPSR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x2))
949 #define KPP_KDDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4))
950 #define KPP_KPDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6))
951
952 /* KPP_KPSR bits */
953 #define KPP_KPSR_KRIE (1 << 9)
954 #define KPP_KPSR_KDIE (1 << 8)
955 #define KPP_KPSR_KRSS (1 << 3)
956 #define KPP_KPSR_KDSC (1 << 2)
957 #define KPP_KPSR_KPKR (1 << 1)
958 #define KPP_KPSR_KPKD (1 << 0)
959
960 /* SDHC */
961 #define SDHC1_CLOCK_CONTROL (*(REG32_PTR_T)(MMC_SDHC1_BASE_ADDR+0x00))
962 #define SDHC2_CLOCK_CONTROL (*(REG32_PTR_T)(MMC_SDHC2_BASE_ADDR+0x00))
963
964 /* SDHC bits */
965 #define STOP_CLK (1 << 0)
966
967 /* ROMPATCH and AVIC */
968 #define ROMPATCH_BASE_ADDR 0x60000000
969
970 /* Since AVIC vector registers are NOT used, we reserve some for various
971 * purposes. Copied from Linux source code. */
972 #define CHIP_REV_1_0 0x10
973 #define CHIP_REV_2_0 0x20
974 #define SYSTEM_REV_ID_REG (AVIC_BASE_ADDR + AVIC_VEC_1)
975 #define SYSTEM_REV_ID_MAG 0xF00C
976
977 /*
978 * NAND, SDRAM, WEIM, M3IF, EMI controllers
979 */
980 #define EXT_MEM_CTRL_BASE 0xB8000000
981 #define NFC_BASE EXT_MEM_CTRL_BASE
982 #define ESDCTL_BASE 0xB8001000
983 #define WEIM_BASE_ADDR 0xB8002000
984 #define WEIM_CTRL_CS0 (WEIM_BASE_ADDR+0x00)
985 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR+0x10)
986 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR+0x20)
987 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR+0x30)
988 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR+0x40)
989 #define M3IF_BASE 0xB8003000
990 #define PCMCIA_CTL_BASE 0xB8004000
991
992 /*
993 * Memory regions and CS
994 */
995 #define IPU_MEM_BASE_ADDR 0x70000000
996 #define CSD0_BASE_ADDR 0x80000000
997 #define CSD1_BASE_ADDR 0x90000000
998 #define CS0_BASE_ADDR 0xA0000000
999 #define CS1_BASE_ADDR 0xA8000000
1000 #define CS2_BASE_ADDR 0xB0000000
1001 #define CS3_BASE_ADDR 0xB2000000
1002 #define CS4_BASE_ADDR 0xB4000000
1003 #define CS4_BASE_PSRAM 0xB5000000
1004 #define CS5_BASE_ADDR 0xB6000000
1005 #define PCMCIA_MEM_BASE_ADDR 0xC0000000
1006
1007 #define INTERNAL_ROM_VA 0xF0000000
1008
1009 /*
1010 * SDRAM
1011 */
1012 #define RAM_BANK0_BASE SDRAM_BASE_ADDR
1013
1014 /*
1015 * IRQ Controller Register Definitions.
1016 */
1017 #define AVIC_BASE_ADDR 0x68000000
1018 #define AVIC_INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
1019 #define AVIC_NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
1020 #define AVIC_INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
1021 #define AVIC_INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
1022 #define AVIC_INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
1023 #define AVIC_INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
1024 #define AVIC_INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
1025 #define AVIC_INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
1026 #define AVIC_NIPRIORITY(n) (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n])
1027 #define AVIC_NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
1028 #define AVIC_NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
1029 #define AVIC_NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
1030 #define AVIC_NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
1031 #define AVIC_NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
1032 #define AVIC_NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
1033 #define AVIC_NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
1034 #define AVIC_NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
1035 #define AVIC_NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
1036 #define AVIC_FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
1037 #define AVIC_INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
1038 #define AVIC_INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
1039 #define AVIC_INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
1040 #define AVIC_INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
1041 #define AVIC_NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
1042 #define AVIC_NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
1043 #define AVIC_FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
1044 #define AVIC_FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
1045 #define AVIC_VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100)
1046 #define AVIC_VECTOR(n) (((REG32_PTR_T)VECTOR_BASE_ADDR)[n])
1047
1048 /* The vectors go all the way up to 63. 4 bytes for each */
1049 #define AVIC_INTCNTL_ABFLAG (1 << 25)
1050 #define AVIC_INTCNTL_ABFEN (1 << 24)
1051 #define AVIC_INTCNTL_NIDIS (1 << 22)
1052 #define AVIC_INTCNTL_FIDIS (1 << 21)
1053 #define AVIC_INTCNTL_NIAD (1 << 20)
1054 #define AVIC_INTCNTL_FIAD (1 << 19)
1055 #define AVIC_INTCNTL_NM (1 << 18)
1056
1057 /* L210 */
1058 #define L2CC_BASE_ADDR 0x30000000
1059 #define L2_CACHE_LINE_SIZE 32
1060 #define L2_CACHE_CTL_REG 0x100
1061 #define L2_CACHE_AUX_CTL_REG 0x104
1062 #define L2_CACHE_SYNC_REG 0x730
1063 #define L2_CACHE_INV_LINE_REG 0x770
1064 #define L2_CACHE_INV_WAY_REG 0x77C
1065 #define L2_CACHE_CLEAN_LINE_REG 0x7B0
1066 #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
1067
1068 #define L2CC_CACHE_SYNC (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG))
1069
1070 /* CCM */
1071 #define CCM_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
1072 #define CCM_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
1073 #define CCM_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
1074 #define CCM_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
1075 #define CCM_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
1076 #define CCM_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
1077 #define CCM_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
1078 #define CCM_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
1079 #define CCM_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
1080 #define CCM_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
1081 #define CCM_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
1082 #define CCM_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
1083 #define CCM_LDC (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30))
1084 #define CCM_DCVR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34))
1085 #define CCM_DCVR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38))
1086 #define CCM_DCVR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C))
1087 #define CCM_DCVR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40))
1088 #define CCM_LTR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44))
1089 #define CCM_LTR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48))
1090 #define CCM_LTR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C))
1091 #define CCM_LTR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50))
1092 #define CCM_LTBR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54))
1093 #define CCM_LTBR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58))
1094 #define CCM_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
1095 #define CCM_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60))
1096 #define CCM_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
1097
1098 /* CCMR */
1099 #define CCM_CCMR_L2PG (0x1 << 29)
1100 #define CCM_CCMR_VSTBY (0x1 << 28)
1101 #define CCM_CCMR_WBEN (0x1 << 27)
1102 #define CCM_CCMR_FPMF (0x1 << 26)
1103 #define CCM_CCMR_CSCS (0x1 << 25)
1104 #define CCM_CCMR_PERCS (0x1 << 24)
1105
1106 #define CCM_CCMR_SSI2S (0x3 << 21)
1107 #define CCM_CCMR_SSI2S_MCU_CLK (0x0 << 21)
1108 #define CCM_CCMR_SSI2S_USB_CLK (0x1 << 21)
1109 #define CCM_CCMR_SSI2S_SERIAL_CLK (0x2 << 21) /* default */
1110
1111 #define CCM_CCMR_SSI1S (0x3 << 18)
1112 #define CCM_CCMR_SSI1S_MCU_CLK (0x0 << 18)
1113 #define CCM_CCMR_SSI1S_USB_CLK (0x1 << 18)
1114 #define CCM_CCMR_SSI1S_SERIAL_CLK (0x2 << 18) /* default */
1115
1116 #define CCM_CCMR_RAMW (0x3 << 16)
1117 #define CCM_CCMR_RAMW_0ARM_0ALTMS (0x0 << 16)
1118 #define CCM_CCMR_RAMW_0ARM_1ALTMS (0x1 << 16) /* Not recommended */
1119 #define CCM_CCMR_RAMW_1ARM_0ALTMS (0x2 << 16) /* Not recommended */
1120 #define CCM_CCMR_RAMW_1ARM_1ALTMS (0x3 << 16)
1121
1122 #define CCM_CCMR_LPM (0x3 << 14)
1123 #define CCM_CCMR_LPM_WAIT_MODE (0x0 << 14)
1124 #define CCM_CCMR_LPM_DOZE_MODE (0x1 << 14)
1125 #define CCM_CCMR_LPM_SRM (0x2 << 14) /* State retention mode */
1126 #define CCM_CCMR_LPM_DSM (0x3 << 14) /* Deep sleep mode */
1127
1128 #define CCM_CCMR_FIRS (0x3 << 11)
1129 #define CCM_CCMR_FIRS_MCU_CLK (0x0 << 11)
1130 #define CCM_CCMR_FIRS_USB_CLK (0x1 << 11)
1131 #define CCM_CCMR_FIRS_SERIAL_CLK (0x2 << 11)
1132
1133 #define CCM_CCMR_WAMO (0x1 << 10)
1134 #define CCM_CCMR_UPE (0x1 << 9)
1135 #define CCM_CCMR_SPE (0x1 << 8)
1136 #define CCM_CCMR_MDS (0x1 << 7)
1137
1138 #define CCM_CCMR_ROMW (0x3 << 5)
1139 #define CCM_CCMR_ROMW_0ARM_0ALTMS (0x0 << 5)
1140 #define CCM_CCMR_ROMW_0ARM_1ALTMS (0x1 << 5) /* Not recommended */
1141 #define CCM_CCMR_ROMW_1ARM_0ALTMS (0x2 << 5) /* Not recommended */
1142 #define CCM_CCMR_ROMW_1ARM_1ALTMS (0x3 << 5)
1143
1144 #define CCM_CCMR_SBYCS (0x1 << 4)
1145 #define CCM_CCMR_MPE (0x1 << 3)
1146
1147 #define CCM_CCMR_PRCS (0x3 << 1)
1148 #define CCM_CCMR_PRCS_FPM (0x1 << 1)
1149 #define CCM_CCMR_PRCS_CKIH (0x2 << 1)
1150
1151 #define CCM_CCMR_FPME (0x1 << 0)
1152
1153 /* PDR0 */
1154 #define CCM_PDR0_CSI_PODF (0x1ff << 23)
1155 #define CCM_PDR0_CSI_PODF_POS (23)
1156
1157 #define CCM_PDR0_PER_PODF (0x1f << 16)
1158 #define CCM_PDR0_PER_PODF_POS (16)
1159
1160 #define CCM_PDR0_HSP_PODF (0x7 << 11)
1161 #define CCM_PDR0_HSP_PODF_POS (11)
1162
1163 #define CCM_PDR0_NFC_PODF (0x7 << 8)
1164 #define CCM_PDR0_NFC_PODF_POS (8)
1165
1166 #define CCM_PDR0_IPG_PODF (0x3 << 6)
1167 #define CCM_PDR0_IPG_PODF_POS (6)
1168
1169 #define CCM_PDR0_MAX_PODF (0x7 << 3)
1170 #define CCM_PDR0_MAX_PODF_POS (3)
1171
1172 #define CCM_PDR0_MCU_PODF (0x7 << 0)
1173 #define CCM_PDR0_MCU_PODF_POS (0)
1174
1175 /* PDR1 */
1176 #define CCM_PDR1_USB_PRDF (0x3 << 30)
1177 #define CCM_PDR1_USB_PRDF_POS (30)
1178
1179 #define CCM_PDR1_USB_PODF (0x7 << 27)
1180 #define CCM_PDR1_USB_PODF_POS (27)
1181
1182 #define CCM_PDR1_FIRI_PRE_PODF (0x7 << 24)
1183 #define CCM_PDR1_FIRI_PRE_PODF_POS (24)
1184
1185 #define CCM_PDR1_FIRI_PODF (0x3f << 18)
1186 #define CCM_PDR1_FIRI_PODF_POS (18)
1187
1188 #define CCM_PDR1_SSI2_PRE_PODF (0x7 << 15)
1189 #define CCM_PDR1_SSI2_PRE_PODF_POS (15)
1190
1191 #define CCM_PDR1_SSI2_PODF (0x3f << 9)
1192 #define CCM_PDR1_SSI2_PODF_POS (9)
1193
1194 #define CCM_PDR1_SSI1_PRE_PODF (0x7 << 6)
1195 #define CCM_PDR1_SSI1_PRE_PODF_POS (6)
1196
1197 #define CCM_PDR1_SSI1_PODF (0x3f << 0)
1198 #define CCM_PDR1_SSI1_PODF_POS (0)
1199
1200 /* RCSR */
1201 #define CCM_RCSR_NF16B (1 << 31)
1202
1203 #define CCM_RCSR_NFMS (1 << 30)
1204
1205 #define CCM_RCSR_BTP4 (1 << 27)
1206 #define CCM_RCSR_BTP3 (1 << 26)
1207 #define CCM_RCSR_BTP2 (1 << 25)
1208 #define CCM_RCSR_BTP1 (1 << 24)
1209 #define CCM_RCSR_BTP0 (1 << 23)
1210
1211 #define CCM_RCSR_OSCNT (0x7f << 16)
1212 #define CCM_RCSR_OSCNT_POS (16)
1213
1214 #define CCM_RCSR_PERES (1 << 15)
1215
1216 #define CCM_RCSR_SDM (0x3 << 12)
1217 #define CCM_RCSR_SDM_POS (12)
1218
1219 #define CCM_RCSR_GPF (0x7 << 5)
1220 #define CCM_RCSR_GPF_POS (5)
1221
1222 #define CCM_RCSR_WFIS (1 << 4)
1223
1224 #define CCM_RCSR_REST (0x7 << 0)
1225 #define CCM_RCSR_REST_POS (0)
1226 #define CCM_RCSR_REST_POR_EXT (0x0)
1227 #define CCM_RCSR_REST_QUALIFIED_EXT (0x1)
1228 #define CCM_RCSR_REST_WATCHDOG_TMO (0x2)
1229 /* 0x3 - 0x5: reserved */
1230 #define CCM_RCSR_REST_JTAG (0x6)
1231 #define CCM_RCSR_REST_ARM11P_GATING (0x7)
1232
1233 /* MPCTL */
1234 #define CCM_MPCTL_BRM (1 << 31)
1235 #define CCM_MPCTL_PD (0xf << 26)
1236 #define CCM_MPCTL_PD_POS (26)
1237 #define CCM_MPCTL_MFD (0x3ff << 16)
1238 #define CCM_MPCTL_MFD_POS (16)
1239 #define CCM_MPCTL_MFI (0xf << 10)
1240 #define CCM_MPCTL_MFI_POS (10)
1241 #define CCM_MPCTL_MFN (0x3ff << 0)
1242 #define CCM_MPCTL_MFN_POS (0)
1243
1244 /* UPCTL */
1245 #define CCM_UPCTL_BRM (1 << 31)
1246 #define CCM_UPCTL_PD (0xf << 26)
1247 #define CCM_UPCTL_PD_POS (26)
1248 #define CCM_UPCTL_MFD (0x3ff << 16)
1249 #define CCM_UPCTL_MFD_POS (16)
1250 #define CCM_UPCTL_MFI (0xf << 10)
1251 #define CCM_UPCTL_MFI_POS (10)
1252 #define CCM_UPCTL_MFN (0x3ff << 0)
1253 #define CCM_UPCTL_MFN_POS (0)
1254
1255 /* SPCTL */
1256 #define CCM_SPCTL_BRM (1 << 31)
1257 #define CCM_SPCTL_PD (0xf << 26)
1258 #define CCM_SPCTL_PD_POS (26)
1259 #define CCM_SPCTL_MFD (0x3ff << 16)
1260 #define CCM_SPCTL_MFD_POS (16)
1261 #define CCM_SPCTL_MFI (0xf << 10)
1262 #define CCM_SPCTL_MFI_POS (10)
1263 #define CCM_SPCTL_MFN (0x3ff << 0)
1264 #define CCM_SPCTL_MFN_POS (0)
1265
1266 /* COSR */
1267 #define CCM_COSR_CLKOEN (1 << 9)
1268 #define CCM_COSR_CLKOUTDIV (0x7 << 6)
1269 #define CCM_COSR_CLKOUTDIV_POS (6)
1270 #define CCM_COSR_CLKOSEL (0xf << 0)
1271 #define CCM_COSR_CLKOSEL_POS (0)
1272 #define CCM_COSR_CLKOSEL_MPL_DPDGCK_CLK (0x0)
1273 #define CCM_COSR_CLKOSEL_IPG_CLK_CCM (0x1)
1274 #define CCM_COSR_CLKOSEL_UPL_DPDGCK_CLK (0x2)
1275 #define CCM_COSR_CLKOSEL_PLL_REF_CLK (0x3)
1276 #define CCM_COSR_CLKOSEL_FPM_CKIL512_CLK (0x4)
1277 #define CCM_COSR_CLKOSEL_IPG_CLK_AHB_ARM (0x5)
1278 #define CCM_COSR_CLKOSEL_IPG_CLK_ARM (0x6)
1279 #define CCM_COSR_CLKOSEL_SPL_DPDGCK_CLK (0x7)
1280 #define CCM_COSR_CLKOSEL_CKIH (0x8)
1281 #define CCM_COSR_CLKOSEL_IPG_CLK_AHB_EMI_CLK (0x9)
1282 #define CCM_COSR_CLKOSEL_IPG_CLK_IPU_HSP (0x9)
1283 #define CCM_COSR_CLKOSEL_IPG_CLK_NFC_20M (0xa)
1284 #define CCM_COSR_CLKOSEL_IPG_CLK_PERCLK_UART1 (0xb)
1285 #define CCM_COSR_CLKOSEL_IPG_REF_CIR1 (0xc) /* ref_cir_gateload */
1286 #define CCM_COSR_CLKOSEL_IPG_REF_CIR2 (0xc) /* ref_cir_intrcload */
1287 #define CCM_COSR_CLKOSEL_IPG_REF_CIR3 (0xc) /* ref_cir_path */
1288
1289 /* CGR0 */
1290 /* CGR1 */
1291 /* CGR2 */
1292 /* Handled in ccm-imx31.h and ccm-imx31.c */
1293
1294
1295 #define CCM_WIMR0_GPIO3 (1 << 0)
1296 #define CCM_WIMR0_GPIO2 (1 << 1)
1297 #define CCM_WIMR0_GPIO1 (1 << 2)
1298 #define CCM_WIMR0_PCMCIA (1 << 3)
1299 #define CCM_WIMR0_WDT (1 << 4)
1300 #define CCM_WIMR0_USB_OTG (1 << 5)
1301 #define CCM_WIMR0_IPI_INT_UH2 (1 << 6)
1302 #define CCM_WIMR0_IPI_INT_UH1 (1 << 7)
1303 #define CCM_WIMR0_IPI_INT_UART5_ANDED (1 << 8)
1304 #define CCM_WIMR0_IPI_INT_UART4_ANDED (1 << 9)
1305 #define CCM_WIMR0_IPI_INT_UART3_ANDED (1 << 10)
1306 #define CCM_WIMR0_IPI_INT_UART2_ANDED (1 << 11)
1307 #define CCM_WIMR0_IPI_INT_UART1_ANDED (1 << 12)
1308 #define CCM_WIMR0_IPI_INT_SIM_DATA_IRQ (1 << 13)
1309 #define CCM_WIMR0_IPI_INT_SDHC2 (1 << 14)
1310 #define CCM_WIMR0_IPI_INT_SDHC1 (1 << 15)
1311 #define CCM_WIMR0_IPI_INT_RTC (1 << 16)
1312 #define CCM_WIMR0_IPI_INT_PWM (1 << 17)
1313 #define CCM_WIMR0_IPI_INT_KPP (1 << 18)
1314 #define CCM_WIMR0_IPI_INT_IIM (1 << 19)
1315 #define CCM_WIMR0_IPI_INT_GPT (1 << 20)
1316 #define CCM_WIMR0_IPI_INT_FIR (1 << 21)
1317 #define CCM_WIMR0_IPI_INT_EPIT2 (1 << 22)
1318 #define CCM_WIMR0_IPI_INT_EPIT1 (1 << 23)
1319 #define CCM_WIMR0_IPI_INT_CSPI2 (1 << 24)
1320 #define CCM_WIMR0_IPI_INT_CSPI1 (1 << 25)
1321 #define CCM_WIMR0_IPI_INT_POWER_FAIL (1 << 26)
1322 #define CCM_WIMR0_IPI_INT_CSPI3 (1 << 27)
1323 #define CCM_WIMR0_RESERVED28 (1 << 28)
1324 #define CCM_WIMR0_RESERVED29 (1 << 29)
1325 #define CCM_WIMR0_RESERVED30 (1 << 30)
1326 #define CCM_WIMR0_RESERVED31 (1 << 31)
1327
1328 /* LDC */
1329 /* 32 bits specify value */
1330
1331 /* DCVR0-DCVR3 */
1332 #define CCM_DCVR_ULV (0x3ff << 22) /* Upper limit */
1333 #define CCM_DCVR_ULV_POS (22)
1334 #define CCM_DCVR_LLV (0x3ff << 12) /* Lower limit */
1335 #define CCM_DCVR_LLV_POS (12)
1336 #define CCM_DCVR_ELV (0x3ff << 2) /* Emergency limit */
1337 #define CCM_DCVR_ELV_POS (2)
1338
1339
1340 /* LTR0 */
1341 #define CCM_LTR0_UPTHR (0x3f << 22)
1342 #define CCM_LTR0_UPTHR_POS (22)
1343 #define CCM_LTR0_DNTHR (0x3f << 16)
1344 #define CCM_LTR0_DNTHR_POS (16)
1345 /* for div_3_clk */
1346 #define CCM_LTR0_DIV3CK (0x3 << 1)
1347 #define CCM_LTR0_DIV3CK_POS (1)
1348 #define CCM_LTR0_DIV3CK_2048 (0x0 << 1) /* 1/2048 ARM clock */
1349 #define CCM_LTR0_DIV3CK_8192 (0x1 << 1) /* 1/8192 ARM clock */
1350 #define CCM_LTR0_DIV3CK_32768 (0x2 << 1) /* 1/32768 ARM clock */
1351 #define CCM_LTR0_DIV3CK_131072 (0x3 << 1) /* 1/131072 ARM clock */
1352
1353 /* LTR1 */
1354 #define CCM_LTR1_LTBRSH (1 << 23)
1355 #define CCM_LTR1_LTBRSR (1 << 22)
1356 #define CCM_LTR1_DNCNT (0xff << 14)
1357 #define CCM_LTR1_DNCNT_POS (14)
1358 #define CCM_LTR1_UPCNT (0xff << 6)
1359 #define CCM_LTR1_UPCNT_POS (6)
1360 #define CCM_LTR1_PNCTHR (0x3f << 0)
1361 #define CCM_LTR1_PNCTHR_POS (0)
1362
1363 /* LTR2 */
1364 #define CCM_LTR2_EMAC (0x1ff)
1365 #define CCM_LTR2_EMAC_POS (0)
1366
1367 /* PMCR0 */
1368 #define CCM_PMCR0_DFSUP_MCUPLL (1 << 31)
1369 #define CCM_PMCR0_DFSUP_MCUPLL_POS (31)
1370 #define CCM_PMCR0_DFSUP_POST_DIVIDERS (1 << 30)
1371 #define CCM_PMCR0_DVSUP (0x3 << 28)
1372 #define CCM_PMCR0_DVSUP_POS (28)
1373 #define CCM_PMCR0_UDSC (1 << 27)
1374 #define CCM_PMCR0_VSCNT (0x7 << 24)
1375 #define CCM_PMCR0_VSCNT_POS (24)
1376 #define CCM_PMCR0_DVFEV (1 << 23)
1377 #define CCM_PMCR0_DVFIS (1 << 22)
1378 #define CCM_PMCR0_LBMI (1 << 21)
1379 #define CCM_PMCR0_LBFL (1 << 20)
1380 #define CCM_PMCR0_LBCF (0x3 << 18)
1381 #define CCM_PMCR0_LBCF_4 (0x0 << 18)
1382 #define CCM_PMCR0_LBCF_8 (0x1 << 18)
1383 #define CCM_PMCR0_LBCF_12 (0x2 << 18)
1384 #define CCM_PMCR0_LBCF_16 (0x3 << 18)
1385 #define CCM_PMCR0_PTVIS (1 << 17)
1386 #define CCM_PMCR0_UPDTEN (1 << 16)
1387 #define CCM_PMCR0_FSVAIM (1 << 15)
1388 #define CCM_PMCR0_FSVAI (0x3 << 13)
1389 #define CCM_PMCR0_FSVAI_NO_INT (0x0 << 13)
1390 #define CCM_PMCR0_FSVAI_INCREASE (0x1 << 13)
1391 #define CCM_PMCR0_FSVAI_DECREASE (0x2 << 13)
1392 #define CCM_PMCR0_FSVAI_INCREASE_NOW (0x3 << 13)
1393 #define CCM_PMCR0_FSVAI_POS (13)
1394 #define CCM_PMCR0_DPVCR (1 << 12)
1395 #define CCM_PMCR0_DPVV (1 << 11)
1396 #define CCM_PMCR0_WFIM (1 << 10)
1397 #define CCM_PMCR0_DRCE3 (1 << 9)
1398 #define CCM_PMCR0_DRCE2 (1 << 8)
1399 #define CCM_PMCR0_DRCE1 (1 << 7)
1400 #define CCM_PMCR0_DRCE0 (1 << 6)
1401 #define CCM_PMCR0_DCR (1 << 5) /* 512 vs 256 count */
1402 #define CCM_PMCR0_DVFEN (1 << 4)
1403 #define CCM_PMCR0_PTVAIM (1 << 3)
1404 #define CCM_PMCR0_PTVAI (0x3 << 1)
1405 #define CCM_PMCR0_PTVAI_NO_INT (0x0 << 1)
1406 #define CCM_PMCR0_PTVAI_DECREASE (0x1 << 1)
1407 #define CCM_PMCR0_PTVAI_INCREASE (0x2 << 1)
1408 #define CCM_PMCR0_PTVAI_INCREASE_NOW (0x3 << 1)
1409 #define CCM_PMCR0_DPTEN (1 << 0)
1410
1411
1412 /* PMCR1 */
1413 #define CCM_PMCR1_DVGP_POS (0)
1414 #define CCM_PMCR1_DVGP_MASK (0xf << 0)
1415
1416 /* IC revision 2.0 or greater ONLY! */
1417 #define CCM_PMCR1_EMIRQ_EN (1 << 8)
1418 #define CCM_PMCR1_PLLRDIS (1 << 7) /* No PLL reset on switch */
1419
1420
1421 /* WEIM - CS0 */
1422 #define CSCRU 0x00
1423 #define CSCRL 0x04
1424 #define CSCRA 0x08
1425
1426 /* ESDCTL */
1427 #define ESDCTL_ESDCTL0 0x00
1428 #define ESDCTL_ESDCFG0 0x04
1429 #define ESDCTL_ESDCTL1 0x08
1430 #define ESDCTL_ESDCFG1 0x0C
1431 #define ESDCTL_ESDMISC 0x10
1432
1433 /* More UART 1 Register defines */
1434 #define URXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00))
1435 #define UTXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x40))
1436 #define UCR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x80))
1437 #define UCR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x84))
1438 #define UCR3_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x88))
1439 #define UCR4_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x8C))
1440 #define UFCR1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x90))
1441 #define USR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x94))
1442 #define USR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x98))
1443 #define UTS1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0xB4))
1444
1445 #define UCR1_2 (*(REG32_PTR_T)(UART2_BASE_ADDR+0x80))
1446 #define UCR1_3 (*(REG32_PTR_T)(UART3_BASE_ADDR+0x80))
1447 #define UCR1_4 (*(REG32_PTR_T)(UART4_BASE_ADDR+0x80))
1448 #define UCR1_5 (*(REG32_PTR_T)(UART5_BASE_ADDR+0x80))
1449
1450 /*
1451 * UART Control Register 0 Bit Fields.
1452 */
1453 #define EUARTUCR1_ADEN (1 << 15) // Auto detect interrupt
1454 #define EUARTUCR1_ADBR (1 << 14) // Auto detect baud rate
1455 #define EUARTUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
1456 #define EUARTUCR1_IDEN (1 << 12) // Idle condition interrupt
1457 #define EUARTUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
1458 #define EUARTUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
1459 #define EUARTUCR1_IREN (1 << 7) // Infrared interface enable
1460 #define EUARTUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable
1461 #define EUARTUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
1462 #define EUARTUCR1_SNDBRK (1 << 4) // Send break
1463 #define EUARTUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
1464 #define EUARTUCR1_DOZE (1 << 1) // Doze
1465 #define EUARTUCR1_UARTEN (1 << 0) // UART enabled
1466 #define EUARTUCR2_ESCI (1 << 15) // Escape seq interrupt enable
1467 #define EUARTUCR2_IRTS (1 << 14) // Ignore RTS pin
1468 #define EUARTUCR2_CTSC (1 << 13) // CTS pin control
1469 #define EUARTUCR2_CTS (1 << 12) // Clear to send
1470 #define EUARTUCR2_ESCEN (1 << 11) // Escape enable
1471 #define EUARTUCR2_PREN (1 << 8) // Parity enable
1472 #define EUARTUCR2_PROE (1 << 7) // Parity odd/even
1473 #define EUARTUCR2_STPB (1 << 6) // Stop
1474 #define EUARTUCR2_WS (1 << 5) // Word size
1475 #define EUARTUCR2_RTSEN (1 << 4) // Request to send interrupt enable
1476 #define EUARTUCR2_ATEN (1 << 3) // Aging timer enable
1477 #define EUARTUCR2_TXEN (1 << 2) // Transmitter enabled
1478 #define EUARTUCR2_RXEN (1 << 1) // Receiver enabled
1479 #define EUARTUCR2_SRST_ (1 << 0) // SW reset
1480 #define EUARTUCR3_PARERREN (1 << 12) // Parity enable
1481 #define EUARTUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
1482 #define EUARTUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
1483 #define EUARTUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
1484 #define EUARTUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
1485 #define EUARTUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
1486 #define EUARTUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
1487 #define EUARTUCR3_INVT (1 << 1) // Inverted Infrared transmission
1488 #define EUARTUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
1489 #define EUARTUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
1490 #define EUARTUCR4_INVR (1 << 9) // Inverted infrared reception
1491 #define EUARTUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
1492 #define EUARTUCR4_WKEN (1 << 7) // Wake interrupt enable
1493 #define EUARTUCR4_IRSC (1 << 5) // IR special case
1494 #define EUARTUCR4_LPBYP (1 << 4) // Low power bypass
1495 #define EUARTUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
1496 #define EUARTUCR4_BKEN (1 << 2) // Break condition interrupt enable
1497 #define EUARTUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
1498 #define EUARTUCR4_DREN (1 << 0) // Recv data ready interrupt enable
1499 #define EUARTUFCR_RXTL_SHF 0 // Receiver trigger level shift
1500 #define EUARTUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1)
1501 #define EUARTUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2)
1502 #define EUARTUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
1503 #define EUARTUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
1504 #define EUARTUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
1505 #define EUARTUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
1506 #define EUARTUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
1507 #define EUARTUFCR_TXTL_SHF 10 // Transmitter trigger level shift
1508 #define EUARTUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
1509 #define EUARTUSR1_RTSS (1 << 14) // RTS pin status
1510 #define EUARTUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
1511 #define EUARTUSR1_RTSD (1 << 12) // RTS delta
1512 #define EUARTUSR1_ESCF (1 << 11) // Escape seq interrupt flag
1513 #define EUARTUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
1514 #define EUARTUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
1515 #define EUARTUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
1516 #define EUARTUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
1517 #define EUARTUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
1518 #define EUARTUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
1519 #define EUARTUSR2_ADET (1 << 15) // Auto baud rate detect complete
1520 #define EUARTUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
1521 #define EUARTUSR2_IDLE (1 << 12) // Idle condition
1522 #define EUARTUSR2_ACST (1 << 11) // Autobaud counter stopped
1523 #define EUARTUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
1524 #define EUARTUSR2_WAKE (1 << 7) // Wake
1525 #define EUARTUSR2_RTSF (1 << 4) // RTS edge interrupt flag
1526 #define EUARTUSR2_TXDC (1 << 3) // Transmitter complete
1527 #define EUARTUSR2_BRCD (1 << 2) // Break condition
1528 #define EUARTUSR2_ORE (1 << 1) // Overrun error
1529 #define EUARTUSR2_RDR (1 << 0) // Recv data ready
1530 #define EUARTUTS_FRCPERR (1 << 13) // Force parity error
1531 #define EUARTUTS_LOOP (1 << 12) // Loop tx and rx
1532 #define EUARTUTS_TXEMPTY (1 << 6) // TxFIFO empty
1533 #define EUARTUTS_RXEMPTY (1 << 5) // RxFIFO empty
1534 #define EUARTUTS_TXFULL (1 << 4) // TxFIFO full
1535 #define EUARTUTS_RXFULL (1 << 3) // RxFIFO full
1536 #define EUARTUTS_SOFTRST (1 << 0) // Software reset
1537
1538 /* SDMA */
1539 #define SDMA_MC0PTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x000))
1540 #define SDMA_INTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x004))
1541 #define SDMA_STOP_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x008))
1542 #define SDMA_HSTART (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x00C))
1543 #define SDMA_EVTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x010))
1544 #define SDMA_DSPOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x014))
1545 #define SDMA_HOSTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x018))
1546 #define SDMA_EVTPEND (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x01C))
1547 #define SDMA_DSPENBL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x020))
1548 #define SDMA_RESET (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x024))
1549 #define SDMA_EVTERR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x028))
1550 #define SDMA_INTRMSK (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x02C))
1551 #define SDMA_PSW (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x030))
1552 #define SDMA_EVTERRDBG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x034))
1553 #define SDMA_CONFIG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x038))
1554 #define SDMA_ONCE_ENB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x040))
1555 #define SDMA_ONCE_DATA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x044))
1556 #define SDMA_ONCE_INSTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x048))
1557 #define SDMA_ONCE_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x04C))
1558 #define SDMA_ONCE_CMD (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x050))
1559 #define SDMA_EVT_MIRROR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x054))
1560 #define SDMA_ILLINSTADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x058))
1561 #define SDMA_CHN0ADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x05C))
1562 #define SDMA_ONCE_RTB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x060))
1563 #define SDMA_XTRIG_CONF1 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x070))
1564 #define SDMA_XTRIG_CONF2 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x074))
1565
1566 /* SDMA_CHNENBL: 0x080 - 0x0FC */
1567 #define SDMA_CHNENBL(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x080))[n]) /* 0..31 */
1568
1569 /* SDMA_CHNPRI: 0x100 - 0x17C */
1570 #define SDMA_CHNPRI(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x100))[n]) /* 0..31 */
1571
1572 #define SDMA_ONCE_COUNT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x200))
1573 #define SDMA_ONCE_ECTL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x204))
1574 #define SDMA_ONCE_EAA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x208))
1575 #define SDMA_ONCE_EAB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x20C))
1576 #define SDMA_ONCE_EAM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x210))
1577 #define SDMA_ONCE_ED (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x214))
1578 #define SDMA_ONCE_EDM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x218))
1579 #define SDMA_ONCE_PCMATCH (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x21C))
1580
1581 /* SDMA_RESET */
1582 #define SDMA_RESET_RESCHED (0x1 << 1)
1583 #define SDMA_RESET_RESET (0x1 << 0)
1584
1585 /* SDMA_PSW */
1586 #define SDMA_PSW_NCP (0x7 << 13)
1587 #define SDMA_PSW_NCR (0x1f << 8)
1588 #define SDMA_PSW_CCP (0x7 << 5)
1589 #define SDMA_PSW_CCR (0x1f << 0)
1590
1591 /* SDMA_CONFIG */
1592 #define SDMA_CONFIG_DSPDMA (0x1 << 12)
1593 #define SDMA_CONFIG_RTDOBS (0x1 << 11)
1594 #define SDMA_CONFIG_ACR (0x1 << 4)
1595 #define SDMA_CONFIG_CSM (0x3 << 0)
1596 #define SDMA_CONFIG_CSM_STATIC (0x0 << 0)
1597 #define SDMA_CONFIG_CSM_DYNAMIC_LOW_POWER (0x1 << 0)
1598 #define SDMA_CONFIG_CSM_DYNAMIC_NO_LOOP (0x2 << 0)
1599 #define SDMA_CONFIG_CSM_DYNAMIC (0x3 << 0)
1600
1601 /* SDMA_ONCE_ENB */
1602 #define SDMA_ONCE_ENB_ENB (0x1 << 0)
1603
1604 /* SDMA_ONCE_STAT */
1605 #define SDMA_ONCE_STAT_PST (0xf << 12)
1606 #define SDMA_ONCE_STAT_PST_PROGRAM (0x0 << 12)
1607 #define SDMA_ONCE_STAT_PST_DATA (0x1 << 12)
1608 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW (0x2 << 12)
1609 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP (0x3 << 12)
1610 #define SDMA_ONCE_STAT_PST_DEBUG (0x4 << 12)
1611 #define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT (0x5 << 12)
1612 #define SDMA_ONCE_STAT_PST_SLEEP (0x6 << 12)
1613 #define SDMA_ONCE_STAT_PST_SAVE (0x7 << 12)
1614 #define SDMA_ONCE_STAT_PST_PROGRAM_IN_SLEEP (0x8 << 12)
1615 #define SDMA_ONCE_STAT_PST_DATA_IN_SLEEP (0x9 << 12)
1616 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_SLEEP (0xa << 12)
1617 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP_IN_SLEEP (0xb << 12)
1618 #define SDMA_ONCE_STAT_PST_DEBUG_IN_SLEEP (0xc << 12)
1619 #define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT_IN_SLEEP (0xd << 12)
1620 #define SDMA_ONCE_STAT_PST_SLEEP_AFTER_RESET (0xe << 12)
1621 #define SDMA_ONCE_STAT_PST_RESTORE (0xf << 12)
1622 #define SDMA_ONCE_STAT_RCV (0x1 << 11)
1623 #define SDMA_ONCE_STAT_EDR (0x1 << 10)
1624 #define SDMA_ONCE_STAT_ODR (0x1 << 9)
1625 #define SDMA_ONCE_STAT_SWB (0x1 << 8)
1626 #define SDMA_ONCE_STAT_MST (0x1 << 7)
1627 #define SDMA_ONCE_STAT_ECDR (0x7 << 0)
1628 #define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRA_COND (0x1 << 0)
1629 #define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRB_COND (0x1 << 1)
1630 #define SDMA_ONCE_STAT_ECDR_MATCHED_DATA_COND (0x1 << 2)
1631
1632 /* SDMA_ONCE_CMD */
1633 #define SDMA_ONCE_CMD_RSTATUS 0x0
1634 #define SDMA_ONCE_CMD_DMOV 0x1
1635 #define SDMA_ONCE_CMD_EXEC_ONCE 0x2
1636 #define SDMA_ONCE_CMD_RUN_CORE 0x3
1637 #define SDMA_ONCE_CMD_EXEC_CORE 0x4
1638 #define SDMA_ONCE_CMD_DEBUG_RQST 0x5
1639 #define SDMA_ONCE_CMD_RBUFFER 0x6
1640 /* 7-15 reserved */
1641
1642 /* SDMA_CHN0ADDR */
1643 #define SDMA_CHN0ADDR_SMSZ (0x1 << 14)
1644 /* 13:0 = 0x0050 by default (std. boot code) */
1645
1646 /* SDMA_EVT_MIRROR */
1647 #define SDMA_EVT_MIRROR_EVENTS(n) (0x1 << (n))
1648
1649 /* SDMA_XTRIG_CONF1 */
1650 #define SDMA_XTRIG_CONF1_CNF3 (0x1 << 30)
1651 #define SDMA_XTRIG_CONF1_NUM3 (0x1f << 24)
1652 #define SDMA_XTRIG_CONF1_CNF2 (0x1 << 22)
1653 #define SDMA_XTRIG_CONF1_NUM2 (0x1f << 16)
1654 #define SDMA_XTRIG_CONF1_CNF1 (0x1 << 14)
1655 #define SDMA_XTRIG_CONF1_NUM1 (0x1f << 8)
1656 #define SDMA_XTRIG_CONF1_CNF0 (0x1 << 6)
1657 #define SDMA_XTRIG_CONF1_NUM0 (0x1f << 0)
1658
1659 /* SDMA_XTRIG_CONF2 */
1660 #define SDMA_XTRIG_CONF2_CNF7 (0x1 << 30)
1661 #define SDMA_XTRIG_CONF2_NUM7 (0x1f << 24)
1662 #define SDMA_XTRIG_CONF2_CNF6 (0x1 << 22)
1663 #define SDMA_XTRIG_CONF2_NUM6 (0x1f << 16)
1664 #define SDMA_XTRIG_CONF2_CNF5 (0x1 << 14)
1665 #define SDMA_XTRIG_CONF2_NUM5 (0x1f << 8)
1666 #define SDMA_XTRIG_CONF2_CNF4 (0x1 << 6)
1667 #define SDMA_XTRIG_CONF2_NUM4 (0x1f << 0)
1668
1669 /* SDMA_CHNENBL(n) */
1670 #define SDMA_CHNENBL_ENBL(n) (0x1 << (n))
1671
1672
1673 #define L2CC_ENABLED
1674
1675 /* Assuming 26MHz input clock */
1676 /* PD MFD MFI MFN */
1677 #define MPCTL_PARAM_208 ((1 << 26) + (0 << 16) + (8 << 10) + (0 << 0))
1678 #define MPCTL_PARAM_399 ((0 << 26) + (51 << 16) + (7 << 10) + (35 << 0))
1679 #define MPCTL_PARAM_532 ((0 << 26) + (51 << 16) + (10 << 10) + (12 << 0))
1680
1681 /* UPCTL PD MFD MFI MFN */
1682 #define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0))
1683 #define UPCTL_PARAM_240 (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
1684
1685 /* PDR0 */
1686 #define PDR0_208_104_52 0xFF870D48 /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
1687 #define PDR0_399_66_66 0xFF872B28 /* ARM=399MHz, HCLK=IPG=66.5MHz */
1688 #define PDR0_399_133_66 0xFF871650 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
1689 #define PDR0_532_133_66 0xFF871E58 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1690 #define PDR0_665_83_66 0xFF873D78 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1691 #define PDR0_665_133_66 0xFF872660 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1692
1693 #define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */
1694
1695 #define PBC_BSTAT2 0x2
1696 #define PBC_BCTRL1 0x4
1697 #define PBC_BCTRL1_CLR 0x6
1698 #define PBC_BCTRL2 0x8
1699 #define PBC_BCTRL2_CLR 0xA
1700 #define PBC_BCTRL3 0xC
1701 #define PBC_BCTRL3_CLR 0xE
1702 #define PBC_BCTRL4 0x10
1703 #define PBC_BCTRL4_CLR 0x12
1704 #define PBC_BSTAT1 0x14
1705 #define MX31EVB_CS_LAN_BASE (CS4_BASE_ADDR + 0x00020000 + 0x300)
1706 #define MX31EVB_CS_UART_BASE (CS4_BASE_ADDR + 0x00010000)
1707
1708 #define REDBOOT_IMAGE_SIZE 0x40000
1709
1710 #define SDRAM_WORKAROUND_FULL_PAGE
1711
1712 #define ARMHIPG_208_52_52 /* ARM: 208MHz, HCLK=IPG=52MHz*/
1713 #define ARMHIPG_52_52_52 /* ARM: 52MHz, HCLK=IPG=52MHz*/
1714 #define ARMHIPG_399_66_66
1715 #define ARMHIPG_399_133_66
1716
1717 /* MX31 EVB SDRAM is from 0x80000000, 64M */
1718 #define SDRAM_BASE_ADDR CSD0_BASE_ADDR
1719 #define SDRAM_SIZE 0x04000000
1720
1721 #define UART_WIDTH_32 /* internal UART is 32bit access only */
1722 #define EXT_UART_x16
1723
1724 #define UART_WIDTH_32 /* internal UART is 32bit access only */
1725
1726 #define FLASH_BURST_MODE_ENABLE 1
1727 #define SDRAM_COMPARE_CONST1 0x55555555
1728 #define SDRAM_COMPARE_CONST2 0xAAAAAAAA
1729 #define UART_FIFO_CTRL 0x881
1730 #define TIMEOUT 1000
1731
1732 /* Timer frequency */
1733 /* timer is based on ipg_clk */
1734 #define TIMER_FREQ (66000000)
1735
1736 #endif /* __IMX31L_H__ */
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