firmware/target/arm/as3525/sd-as3525v2.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h" /* for HAVE_MULTIVOLUME */
  24 #include "fat.h"
  25 #include "thread.h"
  26 #include "led.h"
  27 #include "hotswap.h"
  28 #include "system.h"
  29 #include "kernel.h"
  30 #include "cpu.h"
  31 #include <stdio.h>
  32 #include <stdlib.h>
  33 #include <string.h>
  34 #include "as3525v2.h"
  35 #include "pl081.h"  /* DMA controller */
  36 #include "dma-target.h" /* DMA request lines */
  37 #include "clock-target.h"
  38 #include "panic.h"
  39 #include "stdbool.h"
  40 #include "ata_idle_notify.h"
  41 #include "sd.h"
  42 #include "usb.h"
  43
  44 #ifdef HAVE_HOTSWAP
  45 #include "disk.h"
  46 #endif
  47
  48 #include "lcd.h"
  49 #include <stdarg.h>
  50 #include "sysfont.h"
  51
  52 #define     INTERNAL_AS3525  0   /* embedded SD card */
  53 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  54
  55 /* command flags */
  56 #define MCI_NO_RESP     (0<<0)
  57 #define MCI_RESP        (1<<0)
  58 #define MCI_LONG_RESP   (1<<1)
  59
  60 /* controller registers */
  61 #define SD_BASE 0xC6070000
  62
  63 #define SD_REG(x)       (*(volatile unsigned long *) (SD_BASE+x))
  64
  65 #define MCI_CTRL        SD_REG(0x00)
  66
  67 /* control bits */
  68 #define CTRL_RESET      (1<<0)
  69 #define FIFO_RESET      (1<<1)
  70 #define DMA_RESET       (1<<2)
  71 #define INT_ENABLE      (1<<4)
  72 #define DMA_ENABLE      (1<<5)
  73 #define READ_WAIT       (1<<6)
  74 #define SEND_IRQ_RESP   (1<<7)
  75 #define ABRT_READ_DATA  (1<<8)
  76 #define SEND_CCSD       (1<<9)
  77 #define SEND_AS_CCSD    (1<<10)
  78 #define EN_OD_PULLUP    (1<<24)
  79
  80
  81 #define MCI_PWREN       SD_REG(0x04)    /* power enable */
  82
  83 #define PWR_CRD_0       (1<<0)
  84 #define PWR_CRD_1       (1<<1)
  85 #define PWR_CRD_2       (1<<2)
  86 #define PWR_CRD_3       (1<<3)
  87
  88 #define MCI_CLKDIV      SD_REG(0x08)    /* clock divider */
  89 /* CLK_DIV_0 :    bits 7:0
  90  * CLK_DIV_1 :    bits 15:8
  91  * CLK_DIV_2 :    bits 23:16
  92  * CLK_DIV_3 :    bits 31:24
  93  */
  94
  95 #define MCI_CLKSRC      SD_REG(0x0C)    /* clock source */
  96 /* CLK_SRC_CRD0:  bits 1:0
  97  * CLK_SRC_CRD1:  bits 3:2
  98  * CLK_SRC_CRD2:  bits 5:4
  99  * CLK_SRC_CRD3:  bits 7:6
 100  */
 101
 102 #define MCI_CLKENA      SD_REG(0x10)    /* clock enable */
 103
 104 #define CCLK_ENA_CRD0   (1<<0)
 105 #define CCLK_ENA_CRD1   (1<<1)
 106 #define CCLK_ENA_CRD2   (1<<2)
 107 #define CCLK_ENA_CRD3   (1<<3)
 108 #define CCLK_LP_CRD0    (1<<16)         /* LP --> Low Power Mode? */
 109 #define CCLK_LP_CRD1    (1<<17)
 110 #define CCLK_LP_CRD2    (1<<18)
 111 #define CCLK_LP_CRD3    (1<<19)
 112
 113 #define MCI_TMOUT       SD_REG(0x14)    /* timeout */
 114 /* response timeout bits 0:7
 115  * data timeout bits     8:31
 116  */
 117
 118 #define MCI_CTYPE       SD_REG(0x18)    /* card type */
 119                                         /* 1 bit per card, set = wide bus */
 120 #define WIDTH4_CRD0     (1<<0)
 121 #define WIDTH4_CRD1     (1<<1)
 122 #define WIDTH4_CRD2     (1<<2)
 123 #define WIDTH4_CRD3     (1<<3)
 124
 125 #define MCI_BLKSIZ      SD_REG(0x1C)    /* block size  bits 0:15*/
 126 #define MCI_BYTCNT      SD_REG(0x20)    /* byte count  bits 0:31*/
 127 #define MCI_MASK        SD_REG(0x24)    /* interrupt mask */
 128
 129
 130
 131 #define MCI_ARGUMENT    SD_REG(0x28)
 132 #define MCI_COMMAND     SD_REG(0x2C)
 133
 134 /* command bits (bits 5:0 are the command index) */
 135 #define CMD_RESP_EXP_BIT        (1<<6)
 136 #define CMD_RESP_LENGTH_BIT     (1<<7)
 137 #define CMD_CHECK_CRC_BIT       (1<<8)
 138 #define CMD_DATA_EXP_BIT        (1<<9)
 139 #define CMD_RW_BIT              (1<<10)
 140 #define CMD_TRANSMODE_BIT       (1<<11)
 141 #define CMD_SENT_AUTO_STOP_BIT  (1<<12)
 142 #define CMD_WAIT_PRV_DAT_BIT    (1<<13)
 143 #define CMD_ABRT_CMD_BIT        (1<<14)
 144 #define CMD_SEND_INIT_BIT       (1<<15)
 145 #define CMD_CARD_NO(x)          ((x)<<16)         /* 5 bits wide  */
 146 #define CMD_SEND_CLK_ONLY       (1<<21)
 147 #define CMD_READ_CEATA          (1<<22)
 148 #define CMD_CCS_EXPECTED        (1<<23)
 149 #define CMD_DONE_BIT            (1<<31)
 150
 151 #define TRANSFER_CMD  (cmd == SD_READ_MULTIPLE_BLOCK ||   \
 152                        cmd == SD_WRITE_MULTIPLE_BLOCK)
 153
 154 #define MCI_RESP0       SD_REG(0x30)
 155 #define MCI_RESP1       SD_REG(0x34)
 156 #define MCI_RESP2       SD_REG(0x38)
 157 #define MCI_RESP3       SD_REG(0x3C)
 158
 159 #define MCI_MASK_STATUS SD_REG(0x40)    /* masked interrupt status */
 160 #define MCI_RAW_STATUS  SD_REG(0x44)    /* raw interrupt status, also used as
 161                                          * status clear */
 162
 163 /* interrupt bits */                /* C D E   (Cmd) (Data) (End) */
 164 #define MCI_INT_CRDDET  (1<<0)      /*          card detect */
 165 #define MCI_INT_RE      (1<<1)      /* x         response error */
 166 #define MCI_INT_CD      (1<<2)      /*     x     command done */
 167 #define MCI_INT_DTO     (1<<3)      /*     x     data transfer over */
 168 #define MCI_INT_TXDR    (1<<4)      /*          tx fifo data request */
 169 #define MCI_INT_RXDR    (1<<5)      /*          rx fifo data request */
 170 #define MCI_INT_RCRC    (1<<6)      /* x         response crc error */
 171 #define MCI_INT_DCRC    (1<<7)      /*   x       data crc error */
 172 #define MCI_INT_RTO     (1<<8)      /* x         response timeout */
 173 #define MCI_INT_DRTO    (1<<9)      /*   x       data read timeout */
 174 #define MCI_INT_HTO     (1<<10)     /*   x       data starv timeout */
 175 #define MCI_INT_FRUN    (1<<11)     /*   x       fifo over/underrun */
 176 #define MCI_INT_HLE     (1<<12)     /* x x        hw locked while error */
 177 #define MCI_INT_SBE     (1<<13)     /*   x       start bit error */
 178 #define MCI_INT_ACD     (1<<14)     /*          auto command done */
 179 #define MCI_INT_EBE     (1<<15)     /*   x       end bit error */
 180 #define MCI_INT_SDIO    (0xf<<16)
 181
 182 /*
 183  *  STATUS register
 184  *  & 0xBA80    = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
 185  *                  MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
 186  *  & 8         = MCI_INT_DTO
 187  *  & 0x428     = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
 188  *  & 0x418     = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
 189  */
 190
 191 #define MCI_CMD_ERROR    \
 192          (MCI_INT_RE   | \
 193           MCI_INT_RCRC | \
 194           MCI_INT_RTO  | \
 195           MCI_INT_HLE)
 196
 197 #define MCI_DATA_ERROR    \
 198         ( MCI_INT_DCRC  | \
 199           MCI_INT_DRTO  | \
 200           MCI_INT_HTO   | \
 201           MCI_INT_FRUN  | \
 202           MCI_INT_HLE   | \
 203           MCI_INT_SBE   | \
 204           MCI_INT_EBE)
 205
 206 #define MCI_STATUS      SD_REG(0x48)
 207
 208 #define FIFO_RX_WM              (1<<0)
 209 #define FIFO_TX_WM              (1<<1)
 210 #define FIFO_EMPTY              (1<<2)
 211 #define FIFO_FULL               (1<<3)
 212 #define CMD_FSM_STATE_B0        (1<<4)
 213 #define CMD_FSM_STATE_B1        (1<<5)
 214 #define CMD_FSM_STATE_B2        (1<<6)
 215 #define CMD_FSM_STATE_B3        (1<<7)
 216 #define DATA_3_STAT             (1<<8)
 217 #define DATA_BUSY               (1<<9)
 218 #define DATA_STAT_MC_BUSY       (1<<10)
 219 #define RESP_IDX_B0             (1<<11)
 220 #define RESP_IDX_B1             (1<<12)
 221 #define RESP_IDX_B2             (1<<13)
 222 #define RESP_IDX_B3             (1<<14)
 223 #define RESP_IDX_B4             (1<<15)
 224 #define RESP_IDX_B5             (1<<16)
 225 #define FIFO_CNT_B00            (1<<17)
 226 #define FIFO_CNT_B01            (1<<18)
 227 #define FIFO_CNT_B02            (1<<19)
 228 #define FIFO_CNT_B03            (1<<20)
 229 #define FIFO_CNT_B04            (1<<21)
 230 #define FIFO_CNT_B05            (1<<22)
 231 #define FIFO_CNT_B06            (1<<23)
 232 #define FIFO_CNT_B07            (1<<24)
 233 #define FIFO_CNT_B08            (1<<25)
 234 #define FIFO_CNT_B09            (1<<26)
 235 #define FIFO_CNT_B10            (1<<27)
 236 #define FIFO_CNT_B11            (1<<28)
 237 #define FIFO_CNT_B12            (1<<29)
 238 #define DMA_ACK                 (1<<30)
 239 #define START_CMD               (1<<31)
 240
 241 #define MCI_FIFOTH      SD_REG(0x4C)    /* FIFO threshold */
 242 /* TX watermark :    bits 11:0
 243  * RX watermark :    bits 27:16
 244  * DMA MTRANS SIZE : bits 30:28
 245  * bits 31, 15:12 : unused
 246  */
 247 #define MCI_FIFOTH_MASK 0x8000f000
 248
 249 #define MCI_CDETECT     SD_REG(0x50)    /* card detect */
 250
 251 #define CDETECT_CRD_0   (1<<0)
 252 #define CDETECT_CRD_1   (1<<1)
 253 #define CDETECT_CRD_2   (1<<2)
 254 #define CDETECT_CRD_3   (1<<3)
 255
 256 #define MCI_WRTPRT      SD_REG(0x54)    /* write protect */
 257 #define MCI_GPIO        SD_REG(0x58)
 258 #define MCI_TCBCNT      SD_REG(0x5C)    /* transferred CIU byte count (card)*/
 259 #define MCI_TBBCNT      SD_REG(0x60)    /* transferred host/DMA to/from bytes (FIFO)*/
 260 #define MCI_DEBNCE      SD_REG(0x64)    /* card detect debounce  bits 23:0*/
 261 #define MCI_USRID       SD_REG(0x68)    /* user id */
 262 #define MCI_VERID       SD_REG(0x6C)    /* version id */
 263
 264 #define MCI_HCON        SD_REG(0x70)    /* hardware config */
 265 /* bit  0       : card type
 266  * bits 5:1     : maximum card index
 267  * bit  6       : BUS TYPE
 268  * bits 9:7     : DATA WIDTH
 269  * bits 15:10   : ADDR WIDTH
 270  * bits 17:16   : DMA IF
 271  * bits 20:18   : DMA WIDTH
 272  * bit  21      : FIFO RAM INSIDE
 273  * bit  22      : IMPL HOLD REG
 274  * bit  23      : SET CLK FALSE
 275  * bits 25:24   : MAX CLK DIV IDX
 276  * bit  26      : AREA OPTIM
 277  */
 278
 279 #define MCI_BMOD        SD_REG(0x80)    /* bus mode */
 280 /* bit  0       : SWR
 281  * bit  1       : FB
 282  * bits 6:2     : DSL
 283  * bit  7       : DE
 284  * bit  10:8    : PBL
 285  */
 286
 287 #define MCI_PLDMND      SD_REG(0x84)    /* poll demand */
 288 #define MCI_DBADDR      SD_REG(0x88)    /* descriptor base address */
 289 #define MCI_IDSTS       SD_REG(0x8C)    /* internal DMAC status */
 290 /* bit  0       : TI
 291  * bit  1       : RI
 292  * bit  2       : FBE
 293  * bit  3       : unused
 294  * bit  4       : DU
 295  * bit  5       : CES
 296  * bits 7:6     : unused
 297  * bits 8       : NIS
 298  * bit  9       : AIS
 299  * bits 12:10   : EB
 300  * bits 16:13   : FSM
 301  */
 302
 303 #define MCI_IDINTEN     SD_REG(0x90)    /* internal DMAC interrupt enable */
 304 /* bit  0       : TI
 305  * bit  1       : RI
 306  * bit  2       : FBE
 307  * bit  3       : unused
 308  * bit  4       : DU
 309  * bit  5       : CES
 310  * bits 7:6     : unused
 311  * bits 8       : NI
 312  * bit  9       : AI
 313  */
 314 #define MCI_DSCADDR     SD_REG(0x94)    /* current host descriptor address */
 315 #define MCI_BUFADDR     SD_REG(0x98)    /* current host buffer address */
 316
 317 #define MCI_FIFO        ((unsigned long *) (SD_BASE+0x100))
 318
 319 #define UNALIGNED_NUM_SECTORS 10
 320 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 321 static unsigned char *uncached_buffer = UNCACHED_ADDR(&aligned_buffer[0]);
 322
 323 static void init_controller(void);
 324 static int sd_wait_for_state(const int drive, unsigned int state);
 325
 326 static tCardInfo card_info[NUM_DRIVES];
 327
 328 /* for compatibility */
 329 static long last_disk_activity = -1;
 330
 331 #define MIN_YIELD_PERIOD 5  /* ticks */
 332 static long next_yield = 0;
 333
 334 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 335 static const char         sd_thread_name[] = "ata/sd";
 336 static struct mutex       sd_mtx SHAREDBSS_ATTR;
 337 static struct event_queue sd_queue;
 338 #ifndef BOOTLOADER
 339 bool sd_enabled = false;
 340 #endif
 341
 342 static struct wakeup transfer_completion_signal;
 343 static struct wakeup command_completion_signal;
 344 static volatile bool retry;
 345 static volatile int cmd_error;
 346
 347 #if defined(HAVE_MULTIDRIVE)
 348 int active_card = 0;
 349 #define EXT_SD_BITS (1<<2)
 350 #endif
 351
 352 static inline void mci_delay(void) { udelay(1000); }
 353
 354 void INT_NAND(void)
 355 {
 356     MCI_CTRL &= ~INT_ENABLE;
 357     /* use raw status here as we need to check some Ints that are masked */
 358     const int status = MCI_RAW_STATUS;
 359
 360     MCI_RAW_STATUS = status;    /* clear status */
 361
 362     if(status & MCI_DATA_ERROR)
 363         retry = true;
 364
 365     if( status & (MCI_INT_DTO|MCI_DATA_ERROR))
 366         wakeup_signal(&transfer_completion_signal);
 367
 368     cmd_error = status & MCI_CMD_ERROR;
 369
 370     if(status & MCI_INT_CD)
 371         wakeup_signal(&command_completion_signal);
 372
 373     MCI_CTRL |= INT_ENABLE;
 374 }
 375
 376 static inline bool card_detect_target(void)
 377 {
 378 #if defined(HAVE_MULTIDRIVE)
 379 #if defined(SANSA_FUZEV2)
 380     return GPIOA_PIN(2);
 381 #elif defined(SANSA_CLIPPLUS)
 382     return !(GPIOA_PIN(2));
 383 #else
 384 #error "microSD pin not defined for your target"
 385 #endif
 386 #else
 387     return false;
 388 #endif
 389 }
 390
 391 static bool send_cmd(const int drive, const int cmd, const int arg, const int flags,
 392         unsigned long *response)
 393 {
 394 #if defined(HAVE_MULTIDRIVE)
 395     /*  Check to see if we need to switch cards  */
 396     if(sd_present(SD_SLOT_AS3525))
 397          if(active_card != drive)
 398         {
 399             GPIOB_PIN(5) = (1-drive) << 5;
 400             active_card = drive;
 401         }
 402 #endif
 403
 404 /*  RCRC & RTO interrupts should be set together with the CD interrupt but
 405  *  in practice sometimes incorrectly precede the CD interrupt.  If we leave
 406  *  them masked for now we can check them in the isr by reading raw status when
 407  *  the CD int is triggered.
 408  */
 409     MCI_MASK |= MCI_INT_CD;
 410     MCI_ARGUMENT = arg;
 411
 412     /* Construct MCI_COMMAND  */
 413     MCI_COMMAND =
 414       /*b5:0*/    cmd
 415       /*b6  */  | ((flags & MCI_RESP)                ? CMD_RESP_EXP_BIT:      0)
 416       /*b7  */  | ((flags & MCI_LONG_RESP)           ? CMD_RESP_LENGTH_BIT:   0)
 417       /*b8      | CMD_CHECK_CRC_BIT       unused  */
 418       /*b9  */  | (TRANSFER_CMD                      ? CMD_DATA_EXP_BIT:      0)
 419       /*b10 */  | ((cmd == SD_WRITE_MULTIPLE_BLOCK)  ? CMD_RW_BIT:            0)
 420       /*b11     | CMD_TRANSMODE_BIT       unused  */
 421       /*b12     | CMD_SENT_AUTO_STOP_BIT  unused  */
 422       /*b13 */  | (TRANSFER_CMD                      ? CMD_WAIT_PRV_DAT_BIT:  0)
 423       /*b14     | CMD_ABRT_CMD_BIT        unused  */
 424       /*b15     | CMD_SEND_INIT_BIT       unused  */
 425    /*b20:16 */  |                                      CMD_CARD_NO(drive)
 426       /*b21     | CMD_SEND_CLK_ONLY       unused  */
 427       /*b22     | CMD_READ_CEATA          unused  */
 428       /*b23     | CMD_CCS_EXPECTED        unused  */
 429       /*b31 */  |                                      CMD_DONE_BIT;
 430
 431     wakeup_wait(&command_completion_signal, TIMEOUT_BLOCK);
 432
 433     MCI_MASK &= ~MCI_INT_CD;
 434
 435     /*  Handle command responses & errors */
 436     if(flags & MCI_RESP)
 437     {
 438         if(cmd_error & (MCI_INT_RCRC | MCI_INT_RTO))
 439             return false;
 440
 441         if(flags & MCI_LONG_RESP)
 442         {
 443             response[0] = MCI_RESP3;
 444             response[1] = MCI_RESP2;
 445             response[2] = MCI_RESP1;
 446             response[3] = MCI_RESP0;
 447         }
 448         else
 449             response[0] = MCI_RESP0;
 450     }
 451     return true;
 452 }
 453
 454 static int sd_init_card(const int drive)
 455 {
 456     unsigned long response;
 457     long init_timeout;
 458     bool sd_v2 = false;
 459
 460     /*  assume 24 MHz clock / 60 = 400 kHz  */
 461     MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C;    /* CLK_DIV_0 : bits 7:0  */
 462
 463     /* 100 - 400kHz clock required for Identification Mode  */
 464     /*  Start of Card Identification Mode ************************************/
 465
 466     /* CMD0 Go Idle  */
 467     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 468         return -1;
 469     mci_delay();
 470
 471     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 472       Non v2 cards will not respond to this command*/
 473     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 474         if((response & 0xFFF) == 0x1AA)
 475             sd_v2 = true;
 476
 477     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 478     init_timeout = current_tick + HZ;
 479
 480     do {
 481         /* this timeout is the only valid error for this loop*/
 482         if(TIME_AFTER(current_tick, init_timeout))
 483             return -2;
 484
 485         /* app_cmd */
 486         send_cmd(drive, SD_APP_CMD, 0, MCI_RESP, &response);
 487
 488          /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 489         if(!send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 490                         MCI_RESP, &card_info[drive].ocr))
 491             return -3;
 492     } while(!(card_info[drive].ocr & (1<<31)) );
 493
 494     /* CMD2 send CID */
 495     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info[drive].cid))
 496         return -4;
 497
 498     /* CMD3 send RCA */
 499     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 500         return -5;
 501
 502 #ifdef HAVE_MULTIDRIVE
 503     /* Make sure we have 2 unique rca numbers */
 504     if(card_info[INTERNAL_AS3525].rca == card_info[SD_SLOT_AS3525].rca)
 505         if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 506             return -6;
 507 #endif
 508     /*  End of Card Identification Mode   ************************************/
 509
 510     /* Attempt to switch cards to HS timings, non HS cards just ignore this */
 511     /*  CMD7 w/rca: Select card to put it in TRAN state */
 512     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 513         return -7;
 514
 515     if(sd_wait_for_state(drive, SD_TRAN))
 516         return -8;
 517
 518     /* CMD6 */
 519     if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
 520         return -9;
 521     mci_delay();
 522
 523     /*  We need to go back to STBY state now so we can read csd */
 524     /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 525     if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 526         return -10;
 527
 528     /* CMD9 send CSD */
 529     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 530                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 531         return -11;
 532
 533     sd_parse_csd(&card_info[drive]);
 534
 535     /*  Card back to full speed  */
 536     MCI_CLKDIV &= ~(0xFF);    /* CLK_DIV_0 : bits 7:0 = 0x00 */
 537
 538     /*  CMD7 w/rca: Select card to put it in TRAN state */
 539     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 540         return -12;
 541
 542 #ifndef BOOTLOADER
 543     /*  Switch to to 4 bit widebus mode  */
 544     if(sd_wait_for_state(drive, SD_TRAN) < 0)
 545         return -13;
 546     /* CMD55 */              /*  Response is requested due to timing issue  */
 547     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 548         return -14;
 549     /* ACMD6  */
 550     if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_NO_RESP, NULL))
 551         return -15;
 552     mci_delay();
 553     /* CMD55 */             /*  Response is requested due to timing issue  */
 554     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 555         return -16;
 556     /* ACMD42  */
 557     if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_NO_RESP, NULL))
 558         return -17;
 559     /* Now that card is widebus make controller aware */
 560     MCI_CTYPE |= (1<<drive);
 561 #endif
 562
 563     card_info[drive].initialized = 1;
 564
 565     MCI_CLKENA |= 1<<(drive + 16);      /*  Set low power mode  */
 566
 567     return 0;
 568 }
 569
 570 static void sd_thread(void) __attribute__((noreturn));
 571 static void sd_thread(void)
 572 {
 573     struct queue_event ev;
 574     bool idle_notified = false;
 575
 576     while (1)
 577     {
 578         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 579
 580         switch ( ev.id )
 581         {
 582 #ifdef HAVE_HOTSWAP
 583         case SYS_HOTSWAP_INSERTED:
 584         case SYS_HOTSWAP_EXTRACTED:
 585         {
 586             int microsd_init = 1;
 587             fat_lock();          /* lock-out FAT activity first -
 588                                     prevent deadlocking via disk_mount that
 589                                     would cause a reverse-order attempt with
 590                                     another thread */
 591             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 592                                     into driver that bypass the fat cache */
 593
 594             /* We now have exclusive control of fat cache and ata */
 595
 596             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 597                                     descriptors aren't leaked and any busy
 598                                     ones are invalid if mounting */
 599             /* Force card init for new card, re-init for re-inserted one or
 600              * clear if the last attempt to init failed with an error. */
 601             card_info[SD_SLOT_AS3525].initialized = 0;
 602
 603             if (ev.id == SYS_HOTSWAP_INSERTED)
 604             {
 605                 sd_enable(true);
 606                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 607                 if (microsd_init < 0) /* initialisation failed */
 608                     panicf("microSD init failed : %d", microsd_init);
 609
 610                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 611             }
 612
 613             /*
 614              * Mount succeeded, or this was an EXTRACTED event,
 615              * in both cases notify the system about the changed filesystems
 616              */
 617             if (microsd_init)
 618                 queue_broadcast(SYS_FS_CHANGED, 0);
 619             /* Access is now safe */
 620             mutex_unlock(&sd_mtx);
 621             fat_unlock();
 622             sd_enable(false);
 623         }
 624             break;
 625 #endif
 626         case SYS_TIMEOUT:
 627             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 628             {
 629                 idle_notified = false;
 630             }
 631             else
 632             {
 633                 /* never let a timer wrap confuse us */
 634                 next_yield = current_tick;
 635
 636                 if (!idle_notified)
 637                 {
 638                     call_storage_idle_notifys(false);
 639                     idle_notified = true;
 640                 }
 641             }
 642             break;
 643
 644         case SYS_USB_CONNECTED:
 645             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 646             /* Wait until the USB cable is extracted again */
 647             usb_wait_for_disconnect(&sd_queue);
 648
 649             break;
 650         case SYS_USB_DISCONNECTED:
 651             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 652             break;
 653         }
 654     }
 655 }
 656
 657 static void init_controller(void)
 658 {
 659     int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1;
 660     int card_mask = (1 << hcon_numcards) - 1;
 661
 662     MCI_PWREN &= ~card_mask;            /*  power off all cards  */
 663
 664     MCI_CLKSRC = 0x00;                  /* All CLK_SRC_CRD set to 0*/
 665     MCI_CLKDIV = 0x00;                  /* CLK_DIV_0 : bits 7:0  */
 666
 667     MCI_PWREN |= card_mask;             /*  power up cards  */
 668     mci_delay();
 669
 670     MCI_CTRL |= CTRL_RESET;
 671     while(MCI_CTRL & CTRL_RESET)
 672         ;
 673
 674     MCI_RAW_STATUS = 0xffffffff;        /* Clear all MCI Interrupts  */
 675
 676     MCI_TMOUT = 0xffffffff;             /*  data b31:8, response b7:0 */
 677
 678     MCI_CTYPE = 0x0;                    /*  all cards 1 bit bus for now */
 679
 680     MCI_CLKENA = card_mask;             /*  Enables card clocks  */
 681
 682     MCI_ARGUMENT = 0;
 683     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 684     while(MCI_COMMAND & CMD_DONE_BIT)
 685         ;
 686
 687     MCI_DEBNCE = 0xfffff;               /* default value */
 688
 689     /* Rx watermark = 63(sd reads)  Tx watermark = 128 (sd writes) */
 690     MCI_FIFOTH = (MCI_FIFOTH & MCI_FIFOTH_MASK) | 0x503f0080;
 691
 692     GPIOB_DIR |= (1<<5);                 /* Set pin B5 to output  */
 693
 694     /* Mask all MCI Interrupts initially  */
 695     MCI_MASK = 0;
 696
 697     MCI_CTRL |= INT_ENABLE;
 698 }
 699
 700 int sd_init(void)
 701 {
 702     int ret;
 703
 704     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 705
 706     CGU_IDE =   (1<<7)          /* AHB interface enable */
 707             |   (AS3525_IDE_DIV << 2)
 708             |   1;              /* clock source = PLLA */
 709
 710     CGU_MEMSTICK =  (1<<7)      /* interface enable */
 711                  |  (AS3525_MS_DIV << 2)
 712                  |  1;          /* clock source = PLLA */
 713
 714     CGU_SDSLOT = (1<<7)         /* interface enable */
 715                | (AS3525_SDSLOT_DIV << 2)
 716                | 1;             /* clock source = PLLA */
 717
 718     wakeup_init(&transfer_completion_signal);
 719     wakeup_init(&command_completion_signal);
 720 #ifdef HAVE_MULTIDRIVE
 721     /* clear previous irq */
 722     GPIOA_IC = EXT_SD_BITS;
 723     /* enable edge detecting */
 724     GPIOA_IS &= ~EXT_SD_BITS;
 725     /* detect both raising and falling edges */
 726     GPIOA_IBE |= EXT_SD_BITS;
 727     /* Configure XPD for SD-MCI interface */
 728     CCU_IO |= (1<<2);
 729 #endif
 730
 731     VIC_INT_ENABLE = INTERRUPT_NAND;
 732
 733     init_controller();
 734     ret = sd_init_card(INTERNAL_AS3525);
 735     if(ret < 0)
 736         return ret;
 737
 738     /* init mutex */
 739     mutex_init(&sd_mtx);
 740
 741     queue_init(&sd_queue, true);
 742     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 743             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 744
 745 #ifndef BOOTLOADER
 746     sd_enabled = true;
 747     sd_enable(false);
 748 #endif
 749     return 0;
 750 }
 751
 752 static int sd_wait_for_state(const int drive, unsigned int state)
 753 {
 754     unsigned long response;
 755     unsigned int timeout = 100; /* ticks */
 756     long t = current_tick;
 757
 758     while (1)
 759     {
 760         long tick;
 761
 762         while(!(send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP, &response)));
 763
 764         if (((response >> 9) & 0xf) == state)
 765             return 0;
 766
 767         if(TIME_AFTER(current_tick, t + timeout))
 768             return -10 * ((response >> 9) & 0xf);
 769
 770         if (TIME_AFTER((tick = current_tick), next_yield))
 771         {
 772             yield();
 773             timeout += current_tick - tick;
 774             next_yield = tick + MIN_YIELD_PERIOD;
 775         }
 776     }
 777 }
 778
 779 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 780                                 int count, void* buf, bool write)
 781 {
 782     int ret = 0;
 783 #ifndef HAVE_MULTIDRIVE
 784     const int drive = 0;
 785 #endif
 786
 787     /* skip SanDisk OF */
 788     if (drive == INTERNAL_AS3525)
 789         start += 0xf000;
 790
 791     mutex_lock(&sd_mtx);
 792 #ifndef BOOTLOADER
 793     sd_enable(true);
 794     led(true);
 795 #endif
 796
 797     if (card_info[drive].initialized <= 0)
 798     {
 799         ret = sd_init_card(drive);
 800         if (!(card_info[drive].initialized))
 801         {
 802             panicf("card not initialised (%d)", ret);
 803             goto sd_transfer_error;
 804         }
 805     }
 806
 807     /*  CMD7 w/rca: Select card to put it in TRAN state */
 808     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 809         return -18;
 810
 811     last_disk_activity = current_tick;
 812     dma_retain();
 813
 814     const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 815
 816     do
 817     {
 818         void *dma_buf = aligned_buffer;
 819         unsigned int transfer = count;
 820         if(transfer > UNALIGNED_NUM_SECTORS)
 821             transfer = UNALIGNED_NUM_SECTORS;
 822
 823         if(write)
 824             memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 825
 826         /* Interrupt handler might set this to true during transfer */
 827         retry = false;
 828
 829         MCI_BLKSIZ = SD_BLOCK_SIZE;
 830         MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
 831
 832         ret = sd_wait_for_state(drive, SD_TRAN);
 833         if (ret < 0)
 834         {
 835             static const char *st[9] = {
 836                 "IDLE", "RDY", "IDENT", "STBY", "TRAN", "DATA", "RCV",
 837                                                                 "PRG", "DIS"};
 838             if(ret <= -10)
 839                 panicf("wait for TRAN state failed (%s) %d",
 840                                                     st[(-ret / 10) % 9], drive);
 841             else
 842                 panicf("wait for state failed");
 843             goto sd_transfer_error;
 844         }
 845
 846         int arg = start;
 847         if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
 848             arg *= SD_BLOCK_SIZE;
 849
 850         if(write)
 851             dma_enable_channel(0, dma_buf, MCI_FIFO, DMA_PERI_SD,
 852                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 853         else
 854             dma_enable_channel(0, MCI_FIFO, dma_buf, DMA_PERI_SD,
 855                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 856
 857         MCI_MASK |= (MCI_DATA_ERROR | MCI_INT_DTO);
 858         MCI_CTRL |= DMA_ENABLE;
 859
 860         unsigned long dummy; /* if we don't ask for a response, writing fails */
 861         if(!send_cmd(drive, cmd, arg, MCI_RESP, &dummy))
 862             panicf("%s multiple blocks failed", write ? "write" : "read");
 863
 864         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 865
 866         MCI_MASK &= ~(MCI_DATA_ERROR | MCI_INT_DTO);
 867
 868         last_disk_activity = current_tick;
 869
 870         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
 871         {
 872             ret = -666;
 873             panicf("STOP TRANSMISSION failed");
 874             goto sd_transfer_error;
 875         }
 876
 877         if(!retry)
 878         {
 879             if(!write)
 880                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 881             buf += transfer * SD_BLOCK_SIZE;
 882             start += transfer;
 883             count -= transfer;
 884         }
 885         else   /*  reset controller if we had an error  */
 886         {
 887             MCI_CTRL |= (FIFO_RESET|DMA_RESET);
 888             while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
 889                 ;
 890         }
 891
 892     } while(retry || count);
 893
 894     dma_release();
 895
 896     /* CMD lines are separate, not common, so we need to actively deselect */
 897     /*  CMD7 w/rca =0 : deselects card & puts it in STBY state */
 898     if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 899         return -19;
 900
 901 #ifndef BOOTLOADER
 902     sd_enable(false);
 903     led(false);
 904 #endif
 905     mutex_unlock(&sd_mtx);
 906     return 0;
 907
 908 sd_transfer_error:
 909     panicf("transfer error : %d",ret);
 910     card_info[drive].initialized = 0;
 911     return ret;
 912 }
 913
 914 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 915                     void* buf)
 916 {
 917     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 918 }
 919
 920 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 921                      const void* buf)
 922 {
 923 #if defined(BOOTLOADER) /* we don't need write support in bootloader */
 924 #ifdef HAVE_MULTIDRIVE
 925     (void) drive;
 926 #endif
 927     (void) start;
 928     (void) count;
 929     (void) buf;
 930     return -1;
 931 #else
 932     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 933 #endif /* defined(BOOTLOADER) */
 934 }
 935
 936 #ifndef BOOTLOADER
 937 long sd_last_disk_activity(void)
 938 {
 939     return last_disk_activity;
 940 }
 941
 942 void sd_enable(bool on)
 943 {
 944     /* TODO */
 945     (void) on;
 946 }
 947
 948 tCardInfo *card_get_info_target(int card_no)
 949 {
 950     return &card_info[card_no];
 951 }
 952 #endif /* BOOTLOADER */
 953
 954 #ifdef HAVE_HOTSWAP
 955 bool sd_removable(IF_MD_NONVOID(int drive))
 956 {
 957     return (drive==1);
 958 }
 959
 960 bool sd_present(IF_MD_NONVOID(int drive))
 961 {
 962     return (drive == 0) ? true : card_detect_target();
 963 }
 964
 965 static int sd1_oneshot_callback(struct timeout *tmo)
 966 {
 967     (void)tmo;
 968
 969     /* This is called only if the state was stable for 300ms - check state
 970      * and post appropriate event. */
 971     if (card_detect_target())
 972     {
 973         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 974     }
 975     else
 976         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 977
 978     return 0;
 979 }
 980
 981 void sd_gpioa_isr(void)
 982 {
 983     static struct timeout sd1_oneshot;
 984     if (GPIOA_MIS & EXT_SD_BITS)
 985         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 986     /* acknowledge interrupt */
 987     GPIOA_IC = EXT_SD_BITS;
 988 }
 989
 990 void card_enable_monitoring_target(bool on)
 991 {
 992     if (on) /* enable interrupt */
 993         GPIOA_IE |= EXT_SD_BITS;
 994     else    /* disable interrupt */
 995         GPIOA_IE &= ~EXT_SD_BITS;
 996 }
 997 #endif /* HAVE_HOTSWAP */
 998
 999 #ifdef CONFIG_STORAGE_MULTI
1000 int sd_num_drives(int first_drive)
1001 {
1002     /* We don't care which logical drive number(s) we have been assigned */
1003     (void)first_drive;
1004
1005     return NUM_DRIVES;
1006 }
1007 #endif /* CONFIG_STORAGE_MULTI */