firmware/target/arm/imx31/avic-imx31.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by James Espinoza
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef AVIC_IMX31_H
  22 #define AVIC_IMX31_H
  23
  24 struct avic_map
  25 {
  26     volatile uint32_t intcntl;              /* 00h */
  27     volatile uint32_t nimask;               /* 04h */
  28     volatile uint32_t intennum;             /* 08h */
  29     volatile uint32_t intdisnum;            /* 0Ch */
  30     union                                   /* 10h */
  31     {
  32         struct
  33         {
  34             volatile uint32_t intenableh;   /* 10h */
  35             volatile uint32_t intenablel;   /* 14h */
  36         };
  37         volatile uint32_t intenable[2];     /* H,L */
  38     };
  39     union
  40     {
  41         struct
  42         {
  43             volatile uint32_t inttypeh;     /* 18h */
  44             volatile uint32_t inttypel;     /* 1Ch */
  45         };
  46         volatile uint32_t inttype[2];       /* H,L */
  47     };
  48     union
  49     {
  50         struct
  51         {
  52             volatile uint32_t nipriority7;  /* 20h */
  53             volatile uint32_t nipriority6;  /* 24h */
  54             volatile uint32_t nipriority5;  /* 28h */
  55             volatile uint32_t nipriority4;  /* 2Ch */
  56             volatile uint32_t nipriority3;  /* 30h */
  57             volatile uint32_t nipriority2;  /* 34h */
  58             volatile uint32_t nipriority1;  /* 38h */
  59             volatile uint32_t nipriority0;  /* 3Ch */
  60         };
  61         volatile uint32_t nipriority[8];    /* 7-0 */
  62     };
  63     volatile uint32_t nivecsr;              /* 40h */
  64     volatile uint32_t fivecsr;              /* 44h */
  65     union
  66     {
  67         struct
  68         {
  69             volatile uint32_t intsrch;      /* 48h */
  70             volatile uint32_t intsrcl;      /* 4Ch */
  71         };
  72         volatile uint32_t intsrc[2];        /* H,L */
  73     };
  74     union
  75     {
  76         struct
  77         {
  78             volatile uint32_t intfrch;      /* 50h */
  79             volatile uint32_t intfrcl;      /* 54h */
  80         };
  81         volatile uint32_t intfrc[2];        /* H,L */
  82     };
  83     union
  84     {
  85         struct
  86         {
  87             volatile uint32_t nipndh;       /* 58h */
  88             volatile uint32_t nipndl;       /* 5Ch */
  89         };
  90         volatile uint32_t nipnd[2];         /* H,L */
  91     };
  92     union
  93     {
  94         struct
  95         {
  96             volatile uint32_t fipndh;       /* 60h */
  97             volatile uint32_t fipndl;       /* 64h */
  98         };
  99         volatile uint32_t fipnd[2];         /* H,L */
 100     };
 101     volatile uint32_t skip1[0x26];          /* 68h */
 102     union                                   /* 100h */
 103     {
 104         struct
 105         {
 106             volatile uint32_t reserved0;
 107             volatile uint32_t reserved1;
 108             volatile uint32_t reserved2;
 109             volatile uint32_t i2c3;
 110             volatile uint32_t i2c2;
 111             volatile uint32_t mpeg4encoder;
 112             volatile uint32_t rtic;
 113             volatile uint32_t fir;
 114             volatile uint32_t mmc_sdhc2;
 115             volatile uint32_t mmc_sdhc1;
 116             volatile uint32_t i2c1;
 117             volatile uint32_t ssi2;
 118             volatile uint32_t ssi1;
 119             volatile uint32_t cspi2;
 120             volatile uint32_t cspi1;
 121             volatile uint32_t ata;
 122             volatile uint32_t mbx;
 123             volatile uint32_t cspi3;
 124             volatile uint32_t uart3;
 125             volatile uint32_t iim;
 126             volatile uint32_t sim1;
 127             volatile uint32_t sim2;
 128             volatile uint32_t rnga;
 129             volatile uint32_t evtmon;
 130             volatile uint32_t kpp;
 131             volatile uint32_t rtc;
 132             volatile uint32_t pwn;
 133             volatile uint32_t epit2;
 134             volatile uint32_t epit1;
 135             volatile uint32_t gpt;
 136             volatile uint32_t pwr_fail;
 137             volatile uint32_t ccm_dvfs;
 138             volatile uint32_t uart2;
 139             volatile uint32_t nandfc;
 140             volatile uint32_t sdma;
 141             volatile uint32_t usb_host1;
 142             volatile uint32_t usb_host2;
 143             volatile uint32_t usb_otg;
 144             volatile uint32_t reserved3;
 145             volatile uint32_t mshc1;
 146             volatile uint32_t mshc2;
 147             volatile uint32_t ipu_err;
 148             volatile uint32_t ipu;
 149             volatile uint32_t reserved4;
 150             volatile uint32_t reserved5;
 151             volatile uint32_t uart1;
 152             volatile uint32_t uart4;
 153             volatile uint32_t uart5;
 154             volatile uint32_t etc_irq;
 155             volatile uint32_t scc_scm;
 156             volatile uint32_t scc_smn;
 157             volatile uint32_t gpio2;
 158             volatile uint32_t gpio1;
 159             volatile uint32_t ccm_clk;
 160             volatile uint32_t pcmcia;
 161             volatile uint32_t wdog;
 162             volatile uint32_t gpio3;
 163             volatile uint32_t reserved6;
 164             volatile uint32_t ext_pwmg;
 165             volatile uint32_t ext_temp;
 166             volatile uint32_t ext_sense1;
 167             volatile uint32_t ext_sense2;
 168             volatile uint32_t ext_wdog;
 169             volatile uint32_t ext_tv;
 170         };
 171         volatile uint32_t vector[0x40];     /* 100h */
 172     };
 173 };
 174
 175 /* #define IRQ priorities for different modules (0-15) */
 176 #define INT_PRIO_DEFAULT    7
 177 #define INT_PRIO_DVFS       (INT_PRIO_DEFAULT+1)
 178 #define INT_PRIO_DPTC       (INT_PRIO_DEFAULT+1)
 179 #define INT_PRIO_SDMA       (INT_PRIO_DEFAULT+2)
 180
 181 enum INT_TYPE
 182 {
 183     INT_TYPE_IRQ = 0,
 184     INT_TYPE_FIQ
 185 };
 186
 187 enum IMX31_INT_LIST
 188 {
 189     __IMX31_INT_FIRST = -1,
 190    INT_RESERVED0, INT_RESERVED1,     INT_RESERVED2, INT_I2C3,
 191    INT_I2C2,      INT_MPEG4_ENCODER, INT_RTIC,      INT_FIR,
 192    INT_MMC_SDHC2, INT_MMC_SDHC1,     INT_I2C1,      INT_SSI2,
 193    INT_SSI1,      INT_CSPI2,         INT_CSPI1,     INT_ATA,
 194    INT_MBX,       INT_CSPI3,         INT_UART3,     INT_IIM,
 195    INT_SIM1,      INT_SIM2,          INT_RNGA,      INT_EVTMON,
 196    INT_KPP,       INT_RTC,           INT_PWN,       INT_EPIT2,
 197    INT_EPIT1,     INT_GPT,           INT_PWR_FAIL,  INT_CCM_DVFS,
 198    INT_UART2,     INT_NANDFC,        INT_SDMA,      INT_USB_HOST1,
 199    INT_USB_HOST2, INT_USB_OTG,       INT_RESERVED3, INT_MSHC1,
 200    INT_MSHC2,     INT_IPU_ERR,       INT_IPU,       INT_RESERVED4,
 201    INT_RESERVED5, INT_UART1,         INT_UART4,     INT_UART5,
 202    INT_ETC_IRQ,   INT_SCC_SCM,       INT_SCC_SMN,   INT_GPIO2,
 203    INT_GPIO1,     INT_CCM_CLK,       INT_PCMCIA,    INT_WDOG,
 204    INT_GPIO3,     INT_RESERVED6,     INT_EXT_PWMG,  INT_EXT_TEMP,
 205    INT_EXT_SENS1, INT_EXT_SENS2,     INT_EXT_WDOG,  INT_EXT_TV,
 206    INT_ALL
 207 };
 208
 209 void avic_init(void);
 210 void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype,
 211                      unsigned long ni_priority, void (*handler)(void));
 212 void avic_set_int_priority(enum IMX31_INT_LIST ints,
 213                            unsigned long ni_priority);
 214 void avic_disable_int(enum IMX31_INT_LIST ints);
 215 void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype);
 216
 217 #define AVIC_NIL_DISABLE 15
 218 #define AVIC_NIL_ENABLE  (-1)
 219 void avic_set_ni_level(int level);
 220
 221
 222 /* Call a service routine while allowing preemption by interrupts of higher
 223  * priority. Avoid using any app or other SVC stack by doing it with a mini
 224  * "stack on irq stack". Avoid actually enabling IRQ until the routine
 225  * decides to do so; epilogue code will always disable them again. */
 226 #define AVIC_NESTED_NI_CALL_PROLOGUE(prio, stacksize) \
 227 ({ asm volatile ( \
 228         "sub    lr, lr, #4               \n" /* prepare return address */ \
 229         "srsdb  #0x12!                   \n" /* save LR_irq and SPSR_irq */ \
 230         "stmfd  sp!, { r0-r3, r12 }      \n" /* preserve context */ \
 231         "mov    r0, #0x68000000          \n" /* AVIC_BASE_ADDR */ \
 232         "mov    r1, %0                   \n" /* load interrupt level */ \
 233         "ldr    r2, [r0, #0x04]          \n" /* save NIMASK */ \
 234         "str    r1, [r0, #0x04]          \n" /* set interrupt level */ \
 235         "mov    r0, sp                   \n" /* grab IRQ stack */ \
 236         "sub    sp, sp, %1               \n" /* allocate space for routine to SP_irq */ \
 237         "cps    #0x13                    \n" /* change to SVC mode */ \
 238         "mov    r1, sp                   \n" /* save SP_svc */ \
 239         "mov    sp, r0                   \n" /* switch to SP_irq *copy* */ \
 240         "stmfd  sp!, { r1, r2, lr }      \n" /* push SP_svc, NIMASK and LR_svc */ \
 241         : : "i"(prio), "i"(stacksize)); })
 242
 243 #define AVIC_NESTED_NI_CALL_EPILOGUE(stacksize) \
 244 ({ asm volatile ( \
 245         "cpsid  i                        \n" /* disable IRQ */ \
 246         "ldmfd  sp!, { r1, r2, lr }      \n" /* pop SP_svc, NIMASK and LR_svc */ \
 247         "mov    sp, r1                   \n" /* restore SP_svc */ \
 248         "cps    #0x12                    \n" /* return to IRQ mode */ \
 249         "add    sp, sp, %0               \n" /* deallocate routine space */ \
 250         "mov    r0, #0x68000000          \n" /* AVIC BASE ADDR */ \
 251         "str    r2, [r0, #0x04]          \n" /* restore NIMASK */ \
 252         "ldmfd  sp!, { r0-r3, r12 }      \n" /* reload context */ \
 253         "rfefd  sp!                      \n" /* move stacked SPSR to CPSR, return */ \
 254         : : "i"(stacksize)); })
 255
 256 #endif /* AVIC_IMX31_H */