1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (c) 2008 by Michael Sevakis
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
23 #include "spi-imx31.h"
24 #include "gpio-imx31.h"
30 #define PMIC_DRIVER_CLOSE
33 /* This is all based on communicating with the MC13783 PMU which is on
34 * CSPI2 with the chip select at 0. The LCD controller resides on
35 * CSPI3 cs1, but we have no idea how to communicate to it */
36 static struct spi_node mc13783_spi
=
38 CSPI2_NUM
, /* CSPI module 2 */
39 CSPI_CONREG_CHIP_SELECT_SS0
| /* Chip select 0 */
40 CSPI_CONREG_DRCTL_DONT_CARE
| /* Don't care about CSPI_RDY */
41 CSPI_CONREG_DATA_RATE_DIV_4
| /* Clock = IPG_CLK/4 - 16.5MHz */
42 CSPI_BITCOUNT(32-1) | /* All 32 bits are to be transferred */
43 CSPI_CONREG_SSPOL
| /* SS active high */
44 CSPI_CONREG_SSCTL
| /* Negate SS between SPI bursts */
45 CSPI_CONREG_MODE
, /* Master mode */
46 0, /* SPI clock - no wait states */
49 extern const struct mc13783_event_list mc13783_event_list
;
51 static int mc13783_thread_stack
[DEFAULT_STACK_SIZE
/sizeof(int)];
52 static const char *mc13783_thread_name
= "pmic";
53 static struct wakeup mc13783_wake
;
55 /* Tracking for which interrupts are enabled */
56 static uint32_t pmic_int_enabled
[2] =
57 { 0x00000000, 0x00000000 };
59 static const unsigned char pmic_intm_regs
[2] =
60 { MC13783_INTERRUPT_MASK0
, MC13783_INTERRUPT_MASK1
};
62 static const unsigned char pmic_ints_regs
[2] =
63 { MC13783_INTERRUPT_STATUS0
, MC13783_INTERRUPT_STATUS1
};
65 #ifdef PMIC_DRIVER_CLOSE
66 static bool pmic_close
= false;
67 static unsigned int mc13783_thread_id
= 0;
70 static void mc13783_interrupt_thread(void)
74 /* Enable mc13783 GPIO event */
75 gpio_enable_event(MC13783_EVENT_ID
);
79 const struct mc13783_event
*event
, *event_last
;
81 wakeup_wait(&mc13783_wake
, TIMEOUT_BLOCK
);
83 #ifdef PMIC_DRIVER_CLOSE
88 mc13783_read_regset(pmic_ints_regs
, pending
, 2);
90 /* Only clear interrupts being dispatched */
91 pending
[0] &= pmic_int_enabled
[0];
92 pending
[1] &= pmic_int_enabled
[1];
94 mc13783_write_regset(pmic_ints_regs
, pending
, 2);
96 /* Whatever is going to be serviced in this loop has been
97 * acknowledged. Reenable interrupt and if anything was still
98 * pending or became pending again, another signal will be
100 imx31_regset32(&MC13783_GPIO_IMR
, 1ul << MC13783_GPIO_LINE
);
102 event
= mc13783_event_list
.events
;
103 event_last
= event
+ mc13783_event_list
.count
;
105 /* .count is surely expected to be > 0 */
108 enum mc13783_event_sets set
= event
->set
;
109 uint32_t pnd
= pending
[set
];
110 uint32_t mask
= event
->mask
;
119 if ((pending
[0] | pending
[1]) == 0)
120 break; /* Teminate early if nothing more to service */
122 while (++event
< event_last
);
125 #ifdef PMIC_DRIVER_CLOSE
126 gpio_disable_event(MC13783_EVENT_ID
);
130 /* GPIO interrupt handler for mc13783 */
131 void mc13783_event(void)
133 /* Mask the interrupt (unmasked when PMIC thread services it). */
134 imx31_regclr32(&MC13783_GPIO_IMR
, 1ul << MC13783_GPIO_LINE
);
135 MC13783_GPIO_ISR
= (1ul << MC13783_GPIO_LINE
);
136 wakeup_signal(&mc13783_wake
);
139 void mc13783_init(void)
141 /* Serial interface must have been initialized first! */
142 wakeup_init(&mc13783_wake
);
144 /* Enable the PMIC SPI module */
145 spi_enable_module(&mc13783_spi
);
147 /* Mask any PMIC interrupts for now - modules will enable them as
149 mc13783_write(MC13783_INTERRUPT_MASK0
, 0xffffff);
150 mc13783_write(MC13783_INTERRUPT_MASK1
, 0xffffff);
152 MC13783_GPIO_ISR
= (1ul << MC13783_GPIO_LINE
);
154 #ifdef PMIC_DRIVER_CLOSE
157 create_thread(mc13783_interrupt_thread
,
158 mc13783_thread_stack
, sizeof(mc13783_thread_stack
), 0,
159 mc13783_thread_name
IF_PRIO(, PRIORITY_REALTIME
) IF_COP(, CPU
));
162 #ifdef PMIC_DRIVER_CLOSE
163 void mc13783_close(void)
165 unsigned int thread_id
= mc13783_thread_id
;
170 mc13783_thread_id
= 0;
173 wakeup_signal(&mc13783_wake
);
174 thread_wait(thread_id
);
176 #endif /* PMIC_DRIVER_CLOSE */
178 bool mc13783_enable_event(enum mc13783_event_ids id
)
180 const struct mc13783_event
* const event
=
181 &mc13783_event_list
.events
[id
];
182 int set
= event
->set
;
183 uint32_t mask
= event
->mask
;
185 spi_lock(&mc13783_spi
);
187 pmic_int_enabled
[set
] |= mask
;
188 mc13783_clear(pmic_intm_regs
[set
], mask
);
190 spi_unlock(&mc13783_spi
);
195 void mc13783_disable_event(enum mc13783_event_ids id
)
197 const struct mc13783_event
* const event
=
198 &mc13783_event_list
.events
[id
];
199 int set
= event
->set
;
200 uint32_t mask
= event
->mask
;
202 spi_lock(&mc13783_spi
);
204 pmic_int_enabled
[set
] &= ~mask
;
205 mc13783_set(pmic_intm_regs
[set
], mask
);
207 spi_unlock(&mc13783_spi
);
210 uint32_t mc13783_set(unsigned address
, uint32_t bits
)
212 spi_lock(&mc13783_spi
);
214 uint32_t data
= mc13783_read(address
);
216 if (data
!= MC13783_DATA_ERROR
)
217 mc13783_write(address
, data
| bits
);
219 spi_unlock(&mc13783_spi
);
224 uint32_t mc13783_clear(unsigned address
, uint32_t bits
)
226 spi_lock(&mc13783_spi
);
228 uint32_t data
= mc13783_read(address
);
230 if (data
!= MC13783_DATA_ERROR
)
231 mc13783_write(address
, data
& ~bits
);
233 spi_unlock(&mc13783_spi
);
238 int mc13783_write(unsigned address
, uint32_t data
)
240 struct spi_transfer xfer
;
243 if (address
>= MC13783_NUM_REGS
)
246 packet
= (1 << 31) | (address
<< 25) | (data
& 0xffffff);
247 xfer
.txbuf
= &packet
;
248 xfer
.rxbuf
= &packet
;
251 if (!spi_transfer(&mc13783_spi
, &xfer
))
254 return 1 - xfer
.count
;
257 uint32_t mc13783_write_masked(unsigned address
, uint32_t data
, uint32_t mask
)
261 spi_lock(&mc13783_spi
);
263 old
= mc13783_read(address
);
265 if (old
!= MC13783_DATA_ERROR
)
267 data
= (old
& ~mask
) | (data
& mask
);
269 if (mc13783_write(address
, data
) != 1)
270 old
= MC13783_DATA_ERROR
;
273 spi_unlock(&mc13783_spi
);
278 int mc13783_write_regset(const unsigned char *regs
, const uint32_t *data
,
282 struct spi_transfer xfer
;
283 uint32_t packets
[MC13783_NUM_REGS
];
285 if ((unsigned)count
> MC13783_NUM_REGS
)
288 for (i
= 0; i
< count
; i
++)
290 uint32_t reg
= regs
[i
];
292 if (reg
>= MC13783_NUM_REGS
)
295 packets
[i
] = (1 << 31) | (reg
<< 25) | (data
[i
] & 0xffffff);
298 xfer
.txbuf
= packets
;
299 xfer
.rxbuf
= packets
;
302 if (!spi_transfer(&mc13783_spi
, &xfer
))
305 return count
- xfer
.count
;
308 uint32_t mc13783_read(unsigned address
)
311 struct spi_transfer xfer
;
313 if (address
>= MC13783_NUM_REGS
)
314 return MC13783_DATA_ERROR
;
316 packet
= address
<< 25;
318 xfer
.txbuf
= &packet
;
319 xfer
.rxbuf
= &packet
;
322 if (!spi_transfer(&mc13783_spi
, &xfer
))
323 return MC13783_DATA_ERROR
;
328 int mc13783_read_regset(const unsigned char *regs
, uint32_t *buffer
,
332 struct spi_transfer xfer
;
334 if ((unsigned)count
> MC13783_NUM_REGS
)
337 for (i
= 0; i
< count
; i
++)
339 unsigned reg
= regs
[i
];
341 if (reg
>= MC13783_NUM_REGS
)
344 buffer
[i
] = reg
<< 25;
351 if (!spi_transfer(&mc13783_spi
, &xfer
))
354 return count
- xfer
.count
;