?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Trim down peak calculation a bit.
[kugel-rb.git] / firmware / export / imx31l.h
blobea92d059cc061fd9913d3e32b814892d7ed3070b
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2006 by James Espinoza
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21 #ifndef __IMX31L_H__
22 #define __IMX31L_H__
23
24 /* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/
25
26 #define REG8_PTR_T volatile unsigned char *
27 #define REG16_PTR_T volatile unsigned short *
28 #define REG32_PTR_T volatile unsigned long *
29
30 /* Place in the section with the framebuffer */
31 #define TTB_BASE_ADDR (CSD0_BASE_ADDR + (MEM*0x100000) - TTB_SIZE)
32 #define TTB_SIZE (0x4000)
33 #define IRAM_SIZE (0x4000)
34 #define TTB_BASE ((unsigned long *)TTB_BASE_ADDR)
35 #define FRAME_SIZE (240*320*2)
36 /* Rockbox framebuffer address, not retail OS */
37 #define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE)
38 #define FRAME ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR))
39
40 #define CACHEALIGN_SIZE 32
41 #define NOCACHE_BASE CSD0_BASE_ADDR
42
43 /* USBOTG */
44 #define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048)))
45 #define USB_NUM_ENDPOINTS 8
46 #define USB_DEVBSS_ATTR NOCACHEBSS_ATTR
47 #define USB_BASE OTG_BASE_ADDR
48 #define QHARRAY_SIZE ((64*USB_NUM_ENDPOINTS*2 + 2047) & (0xffffffff - 2047))
49 #define QHARRAY_PHYS_ADDR ((FRAME_PHYS_ADDR - QHARRAY_SIZE) & (0xffffffff - 2047))
50
51 /*
52 * AIPS 1
53 */
54 #define IRAM_BASE_ADDR 0x1fffc000
55 #define L2CC_BASE_ADDR 0x30000000
56 #define AIPS1_BASE_ADDR 0x43F00000
57 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
58 #define MAX_BASE_ADDR 0x43F04000
59 #define EVTMON_BASE_ADDR 0x43F08000
60 #define CLKCTL_BASE_ADDR 0x43F0C000
61 #define ETB_SLOT4_BASE_ADDR 0x43F10000
62 #define ETB_SLOT5_BASE_ADDR 0x43F14000
63 #define ECT_CTIO_BASE_ADDR 0x43F18000
64 #define I2C1_BASE_ADDR 0x43F80000
65 #define I2C3_BASE_ADDR 0x43F84000
66 #define OTG_BASE_ADDR 0x43F88000
67 #define ATA_BASE_ADDR 0x43F8C000
68 #define UART1_BASE_ADDR 0x43F90000
69 #define UART2_BASE_ADDR 0x43F94000
70 #define I2C2_BASE_ADDR 0x43F98000
71 #define OWIRE_BASE_ADDR 0x43F9C000
72 #define SSI1_BASE_ADDR 0x43FA0000
73 #define CSPI1_BASE_ADDR 0x43FA4000
74 #define KPP_BASE_ADDR 0x43FA8000
75 #define IOMUXC_BASE_ADDR 0x43FAC000
76 #define UART4_BASE_ADDR 0x43FB0000
77 #define UART5_BASE_ADDR 0x43FB4000
78 #define ECT_IP1_BASE_ADDR 0x43FB8000
79 #define ECT_IP2_BASE_ADDR 0x43FBC000
80
81 /*
82 * SPBA
83 */
84 #define SPBA_BASE_ADDR 0x50000000
85 #define MMC_SDHC1_BASE_ADDR 0x50004000
86 #define MMC_SDHC2_BASE_ADDR 0x50008000
87 #define UART3_BASE_ADDR 0x5000C000
88 #define CSPI2_BASE_ADDR 0x50010000
89 #define SSI2_BASE_ADDR 0x50014000
90 #define SIM_BASE_ADDR 0x50018000
91 #define IIM_BASE_ADDR 0x5001C000
92 #define ATA_DMA_BASE_ADDR 0x50020000
93 #define SPBA_CTRL_BASE_ADDR 0x5003C000
94
95 /*
96 * AIPS 2
97 */
98 #define AIPS2_BASE_ADDR 0x53F00000
99 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
100 #define CCM_BASE_ADDR 0x53F80000
101 #define CSPI3_BASE_ADDR 0x53F84000
102 #define FIRI_BASE_ADDR 0x53F8C000
103 #define GPT1_BASE_ADDR 0x53F90000
104 #define EPIT1_BASE_ADDR 0x53F94000
105 #define EPIT2_BASE_ADDR 0x53F98000
106 #define GPIO3_BASE_ADDR 0x53FA4000
107 #define SCC_BASE 0x53FAC000
108 #define SCM_BASE 0x53FAE000
109 #define SMN_BASE 0x53FAF000
110 #define RNGA_BASE_ADDR 0x53FB0000
111 #define IPU_CTRL_BASE_ADDR 0x53FC0000
112 #define AUDMUX_BASE 0x53FC4000
113 #define MPEG4_ENC_BASE 0x53FC8000
114 #define GPIO1_BASE_ADDR 0x53FCC000
115 #define GPIO2_BASE_ADDR 0x53FD0000
116 #define SDMA_BASE_ADDR 0x53FD4000
117 #define RTC_BASE_ADDR 0x53FD8000
118 #define WDOG_BASE_ADDR 0x53FDC000
119 #define PWM_BASE_ADDR 0x53FE0000
120 #define RTIC_BASE_ADDR 0x53FEC000
121
122 #define WDOG1_BASE_ADDR WDOG_BASE_ADDR
123 #define CRM_MCU_BASE_ADDR CCM_BASE_ADDR
124
125 /* IIM */
126 #define IIM_PREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x20))
127 #define IIM_PREV_SIG (0x1f << 3)
128 #define IIM_PREV_SIG_IMX31 (0x01 << 3) /* i.MX31 */
129 #define IIM_SREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x24))
130 #define IIM_SREV_SREV (0xff << 0)
131 #define IIM_SREV_1_0 0x00 /* i.MX31/L 1.0, L38W */
132 #define IIM_SREV_1_1 0x10 /* i.MX31 1.1, 2L38W */
133 #define IIM_SREV_1_1L 0x11 /* i.MX31L 1.1, 2L38W */
134 #define IIM_SREV_1_15 0x12 /* i.MX31 1.15, 2L38W/3L38W */
135 #define IIM_SREV_1_15L 0x13 /* i.MX31L 1.15, 2L38W/3L38W */
136 #define IIM_SREV_1_2 0x14 /* i.MX31 1.2, 3L38W, M45G */
137 #define IIM_SREV_1_2L 0x15 /* i.MX31L 1.2, 3L38W, M45G */
138 #define IIM_SREV_2_0_1 0x28 /* i.MX31 2.0/2.0.1, M91E */
139 #define IIM_SREV_2_0_1L 0x29 /* i.MX31L 2.0/2.0.1, M91E */
140
141 /* IOMUXC */
142 #define IOMUXC_GPR (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+0x008))
143
144 /* SW_MUX_CTL_* */
145 #define IOMUXC_MUX_OUT (0x7 << 4)
146 #define IOMUXC_MUX_OUT_POS (4)
147 #define IOMUXC_MUX_IN (0xf << 0)
148 #define IOMUXC_MUX_IN_POS (0)
149 #define IOMUXC_MUX_MASK (0x7f)
150
151 #define IOMUXC_MUX_OUT_GPIO (0x0 << IOMUXC_MUX_OUT_POS)
152 #define IOMUXC_MUX_OUT_FUNCTIONAL (0x1 << IOMUXC_MUX_OUT_POS)
153 #define IOMUXC_MUX_OUT_ALT1 (0x2 << IOMUXC_MUX_OUT_POS)
154 #define IOMUXC_MUX_OUT_ALT2 (0x3 << IOMUXC_MUX_OUT_POS)
155 #define IOMUXC_MUX_OUT_ALT3 (0x4 << IOMUXC_MUX_OUT_POS)
156 #define IOMUXC_MUX_OUT_ALT4 (0x5 << IOMUXC_MUX_OUT_POS)
157 #define IOMUXC_MUX_OUT_ALT5 (0x6 << IOMUXC_MUX_OUT_POS)
158 #define IOMUXC_MUX_OUT_ALT6 (0x7 << IOMUXC_MUX_OUT_POS)
159
160 #define IOMUXC_MUX_IN_NONE (0x0 << IOMUXC_MUX_IN_POS)
161 #define IOMUXC_MUX_IN_GPIO (0x1 << IOMUXC_MUX_IN_POS)
162 #define IOMUXC_MUX_IN_FUNCTIONAL (0x2 << IOMUXC_MUX_IN_POS)
163 #define IOMUXC_MUX_IN_ALT1 (0x4 << IOMUXC_MUX_IN_POS)
164 #define IOMUXC_MUX_IN_ALT2 (0x8 << IOMUXC_MUX_IN_POS)
165
166 /* SW_PAD_CTL_* */
167 #define IOMUXC_PAD_LOOPBACK (0x1 << 9) /* Route output to input */
168 /* Pullup, pulldown and keeper enable */
169 #define IOMUXC_PAD_PUE_PKE (0x3 << 7)
170 #define IOMUXC_PAD_PUE_PKE_DISABLE (0x0 << 7)
171 #define IOMUXC_PAD_PUE_PKE_DISABLE_2 (0x1 << 7) /* Same as 0x0 */
172 #define IOMUXC_PAD_PUE_PKE_KEEPER (0x2 << 7)
173 #define IOMUXC_PAD_PUE_PKE_PULLUPDOWN (0x3 << 7) /* Enb. Pull up or down */
174 /* Pullup/down resistance */
175 #define IOMUXC_PAD_PUS (0x3 << 5)
176 #define IOMUXC_PAD_PUS_DOWN_100K (0x0 << 5)
177 #define IOMUXC_PAD_PUS_UP_100K (0x1 << 5)
178 #if 0 /* Completeness */
179 #define IOMUXC_PAD_PUS_UP_47K (0x2 << 5) /* Not in IMX31/L */
180 #define IOMUXC_PAD_PUS_UP_22K (0x3 << 5) /* Not in IMX31/L */
181 #endif
182 #define IOMUXC_PAD_HYS (0x1 << 4) /* Schmitt trigger input */
183 #define IOMUXC_PAD_ODE (0x1 << 3) /* Open drain output 0=CMOS pushpull*/
184 #define IOMUXC_PAD_DSE (0x3 << 1)
185 #define IOMUXC_PAD_DSE_STD (0x0 << 1) /* Drive strength */
186 #define IOMUXC_PAD_DSE_HIGH (0x1 << 1)
187 #define IOMUXC_PAD_DSE_MAX (0x2 << 1)
188 #define IOMUXC_PAD_DSE_MAX_2 (0x3 << 1) /* Same as 0x2 */
189 #define IOMUXC_PAD_SRE (0x1 << 0) /* Slew rate, 1=fast */
190
191 #define IOMUXC_PAD_MASK (0x3ff)
192
193 /* RNGA */
194 #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00))
195
196 #define RNGA_CONTROL_SLEEP (1 << 4)
197
198 /* IPU */
199 #define IPU_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00))
200 #define IPU_CHA_BUF0_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04))
201 #define IPU_CHA_BUF1_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08))
202 #define IPU_CHA_DB_MODE_SEL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C))
203 #define IPU_CHA_CUR_BUF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10))
204 #define IPU_FS_PROC_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14))
205 #define IPU_FS_DISP_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18))
206 #define IPU_TASKS_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1C))
207 #define IPU_IMA_ADDR (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x20))
208 #define IPU_IMA_DATA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x24))
209 #define IPU_INT_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x28))
210 #define IPU_INT_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x2C))
211 #define IPU_INT_CTRL_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x30))
212 #define IPU_INT_CTRL_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x34))
213 #define IPU_INT_CTRL_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x38))
214 #define IPU_INT_STAT_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x3C))
215 #define IPU_INT_STAT_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x40))
216 #define IPU_INT_STAT_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x44))
217 #define IPU_INT_STAT_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x48))
218 #define IPU_INT_STAT_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x4C))
219 #define IPU_BRK_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x50))
220 #define IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54))
221 #define IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58))
222 #define IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60))
223 #define IPU_IDMAC_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA4))
224 #define IPU_IDMAC_CHA_EN (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA8))
225 #define IPU_IDMAC_CHA_PRI (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xAC))
226 #define IPU_IDMAC_CHA_BUSY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xB0))
227
228
229
230 /* ATA */
231 #define ATA_TIME_OFF (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00))
232 #define ATA_TIME_ON (*(REG8_PTR_T)(ATA_BASE_ADDR+0x01))
233 /* PIO */
234 #define ATA_TIME_1 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x02))
235 #define ATA_TIME_2W (*(REG8_PTR_T)(ATA_BASE_ADDR+0x03))
236 #define ATA_TIME_2R (*(REG8_PTR_T)(ATA_BASE_ADDR+0x04))
237 #define ATA_TIME_AX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x05))
238 #define ATA_TIME_PIO_RDX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x06))
239 #define ATA_TIME_4 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x07))
240 #define ATA_TIME_9 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x08))
241 /* MDMA */
242 #define ATA_TIME_M (*(REG8_PTR_T)(ATA_BASE_ADDR+0x09))
243 #define ATA_TIME_JN (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0A))
244 #define ATA_TIME_D (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0B))
245 #define ATA_TIME_K (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0C))
246 /* UDMA */
247 #define ATA_TIME_ACK (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0D))
248 #define ATA_TIME_ENV (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0E))
249 #define ATA_TIME_RPX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0F))
250 #define ATA_TIME_ZAH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x10))
251 #define ATA_TIME_MLIX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x11))
252 #define ATA_TIME_DVH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x12))
253 #define ATA_TIME_DZFS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x13))
254 #define ATA_TIME_DVS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x14))
255 #define ATA_TIME_CVH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x15))
256 #define ATA_TIME_SS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x16))
257 #define ATA_TIME_CYC (*(REG8_PTR_T)(ATA_BASE_ADDR+0x17))
258 /* */
259 #define ATA_FIFO_DATA_32 (*(REG32_PTR_T)(ATA_BASE_ADDR+0x18))
260 #define ATA_FIFO_DATA_16 (*(REG16_PTR_T)(ATA_BASE_ADDR+0x1c))
261 #define ATA_FIFO_FILL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x20))
262 /* Actually ATA_CONTROL but conflicts arise */
263 #define ATA_INTF_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x24))
264 #define ATA_INTERRUPT_PENDING (*(REG8_PTR_T)(ATA_BASE_ADDR+0x28))
265 #define ATA_INTERRUPT_ENABLE (*(REG8_PTR_T)(ATA_BASE_ADDR+0x2c))
266 #define ATA_INTERRUPT_CLEAR (*(REG8_PTR_T)(ATA_BASE_ADDR+0x30))
267 #define ATA_FIFO_ALARM (*(REG8_PTR_T)(ATA_BASE_ADDR+0x34))
268 #define ATA_DRIVE_DATA (*(REG16_PTR_T)(ATA_BASE_ADDR+0xA0))
269 #define ATA_DRIVE_FEATURES (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA4))
270 #define ATA_DRIVE_SECTOR_COUNT (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA8))
271 #define ATA_DRIVE_SECTOR_NUM (*(REG8_PTR_T)(ATA_BASE_ADDR+0xAC))
272 #define ATA_DRIVE_CYL_LOW (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB0))
273 #define ATA_DRIVE_CYL_HIGH (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB4))
274 #define ATA_DRIVE_CYL_HEAD (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB8))
275 #define ATA_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* rd */
276 #define ATA_DRIVE_COMMAND (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* wr */
277 #define ATA_ALT_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* rd */
278 #define ATA_DRIVE_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* wr */
279
280 /* ATA_INTF_CONTROL flags */
281 #define ATA_FIFO_RST (1 << 7)
282 #define ATA_ATA_RST (1 << 6)
283 #define ATA_FIFO_TX_EN (1 << 5)
284 #define ATA_FIFO_RCV_EN (1 << 4)
285 #define ATA_DMA_PENDING (1 << 3)
286 #define ATA_DMA_ULTRA_SELECTED (1 << 2)
287 #define ATA_DMA_WRITE (1 << 1)
288 #define ATA_IORDY_EN (1 << 0)
289
290 /* ATA_INTERRUPT_PENDING, ATA_INTERRUPT_ENABLE, ATA_INTERRUPT_CLEAR flags */
291 #define ATA_INTRQ1 (1 << 7) /* INTRQ to the DMA */
292 #define ATA_FIFO_UNDERFLOW (1 << 6)
293 #define ATA_FIFO_OVERFLOW (1 << 5)
294 #define ATA_CONTROLLER_IDLE (1 << 4)
295 #define ATA_INTRQ2 (1 << 3) /* INTRQ to the MCU */
296
297 /* EPIT */
298 #define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00))
299 #define EPITSR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x04))
300 #define EPITLR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x08))
301 #define EPITCMPR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x0C))
302 #define EPITCNT1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x10))
303
304 #define EPITCR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x00))
305 #define EPITSR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x04))
306 #define EPITLR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x08))
307 #define EPITCMPR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x0C))
308 #define EPITCNT2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x10))
309
310 #define EPITCR_CLKSRC_OFF (0 << 24)
311 #define EPITCR_CLKSRC_IPG_CLK (1 << 24)
312 #define EPITCR_CLKSRC_IPG_CLK_HIGHFREQ (2 << 24)
313 #define EPITCR_CLKSRC_IPG_CLK_32K (3 << 24)
314 #define EPITCR_OM_DISCONNECTED (0 << 22)
315 #define EPITCR_OM_TOGGLE (1 << 22)
316 #define EPITCR_OM_CLEAR (2 << 22)
317 #define EPITCR_OM_SET (3 << 22)
318 #define EPITCR_STOPEN (1 << 21)
319 #define EPITCR_DOZEN (1 << 20)
320 #define EPITCR_WAITEN (1 << 19)
321 #define EPITCR_DBGEN (1 << 18)
322 #define EPITCR_IOVW (1 << 17)
323 #define EPITCR_SWR (1 << 16)
324 #define EPITCR_PRESCALER (0xfff << 4) /* Divide by n+1 */
325 #define EPITCR_PRESCALER_POS (4)
326 #define EPITCR_RLD (1 << 3)
327 #define EPITCR_OCIEN (1 << 2)
328 #define EPITCR_ENMOD (1 << 1)
329 #define EPITCR_EN (1 << 0)
330
331 #define EPITSR_OCIF (1 << 0)
332
333 /* GPT */
334 #define GPTCR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x00))
335 #define GPTPR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x04))
336 #define GPTSR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x08))
337 #define GPTIR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x0C))
338 #define GPTOCR1 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x10))
339 #define GPTOCR2 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x14))
340 #define GPTOCR3 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x18))
341 #define GPTICR1 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x1C))
342 #define GPTICR2 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x20))
343 #define GPTCNT (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x24))
344
345 /* GPTCR */
346 #define GPTCR_FO3 (0x1 << 31)
347 #define GPTCR_FO2 (0x1 << 30)
348 #define GPTCR_FO1 (0x1 << 29)
349
350 #define GPTCR_OM3 (0x7 << 26)
351 #define GPTCR_OM3_DISCONNECTED (0x0 << 26)
352 #define GPTCR_OM3_TOGGLE (0x1 << 26)
353 #define GPTCR_OM3_CLEAR (0x2 << 26)
354 #define GPTCR_OM3_SET (0x3 << 26)
355 #define GPTCR_OM3_SINGLE_COUNT (0x4 << 26)
356 /* 0x5-0x7 same as 0x4 */
357
358 #define GPTCR_OM2 (0x7 << 23)
359 #define GPTCR_OM2_DISCONNECTED (0x0 << 23)
360 #define GPTCR_OM2_TOGGLE (0x1 << 23)
361 #define GPTCR_OM2_CLEAR (0x2 << 23)
362 #define GPTCR_OM2_SET (0x3 << 23)
363 #define GPTCR_OM2_SINGLE_COUNT (0x4 << 23)
364
365 /* 0x5-0x7 same as 0x4 */
366 #define GPTCR_OM1 (0x7 << 20)
367 #define GPTCR_OM1_DISCONNECTED (0x0 << 20)
368 #define GPTCR_OM1_TOGGLE (0x1 << 20)
369 #define GPTCR_OM1_CLEAR (0x2 << 20)
370 #define GPTCR_OM1_SET (0x3 << 20)
371 #define GPTCR_OM1_SINGLE_COUNT (0x4 << 20)
372
373 /* 0x5-0x7 same as 0x4 */
374 #define GPTCR_IM2 (0x3 << 18)
375 #define GPTCR_IM2_DISABLED (0x0 << 18)
376 #define GPTCR_IM2_RISING (0x1 << 18)
377 #define GPTCR_IM2_FALLING (0x2 << 18)
378 #define GPTCR_IM2_BOTH (0x3 << 18)
379
380 #define GPTCR_IM1 (0x3 << 16)
381 #define GPTCR_IM1_DISABLED (0x0 << 16)
382 #define GPTCR_IM1_RISING (0x1 << 16)
383 #define GPTCR_IM1_FALLING (0x2 << 16)
384 #define GPTCR_IM1_BOTH (0x3 << 16)
385
386 #define GPTCR_SWR (0x1 << 15)
387 #define GPTCR_FRR (0x1 << 9)
388
389 #define GPTCR_CLKSRC (0x7 << 6)
390 #define GPTCR_CLKSRC_NONE (0x0 << 6)
391 #define GPTCR_CLKSRC_IPG_CLK (0x1 << 6)
392 #define GPTCR_CLKSRC_IPG_CLK_HIGHFREQ (0x2 << 6)
393 #define GPTCR_CLKSRC_IPG_CLK_32K (0x4 << 6)
394 /* Other values not defined */
395
396 #define GPTCR_STOPEN (0x1 << 5)
397 #define GPTCR_DOZEN (0x1 << 4)
398 #define GPTCR_WAITEN (0x1 << 3)
399 #define GPTCR_DBGEN (0x1 << 2)
400 #define GPTCR_ENMODE (0x1 << 1)
401 #define GPTCR_EN (0x1 << 0)
402
403 /* GPTSR */
404 #define GPTSR_ROV (0x1 << 5)
405 #define GPTSR_IF2 (0x1 << 4)
406 #define GPTSR_IF1 (0x1 << 3)
407 #define GPTSR_OF3 (0x1 << 2)
408 #define GPTSR_OF2 (0x1 << 1)
409 #define GPTSR_OF1 (0x1 << 0)
410
411 /* GPTIR */
412 #define GPTIR_ROV (0x1 << 5)
413 #define GPTIR_IF2IE (0x1 << 4)
414 #define GPTIR_IF1IE (0x1 << 3)
415 #define GPTIR_OF3IE (0x1 << 2)
416 #define GPTIR_OF2IE (0x1 << 1)
417 #define GPTIR_OF1IE (0x1 << 0)
418
419 /* GPIO */
420 #define GPIO1_DR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00))
421 #define GPIO1_GDIR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04))
422 #define GPIO1_PSR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x08))
423 #define GPIO1_ICR1 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x0C))
424 #define GPIO1_ICR2 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x10))
425 #define GPIO1_IMR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x14))
426 #define GPIO1_ISR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x18))
427
428 #define GPIO2_DR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x00))
429 #define GPIO2_GDIR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x04))
430 #define GPIO2_PSR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x08))
431 #define GPIO2_ICR1 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x0C))
432 #define GPIO2_ICR2 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x10))
433 #define GPIO2_IMR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x14))
434 #define GPIO2_ISR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x18))
435
436 #define GPIO3_DR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x00))
437 #define GPIO3_GDIR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x04))
438 #define GPIO3_PSR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x08))
439 #define GPIO3_ICR1 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x0C))
440 #define GPIO3_ICR2 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x10))
441 #define GPIO3_IMR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14))
442 #define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18))
443
444 /* CSPI */
445 #define CSPI_RXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00))
446 #define CSPI_TXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04))
447 #define CSPI_CONREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08))
448 #define CSPI_INTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x0C))
449 #define CSPI_DMAREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x10))
450 #define CSPI_STATREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x14))
451 #define CSPI_PERIODREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x18))
452 #define CSPI_TESTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x1C0))
453
454 #define CSPI_RXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x00))
455 #define CSPI_TXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x04))
456 #define CSPI_CONREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x08))
457 #define CSPI_INTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x0C))
458 #define CSPI_DMAREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x10))
459 #define CSPI_STATREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x14))
460 #define CSPI_PERIODREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18))
461 #define CSPI_TESTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0))
462
463 #define CSPI_RXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x00))
464 #define CSPI_TXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x04))
465 #define CSPI_CONREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x08))
466 #define CSPI_INTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x0C))
467 #define CSPI_DMAREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x10))
468 #define CSPI_STATREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x14))
469 #define CSPI_PERIODREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x18))
470 #define CSPI_TESTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x1C0))
471
472 /* CSPI CONREG flags/fields */
473 #define CSPI_CONREG_CHIP_SELECT_SS0 (0 << 24)
474 #define CSPI_CONREG_CHIP_SELECT_SS1 (1 << 24)
475 #define CSPI_CONREG_CHIP_SELECT_SS2 (2 << 24)
476 #define CSPI_CONREG_CHIP_SELECT_SS3 (3 << 24)
477 #define CSPI_CONREG_CHIP_SELECT_MASK (3 << 24)
478 #define CSPI_CONREG_DRCTL_DONT_CARE (0 << 20)
479 #define CSPI_CONREG_DRCTL_TRIG_FALLING (1 << 20)
480 #define CSPI_CONREG_DRCTL_TRIG_LOW (2 << 20)
481 #define CSPI_CONREG_DRCTL_TRIG_RSV (3 << 20)
482 #define CSPI_CONREG_DRCTL_MASK (3 << 20)
483 #define CSPI_CONREG_DATA_RATE_DIV_4 (0 << 16)
484 #define CSPI_CONREG_DATA_RATE_DIV_8 (1 << 16)
485 #define CSPI_CONREG_DATA_RATE_DIV_16 (2 << 16)
486 #define CSPI_CONREG_DATA_RATE_DIV_32 (3 << 16)
487 #define CSPI_CONREG_DATA_RATE_DIV_64 (4 << 16)
488 #define CSPI_CONREG_DATA_RATE_DIV_128 (5 << 16)
489 #define CSPI_CONREG_DATA_RATE_DIV_256 (6 << 16)
490 #define CSPI_CONREG_DATA_RATE_DIV_512 (7 << 16)
491 #define CSPI_CONREG_DATA_RATE_DIV_MASK (7 << 16)
492 #define CSPI_BITCOUNT(n) ((n) << 8)
493 #define CSPI_CONREG_SSPOL (1 << 7)
494 #define CSPI_CONREG_SSCTL (1 << 6)
495 #define CSPI_CONREG_PHA (1 << 6)
496 #define CSPI_CONREG_POL (1 << 4)
497 #define CSPI_CONREG_SMC (1 << 3)
498 #define CSPI_CONREG_XCH (1 << 2)
499 #define CSPI_CONREG_MODE (1 << 1)
500 #define CSPI_CONREG_EN (1 << 0)
501
502 /* CSPI INTREG flags */
503 #define CSPI_INTREG_TCEN (1 << 8)
504 #define CSPI_INTREG_BOEN (1 << 7)
505 #define CSPI_INTREG_ROEN (1 << 6)
506 #define CSPI_INTREG_RFEN (1 << 5)
507 #define CSPI_INTREG_RHEN (1 << 4)
508 #define CSPI_INTREG_RREN (1 << 3)
509 #define CSPI_INTREG_TFEN (1 << 2)
510 #define CSPI_INTREG_THEN (1 << 1)
511 #define CSPI_INTREG_TEEN (1 << 0)
512
513 /* CSPI DMAREG flags */
514 #define CSPI_DMAREG_RFDEN (1 << 5)
515 #define CSPI_DMAREG_RHDEN (1 << 4)
516 #define CSPI_DMAREG_THDEN (1 << 1)
517 #define CSPI_DMAREG_TEDEN (1 << 0)
518
519 /* CSPI STATREG flags */
520 #define CSPI_STATREG_TC (1 << 8) /* w1c */
521 #define CSPI_STATREG_BO (1 << 7) /* w1c */
522 #define CSPI_STATREG_RO (1 << 6)
523 #define CSPI_STATREG_RF (1 << 5)
524 #define CSPI_STATREG_RH (1 << 4)
525 #define CSPI_STATREG_RR (1 << 3)
526 #define CSPI_STATREG_TF (1 << 2)
527 #define CSPI_STATREG_TH (1 << 1)
528 #define CSPI_STATREG_TE (1 << 0)
529
530 /* CSPI PERIODREG flags */
531 #define CSPI_PERIODREG_CSRC (1 << 15)
532
533 /* CSPI TESTREG flags */
534 #define CSPI_TESTREG_SWAP (1 << 15)
535 #define CSPI_TESTREG_LBC (1 << 14)
536
537 /* I2C */
538 #define I2C_IADR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x0))
539 #define I2C_IFDR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x4))
540 #define I2C_I2CR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x8))
541 #define I2C_I2SR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0xC))
542 #define I2C_I2DR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x10))
543
544 #define I2C_IADR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x0))
545 #define I2C_IFDR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x4))
546 #define I2C_I2CR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x8))
547 #define I2C_I2SR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0xC))
548 #define I2C_I2DR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x10))
549
550 #define I2C_IADR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x0))
551 #define I2C_IFDR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x4))
552 #define I2C_I2CR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x8))
553 #define I2C_I2SR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0xC))
554 #define I2C_I2DR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x10))
555
556 /* IADR - [7:1] Address */
557
558 /* IFDR */
559 #define I2C_IFDR_DIV30 0x00
560 #define I2C_IFDR_DIV32 0x01
561 #define I2C_IFDR_DIV36 0x02
562 #define I2C_IFDR_DIV42 0x03
563 #define I2C_IFDR_DIV48 0x04
564 #define I2C_IFDR_DIV52 0x05
565 #define I2C_IFDR_DIV60 0x06
566 #define I2C_IFDR_DIV72 0x07
567 #define I2C_IFDR_DIV80 0x08
568 #define I2C_IFDR_DIV88 0x09
569 #define I2C_IFDR_DIV104 0x0a
570 #define I2C_IFDR_DIV128 0x0b
571 #define I2C_IFDR_DIV144 0x0c
572 #define I2C_IFDR_DIV160 0x0d
573 #define I2C_IFDR_DIV192 0x0e
574 #define I2C_IFDR_DIV240 0x0f
575 #define I2C_IFDR_DIV288 0x10
576 #define I2C_IFDR_DIV320 0x11
577 #define I2C_IFDR_DIV384 0x12
578 #define I2C_IFDR_DIV480 0x13
579 #define I2C_IFDR_DIV576 0x14
580 #define I2C_IFDR_DIV640 0x15
581 #define I2C_IFDR_DIV768 0x16
582 #define I2C_IFDR_DIV960 0x17
583 #define I2C_IFDR_DIV1152 0x18
584 #define I2C_IFDR_DIV1280 0x19
585 #define I2C_IFDR_DIV1536 0x1a
586 #define I2C_IFDR_DIV1920 0x1b
587 #define I2C_IFDR_DIV2304 0x1c
588 #define I2C_IFDR_DIV2560 0x1d
589 #define I2C_IFDR_DIV3072 0x1e
590 #define I2C_IFDR_DIV3840 0x1f
591 #define I2C_IFDR_DIV22 0x20
592 #define I2C_IFDR_DIV24 0x21
593 #define I2C_IFDR_DIV26 0x22
594 #define I2C_IFDR_DIV28 0x23
595 #define I2C_IFDR_DIV32_2 0x24
596 #define I2C_IFDR_DIV36_2 0x25
597 #define I2C_IFDR_DIV40 0x26
598 #define I2C_IFDR_DIV44 0x27
599 #define I2C_IFDR_DIV48_2 0x28
600 #define I2C_IFDR_DIV56 0x29
601 #define I2C_IFDR_DIV64 0x2a
602 #define I2C_IFDR_DIV72_2 0x2b
603 #define I2C_IFDR_DIV80_2 0x2c
604 #define I2C_IFDR_DIV96 0x2d
605 #define I2C_IFDR_DIV112 0x2e
606 #define I2C_IFDR_DIV128_2 0x2f
607 #define I2C_IFDR_DIV160_2 0x30
608 #define I2C_IFDR_DIV192_2 0x31
609 #define I2C_IFDR_DIV224 0x32
610 #define I2C_IFDR_DIV256 0x33
611 #define I2C_IFDR_DIV320_2 0x34
612 #define I2C_IFDR_DIV384_2 0x35
613 #define I2C_IFDR_DIV448 0x36
614 #define I2C_IFDR_DIV512 0x37
615 #define I2C_IFDR_DIV640_2 0x38
616 #define I2C_IFDR_DIV768_2 0x39
617 #define I2C_IFDR_DIV896 0x3a
618 #define I2C_IFDR_DIV1024 0x3b
619 #define I2C_IFDR_DIV1280_2 0x3c
620 #define I2C_IFDR_DIV1536_2 0x3d
621 #define I2C_IFDR_DIV1792 0x3e
622 #define I2C_IFDR_DIV2048 0x3f
623
624 /* I2CR */
625 #define I2C_I2CR_IEN (1 << 7)
626 #define I2C_I2CR_IIEN (1 << 6)
627 #define I2C_I2CR_MSTA (1 << 5)
628 #define I2C_I2CR_MTX (1 << 4)
629 #define I2C_I2CR_TXAK (1 << 3)
630 #define I2C_I2CR_RSATA (1 << 2)
631
632 /* I2SR */
633 #define I2C_I2SR_ICF (1 << 7)
634 #define I2C_I2SR_IAAS (1 << 6)
635 #define I2C_I2SR_IBB (1 << 5)
636 #define I2C_I2SR_IAL (1 << 4)
637 #define I2C_I2SR_SRW (1 << 2)
638 #define I2C_I2SR_IIF (1 << 1)
639 #define I2C_I2SR_RXAK (1 << 0)
640
641 /* I2DR - [7:0] Data */
642
643 /* AUDMUX */
644 #define AUDMUX_PTCR1 (*(REG32_PTR_T)(AUDMUX_BASE+0x00))
645 #define AUDMUX_PDCR1 (*(REG32_PTR_T)(AUDMUX_BASE+0x04))
646 #define AUDMUX_PTCR2 (*(REG32_PTR_T)(AUDMUX_BASE+0x08))
647 #define AUDMUX_PDCR2 (*(REG32_PTR_T)(AUDMUX_BASE+0x0C))
648 #define AUDMUX_PTCR3 (*(REG32_PTR_T)(AUDMUX_BASE+0x10))
649 #define AUDMUX_PDCR3 (*(REG32_PTR_T)(AUDMUX_BASE+0x14))
650 #define AUDMUX_PTCR4 (*(REG32_PTR_T)(AUDMUX_BASE+0x18))
651 #define AUDMUX_PDCR4 (*(REG32_PTR_T)(AUDMUX_BASE+0x1C))
652 #define AUDMUX_PTCR5 (*(REG32_PTR_T)(AUDMUX_BASE+0x20))
653 #define AUDMUX_PDCR5 (*(REG32_PTR_T)(AUDMUX_BASE+0x24))
654 #define AUDMUX_PTCR6 (*(REG32_PTR_T)(AUDMUX_BASE+0x28))
655 #define AUDMUX_PDCR6 (*(REG32_PTR_T)(AUDMUX_BASE+0x2C))
656 #define AUDMUX_PTCR7 (*(REG32_PTR_T)(AUDMUX_BASE+0x30))
657 #define AUDMUX_PDCR7 (*(REG32_PTR_T)(AUDMUX_BASE+0x34))
658 #define AUDMUX_CNMCR (*(REG32_PTR_T)(AUDMUX_BASE+0x38))
659
660 #define AUDMUX_PTCR_TFS_DIR (1 << 31)
661
662 #define AUDMUX_PTCR_TFSEL (0xf << 27)
663 #define AUDMUX_PTCR_TFSEL_TXFS (0x0 << 27)
664 #define AUDMUX_PTCR_TFSEL_RXFS (0x8 << 27)
665 #define AUDMUX_PTCR_TFSEL_PORT1 (0x0 << 27)
666 #define AUDMUX_PTCR_TFSEL_PORT2 (0x1 << 27)
667 #define AUDMUX_PTCR_TFSEL_PORT3 (0x2 << 27)
668 #define AUDMUX_PTCR_TFSEL_PORT4 (0x3 << 27)
669 #define AUDMUX_PTCR_TFSEL_PORT5 (0x4 << 27)
670 #define AUDMUX_PTCR_TFSEL_PORT6 (0x5 << 27)
671 #define AUDMUX_PTCR_TFSEL_PORT7 (0x6 << 27)
672
673 #define AUDMUX_PTCR_TCLKDIR (1 << 26)
674
675 #define AUDMUX_PTCR_TCSEL (0xf << 22)
676 #define AUDMUX_PTCR_TCSEL_TXFS (0x0 << 22)
677 #define AUDMUX_PTCR_TCSEL_RXFS (0x8 << 22)
678 #define AUDMUX_PTCR_TCSEL_PORT1 (0x0 << 22)
679 #define AUDMUX_PTCR_TCSEL_PORT2 (0x1 << 22)
680 #define AUDMUX_PTCR_TCSEL_PORT3 (0x2 << 22)
681 #define AUDMUX_PTCR_TCSEL_PORT4 (0x3 << 22)
682 #define AUDMUX_PTCR_TCSEL_PORT5 (0x4 << 22)
683 #define AUDMUX_PTCR_TCSEL_PORT6 (0x5 << 22)
684 #define AUDMUX_PTCR_TCSEL_PORT7 (0x6 << 22)
685
686 #define AUDMUX_PTCR_RFS_DIR (1 << 21)
687
688 #define AUDMUX_PTCR_RFSSEL (0xf << 17)
689 #define AUDMUX_PTCR_RFSSEL_TXFS (0x0 << 17)
690 #define AUDMUX_PTCR_RFSSEL_RXFS (0x8 << 17)
691 #define AUDMUX_PTCR_RFSSEL_PORT1 (0x0 << 17)
692 #define AUDMUX_PTCR_RFSSEL_PORT2 (0x1 << 17)
693 #define AUDMUX_PTCR_RFSSEL_PORT3 (0x2 << 17)
694 #define AUDMUX_PTCR_RFSSEL_PORT4 (0x3 << 17)
695 #define AUDMUX_PTCR_RFSSEL_PORT5 (0x4 << 17)
696 #define AUDMUX_PTCR_RFSSEL_PORT6 (0x5 << 17)
697 #define AUDMUX_PTCR_RFSSEL_PORT7 (0x6 << 17)
698
699 #define AUDMUX_PTCR_RCLKDIR (1 << 16)
700
701 #define AUDMUX_PTCR_RCSEL (0xf << 12)
702 #define AUDMUX_PTCR_RCSEL_TXFS (0x0 << 12)
703 #define AUDMUX_PTCR_RCSEL_RXFS (0x8 << 12)
704 #define AUDMUX_PTCR_RCSEL_PORT1 (0x0 << 12)
705 #define AUDMUX_PTCR_RCSEL_PORT2 (0x1 << 12)
706 #define AUDMUX_PTCR_RCSEL_PORT3 (0x2 << 12)
707 #define AUDMUX_PTCR_RCSEL_PORT4 (0x3 << 12)
708 #define AUDMUX_PTCR_RCSEL_PORT5 (0x4 << 12)
709 #define AUDMUX_PTCR_RCSEL_PORT6 (0x5 << 12)
710 #define AUDMUX_PTCR_RCSEL_PORT7 (0x6 << 12)
711 #define AUDMUX_PTCR_SYN (1 << 11)
712
713 #define AUDMUX_PDCR_RXDSEL (0x7 << 13)
714 #define AUDMUX_PDCR_RXDSEL_PORT1 (0 << 13)
715 #define AUDMUX_PDCR_RXDSEL_PORT2 (1 << 13)
716 #define AUDMUX_PDCR_RXDSEL_PORT3 (2 << 13)
717 #define AUDMUX_PDCR_RXDSEL_PORT4 (3 << 13)
718 #define AUDMUX_PDCR_RXDSEL_PORT5 (4 << 13)
719 #define AUDMUX_PDCR_RXDSEL_PORT6 (5 << 13)
720 #define AUDMUX_PDCR_RXDSEL_PORT7 (6 << 13)
721 #define AUDMUX_PDCR_TXRXEN (1 << 12)
722
723 #define AUDMUX_CNMCR_BEN (1 << 18)
724 #define AUDMUX_CNMCR_FSPOL (1 << 17)
725 #define AUDMUX_CNMCR_CLKPOL (1 << 16)
726
727 #define AUDMUX_CNMCR_CNTHI (0xff << 8)
728 #define AUDMUX_CNMCR_CNTHI_POS (8)
729
730 #define AUDMUX_CNMCR_CNTLOW (0xff << 0)
731 #define AUDMUX_CNMCR_CNTLOW_POS (0)
732
733 /* SSI */
734 #define SSI_STX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x00))
735 #define SSI_STX1_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x04))
736 #define SSI_SRX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x08))
737 #define SSI_SRX1_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x0C))
738 #define SSI_SCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x10))
739 #define SSI_SISR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x14))
740 #define SSI_SIER1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x18))
741 #define SSI_STCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x1C))
742 #define SSI_SRCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x20))
743 #define SSI_STCCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x24))
744 #define SSI_SRCCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x28))
745 #define SSI_SFCSR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x2C))
746 #define SSI_SACNT1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x38))
747 #define SSI_SACADD1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x3C))
748 #define SSI_SACDAT1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x40))
749 #define SSI_SATAG1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x44))
750 #define SSI_STMSK1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x48))
751 #define SSI_SRMSK1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x4C))
752
753 #define SSI_STX0_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x00))
754 #define SSI_STX1_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x04))
755 #define SSI_SRX0_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x08))
756 #define SSI_SRX1_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x0C))
757 #define SSI_SCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x10))
758 #define SSI_SISR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x14))
759 #define SSI_SIER2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x18))
760 #define SSI_STCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x1C))
761 #define SSI_SRCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x20))
762 #define SSI_STCCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x24))
763 #define SSI_SRCCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x28))
764 #define SSI_SFCSR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x2C))
765 #define SSI_SACNT2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x38))
766 #define SSI_SACADD2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x3C))
767 #define SSI_SACDAT2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x40))
768 #define SSI_SATAG2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x44))
769 #define SSI_STMSK2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x48))
770 #define SSI_SRMSK2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x4C))
771
772 /* SSI SCR */
773 #define SSI_SCR_CLK_IST (0x1 << 9)
774 #define SSI_SCR_TCHN_EN (0x1 << 8)
775 #define SSI_SCR_SYS_CLK_EN (0x1 << 7)
776
777 #define SSI_SCR_I2S_MODE (0x3 << 5)
778 #define SSI_SCR_I2S_MODE_NORMAL (0x0 << 5)
779 #define SSI_SCR_I2S_MODE_MASTER (0x1 << 5)
780 #define SSI_SCR_I2S_MODE_SLAVE (0x2 << 5)
781 #define SSI_SCR_I2S_MODE_NOR2 (0x3 << 5)
782
783 #define SSI_SCR_SYN (0x1 << 4)
784 #define SSI_SCR_NET (0x1 << 3)
785 #define SSI_SCR_RE (0x1 << 2)
786 #define SSI_SCR_TE (0x1 << 1)
787 #define SSI_SCR_SSIEN (0x1 << 0)
788
789 /* SSI SISR */
790 #define SSI_SISR_CMDAU (0x1 << 18)
791 #define SSI_SISR_CMDDU (0x1 << 17)
792 #define SSI_SISR_RXT (0x1 << 16)
793 #define SSI_SISR_RDR1 (0x1 << 15)
794 #define SSI_SISR_RDR0 (0x1 << 14)
795 #define SSI_SISR_TDE1 (0x1 << 13)
796 #define SSI_SISR_TDE0 (0x1 << 12)
797 #define SSI_SISR_ROE1 (0x1 << 11)
798 #define SSI_SISR_ROE0 (0x1 << 10)
799 #define SSI_SISR_TUE1 (0x1 << 9)
800 #define SSI_SISR_TUE0 (0x1 << 8)
801 #define SSI_SISR_TFS (0x1 << 7)
802 #define SSI_SISR_RFS (0x1 << 6)
803 #define SSI_SISR_TLS (0x1 << 5)
804 #define SSI_SISR_RLS (0x1 << 4)
805 #define SSI_SISR_RFF1 (0x1 << 3)
806 #define SSI_SISR_RFF2 (0x1 << 2)
807 #define SSI_SISR_TFE1 (0x1 << 1)
808 #define SSI_SISR_TFE0 (0x1 << 0)
809
810 /* SSI SIER */
811 #define SSI_SIER_RDMAE (0x1 << 22)
812 #define SSI_SIER_RIE (0x1 << 21)
813 #define SSI_SIER_TDMAE (0x1 << 20)
814 #define SSI_SIER_TIE (0x1 << 19)
815 #define SSI_SIER_CMDAU (0x1 << 18)
816 #define SSI_SIER_CMDDU (0x1 << 17)
817 #define SSI_SIER_RXT (0x1 << 16)
818 #define SSI_SIER_RDR1 (0x1 << 15)
819 #define SSI_SIER_RDR0 (0x1 << 14)
820 #define SSI_SIER_TDE1 (0x1 << 13)
821 #define SSI_SIER_TDE0 (0x1 << 12)
822 #define SSI_SIER_ROE1 (0x1 << 11)
823 #define SSI_SIER_ROE0 (0x1 << 10)
824 #define SSI_SIER_TUE1 (0x1 << 9)
825 #define SSI_SIER_TUE0 (0x1 << 8)
826 #define SSI_SIER_TFS (0x1 << 7)
827 #define SSI_SIER_RFS (0x1 << 6)
828 #define SSI_SIER_TLS (0x1 << 5)
829 #define SSI_SIER_RLS (0x1 << 4)
830 #define SSI_SIER_RFF1 (0x1 << 3)
831 #define SSI_SIER_RFF0 (0x1 << 2)
832 #define SSI_SIER_TFE1 (0x1 << 1)
833 #define SSI_SIER_TFE0 (0x1 << 0)
834
835 /* SSI STCR */
836 #define SSI_STCR_TXBIT0 (0x1 << 9)
837 #define SSI_STCR_TFEN1 (0x1 << 8)
838 #define SSI_STCR_TFEN0 (0x1 << 7)
839 #define SSI_STCR_TFDIR (0x1 << 6)
840 #define SSI_STCR_TXDIR (0x1 << 5)
841 #define SSI_STCR_TSHFD (0x1 << 4)
842 #define SSI_STCR_TSCKP (0x1 << 3)
843 #define SSI_STCR_TFSI (0x1 << 2)
844 #define SSI_STCR_TFSL (0x1 << 1)
845 #define SSI_STCR_TEFS (0x1 << 0)
846
847 /* SSI SRCR */
848 #define SSI_SRCR_RXEXT (0x1 << 10)
849 #define SSI_SRCR_RXBIT0 (0x1 << 9)
850 #define SSI_SRCR_RFEN1 (0x1 << 8)
851 #define SSI_SRCR_RFEN0 (0x1 << 7)
852 #define SSI_SRCR_RFDIR (0x1 << 6)
853 #define SSI_SRCR_RXDIR (0x1 << 5)
854 #define SSI_SRCR_RSHFD (0x1 << 4)
855 #define SSI_SRCR_RSCKP (0x1 << 3)
856 #define SSI_SRCR_RFSI (0x1 << 2)
857 #define SSI_SRCR_RFSL (0x1 << 1)
858 #define SSI_SRCR_REFS (0x1 << 0)
859
860 /* SSI STCCR/SRCCR */
861 #define SSI_STRCCR_DIV2 (0x1 << 18)
862 #define SSI_STRCCR_PSR (0x1 << 17)
863
864 #define SSI_STRCCR_WL (0xf << 13)
865 #define SSI_STRCCR_WL8 (0x3 << 13)
866 #define SSI_STRCCR_WL10 (0x4 << 13)
867 #define SSI_STRCCR_WL12 (0x5 << 13)
868 #define SSI_STRCCR_WL16 (0x7 << 13)
869 #define SSI_STRCCR_WL18 (0x8 << 13)
870 #define SSI_STRCCR_WL20 (0x9 << 13)
871 #define SSI_STRCCR_WL22 (0xa << 13)
872 #define SSI_STRCCR_WL24 (0xb << 13)
873
874 #define SSI_STRCCR_DC (0x1f << 8)
875 #define SSI_STRCCR_DC_POS (8)
876
877 #define SSI_STRCCR_PM (0xf << 0)
878 #define SSI_STRCCR_PM_POS (0)
879
880 /* SSI SFCSR */
881 #define SSI_SFCSR_RFCNT1 (0xf << 28)
882 #define SSI_SFCSR_RFCNT1_POS (28)
883
884 #define SSI_SFCSR_TFCNT1 (0xf << 24)
885 #define SSI_SFCSR_TFCNN1_POS (24)
886
887 #define SSI_SFCSR_RFWM1 (0xf << 20)
888 #define SSI_SFCSR_RFWM1_POS (20)
889
890 #define SSI_SFCSR_TFWM1 (0xf << 16)
891 #define SSI_SFCSR_TFWM1_POS (16)
892
893 #define SSI_SFCSR_RFCNT0 (0xf << 12)
894 #define SSI_SFCSR_RFCNT0_POS (12)
895
896 #define SSI_SFCSR_TFCNT0 (0xf << 8)
897 #define SSI_SFCSR_TFCNT0_POS (8)
898
899 #define SSI_SFCSR_RFWM0 (0xf << 4)
900 #define SSI_SFCSR_RFWM0_POS (4)
901
902 #define SSI_SFCSR_TFWM0 (0xf << 0)
903 #define SSI_SFCSR_TFWM0_POS (0)
904
905 /* SACNT */
906 #define SSI_SACNT_FRDIV (0x3f << 5)
907 #define SSI_SACNT_FRDIV_POS (5)
908
909 #define SSI_SACNT_WR (0x1 << 4)
910 #define SSI_SACNT_RD (0x1 << 3)
911 #define SSI_SACNT_TIF (0x1 << 2)
912 #define SSI_SACNT_FV (0x1 << 1)
913 #define SSI_SACNT_AC97EN (0x1 << 0)
914
915 /* RTC */
916 #define RTC_HOURMIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00))
917 #define RTC_SECONDS (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04))
918 #define RTC_ALRM_HM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08))
919 #define RTC_ALRM_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C))
920 #define RTC_CTL (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10))
921 #define RTC_ISR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14))
922 #define RTC_IENR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18))
923 #define RTC_STPWCH (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C))
924 #define RTC_DAYR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20))
925 #define RTC_DAYALARM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24))
926
927 /* Watchdog */
928 #define WDOG_WCR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x00))
929 #define WDOG_WSR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x02))
930 #define WDOG_WRSR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x04))
931
932 #define WDOG_WCR_WT (0xff << 8)
933 #define WDOG_WCR_WT_POS (8)
934
935 #define WDOG_WCR_WOE (0x1 << 6)
936 #define WDOG_WCR_WDA (0x1 << 5)
937 #define WDOG_WCR_SRS (0x1 << 4)
938 #define WDOG_WCR_WRE (0x1 << 3)
939 #define WDOG_WCR_WDE (0x1 << 2)
940 #define WDOG_WCR_WDBG (0x1 << 1)
941 #define WDOG_WCR_WDZST (0x1 << 0)
942
943 #define WDOG_WRSR_JRST (0x1 << 5)
944 #define WDOG_WRSR_PWR (0x1 << 4)
945 #define WDOG_WRSR_EXT (0x1 << 3)
946 #define WDOG_WRSR_CMON (0x1 << 2)
947 #define WDOG_WRSR_TOUT (0x1 << 1)
948 #define WDOG_WRSR_SFTW (0x1 << 0)
949
950 /* Keypad */
951 #define KPP_KPCR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x0))
952 #define KPP_KPSR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x2))
953 #define KPP_KDDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4))
954 #define KPP_KPDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6))
955
956 /* KPP_KPSR bits */
957 #define KPP_KPSR_KRIE (1 << 9)
958 #define KPP_KPSR_KDIE (1 << 8)
959 #define KPP_KPSR_KRSS (1 << 3)
960 #define KPP_KPSR_KDSC (1 << 2)
961 #define KPP_KPSR_KPKR (1 << 1)
962 #define KPP_KPSR_KPKD (1 << 0)
963
964 /* SDHC */
965 #define SDHC1_CLOCK_CONTROL (*(REG32_PTR_T)(MMC_SDHC1_BASE_ADDR+0x00))
966 #define SDHC2_CLOCK_CONTROL (*(REG32_PTR_T)(MMC_SDHC2_BASE_ADDR+0x00))
967
968 /* SDHC bits */
969 #define STOP_CLK (1 << 0)
970
971 /* ROMPATCH and AVIC */
972 #define ROMPATCH_BASE_ADDR 0x60000000
973
974 /* Since AVIC vector registers are NOT used, we reserve some for various
975 * purposes. Copied from Linux source code. */
976 #define CHIP_REV_1_0 0x10
977 #define CHIP_REV_2_0 0x20
978 #define SYSTEM_REV_ID_REG (AVIC_BASE_ADDR + AVIC_VEC_1)
979 #define SYSTEM_REV_ID_MAG 0xF00C
980
981 /*
982 * NAND, SDRAM, WEIM, M3IF, EMI controllers
983 */
984 #define EXT_MEM_CTRL_BASE 0xB8000000
985 #define NFC_BASE EXT_MEM_CTRL_BASE
986 #define ESDCTL_BASE 0xB8001000
987 #define WEIM_BASE_ADDR 0xB8002000
988 #define WEIM_CTRL_CS0 (WEIM_BASE_ADDR+0x00)
989 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR+0x10)
990 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR+0x20)
991 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR+0x30)
992 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR+0x40)
993 #define M3IF_BASE 0xB8003000
994 #define PCMCIA_CTL_BASE 0xB8004000
995
996 /*
997 * Memory regions and CS
998 */
999 #define IPU_MEM_BASE_ADDR 0x70000000
1000 #define CSD0_BASE_ADDR 0x80000000
1001 #define CSD1_BASE_ADDR 0x90000000
1002 #define CS0_BASE_ADDR 0xA0000000
1003 #define CS1_BASE_ADDR 0xA8000000
1004 #define CS2_BASE_ADDR 0xB0000000
1005 #define CS3_BASE_ADDR 0xB2000000
1006 #define CS4_BASE_ADDR 0xB4000000
1007 #define CS4_BASE_PSRAM 0xB5000000
1008 #define CS5_BASE_ADDR 0xB6000000
1009 #define PCMCIA_MEM_BASE_ADDR 0xC0000000
1010
1011 #define INTERNAL_ROM_VA 0xF0000000
1012
1013 /*
1014 * SDRAM
1015 */
1016 #define RAM_BANK0_BASE SDRAM_BASE_ADDR
1017
1018 /*
1019 * IRQ Controller Register Definitions.
1020 */
1021 #define AVIC_BASE_ADDR 0x68000000
1022 #define AVIC_INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
1023 #define AVIC_NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
1024 #define AVIC_INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
1025 #define AVIC_INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
1026 #define AVIC_INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
1027 #define AVIC_INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
1028 #define AVIC_INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
1029 #define AVIC_INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
1030 #define AVIC_NIPRIORITY(n) (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n])
1031 #define AVIC_NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
1032 #define AVIC_NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
1033 #define AVIC_NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
1034 #define AVIC_NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
1035 #define AVIC_NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
1036 #define AVIC_NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
1037 #define AVIC_NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
1038 #define AVIC_NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
1039 #define AVIC_NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
1040 #define AVIC_FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
1041 #define AVIC_INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
1042 #define AVIC_INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
1043 #define AVIC_INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
1044 #define AVIC_INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
1045 #define AVIC_NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
1046 #define AVIC_NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
1047 #define AVIC_FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
1048 #define AVIC_FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
1049 #define AVIC_VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100)
1050 #define AVIC_VECTOR(n) (((REG32_PTR_T)VECTOR_BASE_ADDR)[n])
1051
1052 /* The vectors go all the way up to 63. 4 bytes for each */
1053 #define AVIC_INTCNTL_ABFLAG (1 << 25)
1054 #define AVIC_INTCNTL_ABFEN (1 << 24)
1055 #define AVIC_INTCNTL_NIDIS (1 << 22)
1056 #define AVIC_INTCNTL_FIDIS (1 << 21)
1057 #define AVIC_INTCNTL_NIAD (1 << 20)
1058 #define AVIC_INTCNTL_FIAD (1 << 19)
1059 #define AVIC_INTCNTL_NM (1 << 18)
1060
1061 /* L210 */
1062 #define L2CC_BASE_ADDR 0x30000000
1063 #define L2_CACHE_LINE_SIZE 32
1064 #define L2_CACHE_CTL_REG 0x100
1065 #define L2_CACHE_AUX_CTL_REG 0x104
1066 #define L2_CACHE_SYNC_REG 0x730
1067 #define L2_CACHE_INV_LINE_REG 0x770
1068 #define L2_CACHE_INV_WAY_REG 0x77C
1069 #define L2_CACHE_CLEAN_LINE_REG 0x7B0
1070 #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
1071
1072 #define L2CC_CACHE_SYNC (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG))
1073
1074 /* CCM */
1075 #define CCM_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
1076 #define CCM_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
1077 #define CCM_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
1078 #define CCM_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
1079 #define CCM_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
1080 #define CCM_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
1081 #define CCM_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
1082 #define CCM_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
1083 #define CCM_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
1084 #define CCM_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
1085 #define CCM_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
1086 #define CCM_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
1087 #define CCM_LDC (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30))
1088 #define CCM_DCVR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34))
1089 #define CCM_DCVR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38))
1090 #define CCM_DCVR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C))
1091 #define CCM_DCVR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40))
1092 #define CCM_LTR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44))
1093 #define CCM_LTR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48))
1094 #define CCM_LTR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C))
1095 #define CCM_LTR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50))
1096 #define CCM_LTBR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54))
1097 #define CCM_LTBR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58))
1098 #define CCM_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
1099 #define CCM_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60))
1100 #define CCM_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
1101
1102 /* CCMR */
1103 #define CCM_CCMR_L2PG (0x1 << 29)
1104 #define CCM_CCMR_VSTBY (0x1 << 28)
1105 #define CCM_CCMR_WBEN (0x1 << 27)
1106 #define CCM_CCMR_FPMF (0x1 << 26)
1107 #define CCM_CCMR_CSCS (0x1 << 25)
1108 #define CCM_CCMR_PERCS (0x1 << 24)
1109
1110 #define CCM_CCMR_SSI2S (0x3 << 21)
1111 #define CCM_CCMR_SSI2S_MCU_CLK (0x0 << 21)
1112 #define CCM_CCMR_SSI2S_USB_CLK (0x1 << 21)
1113 #define CCM_CCMR_SSI2S_SERIAL_CLK (0x2 << 21) /* default */
1114
1115 #define CCM_CCMR_SSI1S (0x3 << 18)
1116 #define CCM_CCMR_SSI1S_MCU_CLK (0x0 << 18)
1117 #define CCM_CCMR_SSI1S_USB_CLK (0x1 << 18)
1118 #define CCM_CCMR_SSI1S_SERIAL_CLK (0x2 << 18) /* default */
1119
1120 #define CCM_CCMR_RAMW (0x3 << 16)
1121 #define CCM_CCMR_RAMW_0ARM_0ALTMS (0x0 << 16)
1122 #define CCM_CCMR_RAMW_0ARM_1ALTMS (0x1 << 16) /* Not recommended */
1123 #define CCM_CCMR_RAMW_1ARM_0ALTMS (0x2 << 16) /* Not recommended */
1124 #define CCM_CCMR_RAMW_1ARM_1ALTMS (0x3 << 16)
1125
1126 #define CCM_CCMR_LPM (0x3 << 14)
1127 #define CCM_CCMR_LPM_WAIT_MODE (0x0 << 14)
1128 #define CCM_CCMR_LPM_DOZE_MODE (0x1 << 14)
1129 #define CCM_CCMR_LPM_SRM (0x2 << 14) /* State retention mode */
1130 #define CCM_CCMR_LPM_DSM (0x3 << 14) /* Deep sleep mode */
1131
1132 #define CCM_CCMR_FIRS (0x3 << 11)
1133 #define CCM_CCMR_FIRS_MCU_CLK (0x0 << 11)
1134 #define CCM_CCMR_FIRS_USB_CLK (0x1 << 11)
1135 #define CCM_CCMR_FIRS_SERIAL_CLK (0x2 << 11)
1136
1137 #define CCM_CCMR_WAMO (0x1 << 10)
1138 #define CCM_CCMR_UPE (0x1 << 9)
1139 #define CCM_CCMR_SPE (0x1 << 8)
1140 #define CCM_CCMR_MDS (0x1 << 7)
1141
1142 #define CCM_CCMR_ROMW (0x3 << 5)
1143 #define CCM_CCMR_ROMW_0ARM_0ALTMS (0x0 << 5)
1144 #define CCM_CCMR_ROMW_0ARM_1ALTMS (0x1 << 5) /* Not recommended */
1145 #define CCM_CCMR_ROMW_1ARM_0ALTMS (0x2 << 5) /* Not recommended */
1146 #define CCM_CCMR_ROMW_1ARM_1ALTMS (0x3 << 5)
1147
1148 #define CCM_CCMR_SBYCS (0x1 << 4)
1149 #define CCM_CCMR_MPE (0x1 << 3)
1150
1151 #define CCM_CCMR_PRCS (0x3 << 1)
1152 #define CCM_CCMR_PRCS_FPM (0x1 << 1)
1153 #define CCM_CCMR_PRCS_CKIH (0x2 << 1)
1154
1155 #define CCM_CCMR_FPME (0x1 << 0)
1156
1157 /* PDR0 */
1158 #define CCM_PDR0_CSI_PODF (0x1ff << 23)
1159 #define CCM_PDR0_CSI_PODF_POS (23)
1160
1161 #define CCM_PDR0_PER_PODF (0x1f << 16)
1162 #define CCM_PDR0_PER_PODF_POS (16)
1163
1164 #define CCM_PDR0_HSP_PODF (0x7 << 11)
1165 #define CCM_PDR0_HSP_PODF_POS (11)
1166
1167 #define CCM_PDR0_NFC_PODF (0x7 << 8)
1168 #define CCM_PDR0_NFC_PODF_POS (8)
1169
1170 #define CCM_PDR0_IPG_PODF (0x3 << 6)
1171 #define CCM_PDR0_IPG_PODF_POS (6)
1172
1173 #define CCM_PDR0_MAX_PODF (0x7 << 3)
1174 #define CCM_PDR0_MAX_PODF_POS (3)
1175
1176 #define CCM_PDR0_MCU_PODF (0x7 << 0)
1177 #define CCM_PDR0_MCU_PODF_POS (0)
1178
1179 /* PDR1 */
1180 #define CCM_PDR1_USB_PRDF (0x3 << 30)
1181 #define CCM_PDR1_USB_PRDF_POS (30)
1182
1183 #define CCM_PDR1_USB_PODF (0x7 << 27)
1184 #define CCM_PDR1_USB_PODF_POS (27)
1185
1186 #define CCM_PDR1_FIRI_PRE_PODF (0x7 << 24)
1187 #define CCM_PDR1_FIRI_PRE_PODF_POS (24)
1188
1189 #define CCM_PDR1_FIRI_PODF (0x3f << 18)
1190 #define CCM_PDR1_FIRI_PODF_POS (18)
1191
1192 #define CCM_PDR1_SSI2_PRE_PODF (0x7 << 15)
1193 #define CCM_PDR1_SSI2_PRE_PODF_POS (15)
1194
1195 #define CCM_PDR1_SSI2_PODF (0x3f << 9)
1196 #define CCM_PDR1_SSI2_PODF_POS (9)
1197
1198 #define CCM_PDR1_SSI1_PRE_PODF (0x7 << 6)
1199 #define CCM_PDR1_SSI1_PRE_PODF_POS (6)
1200
1201 #define CCM_PDR1_SSI1_PODF (0x3f << 0)
1202 #define CCM_PDR1_SSI1_PODF_POS (0)
1203
1204 /* RCSR */
1205 #define CCM_RCSR_NF16B (1 << 31)
1206
1207 #define CCM_RCSR_NFMS (1 << 30)
1208
1209 #define CCM_RCSR_BTP4 (1 << 27)
1210 #define CCM_RCSR_BTP3 (1 << 26)
1211 #define CCM_RCSR_BTP2 (1 << 25)
1212 #define CCM_RCSR_BTP1 (1 << 24)
1213 #define CCM_RCSR_BTP0 (1 << 23)
1214
1215 #define CCM_RCSR_OSCNT (0x7f << 16)
1216 #define CCM_RCSR_OSCNT_POS (16)
1217
1218 #define CCM_RCSR_PERES (1 << 15)
1219
1220 #define CCM_RCSR_SDM (0x3 << 12)
1221 #define CCM_RCSR_SDM_POS (12)
1222
1223 #define CCM_RCSR_GPF (0x7 << 5)
1224 #define CCM_RCSR_GPF_POS (5)
1225
1226 #define CCM_RCSR_WFIS (1 << 4)
1227
1228 #define CCM_RCSR_REST (0x7 << 0)
1229 #define CCM_RCSR_REST_POS (0)
1230 #define CCM_RCSR_REST_POR_EXT (0x0)
1231 #define CCM_RCSR_REST_QUALIFIED_EXT (0x1)
1232 #define CCM_RCSR_REST_WATCHDOG_TMO (0x2)
1233 /* 0x3 - 0x5: reserved */
1234 #define CCM_RCSR_REST_JTAG (0x6)
1235 #define CCM_RCSR_REST_ARM11P_GATING (0x7)
1236
1237 /* MPCTL */
1238 #define CCM_MPCTL_BRM (1 << 31)
1239 #define CCM_MPCTL_PD (0xf << 26)
1240 #define CCM_MPCTL_PD_POS (26)
1241 #define CCM_MPCTL_MFD (0x3ff << 16)
1242 #define CCM_MPCTL_MFD_POS (16)
1243 #define CCM_MPCTL_MFI (0xf << 10)
1244 #define CCM_MPCTL_MFI_POS (10)
1245 #define CCM_MPCTL_MFN (0x3ff << 0)
1246 #define CCM_MPCTL_MFN_POS (0)
1247
1248 /* UPCTL */
1249 #define CCM_UPCTL_BRM (1 << 31)
1250 #define CCM_UPCTL_PD (0xf << 26)
1251 #define CCM_UPCTL_PD_POS (26)
1252 #define CCM_UPCTL_MFD (0x3ff << 16)
1253 #define CCM_UPCTL_MFD_POS (16)
1254 #define CCM_UPCTL_MFI (0xf << 10)
1255 #define CCM_UPCTL_MFI_POS (10)
1256 #define CCM_UPCTL_MFN (0x3ff << 0)
1257 #define CCM_UPCTL_MFN_POS (0)
1258
1259 /* SPCTL */
1260 #define CCM_SPCTL_BRM (1 << 31)
1261 #define CCM_SPCTL_PD (0xf << 26)
1262 #define CCM_SPCTL_PD_POS (26)
1263 #define CCM_SPCTL_MFD (0x3ff << 16)
1264 #define CCM_SPCTL_MFD_POS (16)
1265 #define CCM_SPCTL_MFI (0xf << 10)
1266 #define CCM_SPCTL_MFI_POS (10)
1267 #define CCM_SPCTL_MFN (0x3ff << 0)
1268 #define CCM_SPCTL_MFN_POS (0)
1269
1270 /* COSR */
1271 #define CCM_COSR_CLKOEN (1 << 9)
1272 #define CCM_COSR_CLKOUTDIV (0x7 << 6)
1273 #define CCM_COSR_CLKOUTDIV_POS (6)
1274 #define CCM_COSR_CLKOSEL (0xf << 0)
1275 #define CCM_COSR_CLKOSEL_POS (0)
1276 #define CCM_COSR_CLKOSEL_MPL_DPDGCK_CLK (0x0)
1277 #define CCM_COSR_CLKOSEL_IPG_CLK_CCM (0x1)
1278 #define CCM_COSR_CLKOSEL_UPL_DPDGCK_CLK (0x2)
1279 #define CCM_COSR_CLKOSEL_PLL_REF_CLK (0x3)
1280 #define CCM_COSR_CLKOSEL_FPM_CKIL512_CLK (0x4)
1281 #define CCM_COSR_CLKOSEL_IPG_CLK_AHB_ARM (0x5)
1282 #define CCM_COSR_CLKOSEL_IPG_CLK_ARM (0x6)
1283 #define CCM_COSR_CLKOSEL_SPL_DPDGCK_CLK (0x7)
1284 #define CCM_COSR_CLKOSEL_CKIH (0x8)
1285 #define CCM_COSR_CLKOSEL_IPG_CLK_AHB_EMI_CLK (0x9)
1286 #define CCM_COSR_CLKOSEL_IPG_CLK_IPU_HSP (0x9)
1287 #define CCM_COSR_CLKOSEL_IPG_CLK_NFC_20M (0xa)
1288 #define CCM_COSR_CLKOSEL_IPG_CLK_PERCLK_UART1 (0xb)
1289 #define CCM_COSR_CLKOSEL_IPG_REF_CIR1 (0xc) /* ref_cir_gateload */
1290 #define CCM_COSR_CLKOSEL_IPG_REF_CIR2 (0xc) /* ref_cir_intrcload */
1291 #define CCM_COSR_CLKOSEL_IPG_REF_CIR3 (0xc) /* ref_cir_path */
1292
1293 /* CGR0 */
1294 /* CGR1 */
1295 /* CGR2 */
1296 /* Handled in ccm-imx31.h and ccm-imx31.c */
1297
1298
1299 #define CCM_WIMR0_GPIO3 (1 << 0)
1300 #define CCM_WIMR0_GPIO2 (1 << 1)
1301 #define CCM_WIMR0_GPIO1 (1 << 2)
1302 #define CCM_WIMR0_PCMCIA (1 << 3)
1303 #define CCM_WIMR0_WDT (1 << 4)
1304 #define CCM_WIMR0_USB_OTG (1 << 5)
1305 #define CCM_WIMR0_IPI_INT_UH2 (1 << 6)
1306 #define CCM_WIMR0_IPI_INT_UH1 (1 << 7)
1307 #define CCM_WIMR0_IPI_INT_UART5_ANDED (1 << 8)
1308 #define CCM_WIMR0_IPI_INT_UART4_ANDED (1 << 9)
1309 #define CCM_WIMR0_IPI_INT_UART3_ANDED (1 << 10)
1310 #define CCM_WIMR0_IPI_INT_UART2_ANDED (1 << 11)
1311 #define CCM_WIMR0_IPI_INT_UART1_ANDED (1 << 12)
1312 #define CCM_WIMR0_IPI_INT_SIM_DATA_IRQ (1 << 13)
1313 #define CCM_WIMR0_IPI_INT_SDHC2 (1 << 14)
1314 #define CCM_WIMR0_IPI_INT_SDHC1 (1 << 15)
1315 #define CCM_WIMR0_IPI_INT_RTC (1 << 16)
1316 #define CCM_WIMR0_IPI_INT_PWM (1 << 17)
1317 #define CCM_WIMR0_IPI_INT_KPP (1 << 18)
1318 #define CCM_WIMR0_IPI_INT_IIM (1 << 19)
1319 #define CCM_WIMR0_IPI_INT_GPT (1 << 20)
1320 #define CCM_WIMR0_IPI_INT_FIR (1 << 21)
1321 #define CCM_WIMR0_IPI_INT_EPIT2 (1 << 22)
1322 #define CCM_WIMR0_IPI_INT_EPIT1 (1 << 23)
1323 #define CCM_WIMR0_IPI_INT_CSPI2 (1 << 24)
1324 #define CCM_WIMR0_IPI_INT_CSPI1 (1 << 25)
1325 #define CCM_WIMR0_IPI_INT_POWER_FAIL (1 << 26)
1326 #define CCM_WIMR0_IPI_INT_CSPI3 (1 << 27)
1327 #define CCM_WIMR0_RESERVED28 (1 << 28)
1328 #define CCM_WIMR0_RESERVED29 (1 << 29)
1329 #define CCM_WIMR0_RESERVED30 (1 << 30)
1330 #define CCM_WIMR0_RESERVED31 (1 << 31)
1331
1332 /* LDC */
1333 /* 32 bits specify value */
1334
1335 /* DCVR0-DCVR3 */
1336 #define CCM_DCVR_ULV (0x3ff << 22) /* Upper limit */
1337 #define CCM_DCVR_ULV_POS (22)
1338 #define CCM_DCVR_LLV (0x3ff << 12) /* Lower limit */
1339 #define CCM_DCVR_LLV_POS (12)
1340 #define CCM_DCVR_ELV (0x3ff << 2) /* Emergency limit */
1341 #define CCM_DCVR_ELV_POS (2)
1342
1343
1344 /* LTR0 */
1345 #define CCM_LTR0_UPTHR (0x3f << 22)
1346 #define CCM_LTR0_UPTHR_POS (22)
1347 #define CCM_LTR0_DNTHR (0x3f << 16)
1348 #define CCM_LTR0_DNTHR_POS (16)
1349 /* for div_3_clk */
1350 #define CCM_LTR0_DIV3CK (0x3 << 1)
1351 #define CCM_LTR0_DIV3CK_POS (1)
1352 #define CCM_LTR0_DIV3CK_2048 (0x0 << 1) /* 1/2048 ARM clock */
1353 #define CCM_LTR0_DIV3CK_8192 (0x1 << 1) /* 1/8192 ARM clock */
1354 #define CCM_LTR0_DIV3CK_32768 (0x2 << 1) /* 1/32768 ARM clock */
1355 #define CCM_LTR0_DIV3CK_131072 (0x3 << 1) /* 1/131072 ARM clock */
1356
1357 /* LTR1 */
1358 #define CCM_LTR1_LTBRSH (1 << 23)
1359 #define CCM_LTR1_LTBRSR (1 << 22)
1360 #define CCM_LTR1_DNCNT (0xff << 14)
1361 #define CCM_LTR1_DNCNT_POS (14)
1362 #define CCM_LTR1_UPCNT (0xff << 6)
1363 #define CCM_LTR1_UPCNT_POS (6)
1364 #define CCM_LTR1_PNCTHR (0x3f << 0)
1365 #define CCM_LTR1_PNCTHR_POS (0)
1366
1367 /* LTR2 */
1368 #define CCM_LTR2_EMAC (0x1ff)
1369 #define CCM_LTR2_EMAC_POS (0)
1370
1371 /* PMCR0 */
1372 #define CCM_PMCR0_DFSUP_MCUPLL (1 << 31)
1373 #define CCM_PMCR0_DFSUP_MCUPLL_POS (31)
1374 #define CCM_PMCR0_DFSUP_POST_DIVIDERS (1 << 30)
1375 #define CCM_PMCR0_DVSUP (0x3 << 28)
1376 #define CCM_PMCR0_DVSUP_POS (28)
1377 #define CCM_PMCR0_UDSC (1 << 27)
1378 #define CCM_PMCR0_VSCNT (0x7 << 24)
1379 #define CCM_PMCR0_VSCNT_POS (24)
1380 #define CCM_PMCR0_DVFEV (1 << 23)
1381 #define CCM_PMCR0_DVFIS (1 << 22)
1382 #define CCM_PMCR0_LBMI (1 << 21)
1383 #define CCM_PMCR0_LBFL (1 << 20)
1384 #define CCM_PMCR0_LBCF (0x3 << 18)
1385 #define CCM_PMCR0_LBCF_4 (0x0 << 18)
1386 #define CCM_PMCR0_LBCF_8 (0x1 << 18)
1387 #define CCM_PMCR0_LBCF_12 (0x2 << 18)
1388 #define CCM_PMCR0_LBCF_16 (0x3 << 18)
1389 #define CCM_PMCR0_PTVIS (1 << 17)
1390 #define CCM_PMCR0_UPDTEN (1 << 16)
1391 #define CCM_PMCR0_FSVAIM (1 << 15)
1392 #define CCM_PMCR0_FSVAI (0x3 << 13)
1393 #define CCM_PMCR0_FSVAI_NO_INT (0x0 << 13)
1394 #define CCM_PMCR0_FSVAI_INCREASE (0x1 << 13)
1395 #define CCM_PMCR0_FSVAI_DECREASE (0x2 << 13)
1396 #define CCM_PMCR0_FSVAI_INCREASE_NOW (0x3 << 13)
1397 #define CCM_PMCR0_FSVAI_POS (13)
1398 #define CCM_PMCR0_DPVCR (1 << 12)
1399 #define CCM_PMCR0_DPVV (1 << 11)
1400 #define CCM_PMCR0_WFIM (1 << 10)
1401 #define CCM_PMCR0_DRCE3 (1 << 9)
1402 #define CCM_PMCR0_DRCE2 (1 << 8)
1403 #define CCM_PMCR0_DRCE1 (1 << 7)
1404 #define CCM_PMCR0_DRCE0 (1 << 6)
1405 #define CCM_PMCR0_DCR (1 << 5) /* 512 vs 256 count */
1406 #define CCM_PMCR0_DVFEN (1 << 4)
1407 #define CCM_PMCR0_PTVAIM (1 << 3)
1408 #define CCM_PMCR0_PTVAI (0x3 << 1)
1409 #define CCM_PMCR0_PTVAI_NO_INT (0x0 << 1)
1410 #define CCM_PMCR0_PTVAI_DECREASE (0x1 << 1)
1411 #define CCM_PMCR0_PTVAI_INCREASE (0x2 << 1)
1412 #define CCM_PMCR0_PTVAI_INCREASE_NOW (0x3 << 1)
1413 #define CCM_PMCR0_DPTEN (1 << 0)
1414
1415
1416 /* PMCR1 */
1417 #define CCM_PMCR1_DVGP_POS (0)
1418 #define CCM_PMCR1_DVGP_MASK (0xf << 0)
1419
1420 /* IC revision 2.0 or greater ONLY! */
1421 #define CCM_PMCR1_EMIRQ_EN (1 << 8)
1422 #define CCM_PMCR1_PLLRDIS (1 << 7) /* No PLL reset on switch */
1423
1424
1425 /* WEIM - CS0 */
1426 #define CSCRU 0x00
1427 #define CSCRL 0x04
1428 #define CSCRA 0x08
1429
1430 /* ESDCTL */
1431 #define ESDCTL_ESDCTL0 0x00
1432 #define ESDCTL_ESDCFG0 0x04
1433 #define ESDCTL_ESDCTL1 0x08
1434 #define ESDCTL_ESDCFG1 0x0C
1435 #define ESDCTL_ESDMISC 0x10
1436
1437 /* More UART 1 Register defines */
1438 #define URXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00))
1439 #define UTXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x40))
1440 #define UCR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x80))
1441 #define UCR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x84))
1442 #define UCR3_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x88))
1443 #define UCR4_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x8C))
1444 #define UFCR1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x90))
1445 #define USR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x94))
1446 #define USR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x98))
1447 #define UTS1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0xB4))
1448
1449 #define UCR1_2 (*(REG32_PTR_T)(UART2_BASE_ADDR+0x80))
1450 #define UCR1_3 (*(REG32_PTR_T)(UART3_BASE_ADDR+0x80))
1451 #define UCR1_4 (*(REG32_PTR_T)(UART4_BASE_ADDR+0x80))
1452 #define UCR1_5 (*(REG32_PTR_T)(UART5_BASE_ADDR+0x80))
1453
1454 /*
1455 * UART Control Register 0 Bit Fields.
1456 */
1457 #define EUARTUCR1_ADEN (1 << 15) // Auto detect interrupt
1458 #define EUARTUCR1_ADBR (1 << 14) // Auto detect baud rate
1459 #define EUARTUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
1460 #define EUARTUCR1_IDEN (1 << 12) // Idle condition interrupt
1461 #define EUARTUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
1462 #define EUARTUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
1463 #define EUARTUCR1_IREN (1 << 7) // Infrared interface enable
1464 #define EUARTUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable
1465 #define EUARTUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
1466 #define EUARTUCR1_SNDBRK (1 << 4) // Send break
1467 #define EUARTUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
1468 #define EUARTUCR1_DOZE (1 << 1) // Doze
1469 #define EUARTUCR1_UARTEN (1 << 0) // UART enabled
1470 #define EUARTUCR2_ESCI (1 << 15) // Escape seq interrupt enable
1471 #define EUARTUCR2_IRTS (1 << 14) // Ignore RTS pin
1472 #define EUARTUCR2_CTSC (1 << 13) // CTS pin control
1473 #define EUARTUCR2_CTS (1 << 12) // Clear to send
1474 #define EUARTUCR2_ESCEN (1 << 11) // Escape enable
1475 #define EUARTUCR2_PREN (1 << 8) // Parity enable
1476 #define EUARTUCR2_PROE (1 << 7) // Parity odd/even
1477 #define EUARTUCR2_STPB (1 << 6) // Stop
1478 #define EUARTUCR2_WS (1 << 5) // Word size
1479 #define EUARTUCR2_RTSEN (1 << 4) // Request to send interrupt enable
1480 #define EUARTUCR2_ATEN (1 << 3) // Aging timer enable
1481 #define EUARTUCR2_TXEN (1 << 2) // Transmitter enabled
1482 #define EUARTUCR2_RXEN (1 << 1) // Receiver enabled
1483 #define EUARTUCR2_SRST_ (1 << 0) // SW reset
1484 #define EUARTUCR3_PARERREN (1 << 12) // Parity enable
1485 #define EUARTUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
1486 #define EUARTUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
1487 #define EUARTUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
1488 #define EUARTUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
1489 #define EUARTUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
1490 #define EUARTUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
1491 #define EUARTUCR3_INVT (1 << 1) // Inverted Infrared transmission
1492 #define EUARTUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
1493 #define EUARTUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
1494 #define EUARTUCR4_INVR (1 << 9) // Inverted infrared reception
1495 #define EUARTUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
1496 #define EUARTUCR4_WKEN (1 << 7) // Wake interrupt enable
1497 #define EUARTUCR4_IRSC (1 << 5) // IR special case
1498 #define EUARTUCR4_LPBYP (1 << 4) // Low power bypass
1499 #define EUARTUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
1500 #define EUARTUCR4_BKEN (1 << 2) // Break condition interrupt enable
1501 #define EUARTUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
1502 #define EUARTUCR4_DREN (1 << 0) // Recv data ready interrupt enable
1503 #define EUARTUFCR_RXTL_SHF 0 // Receiver trigger level shift
1504 #define EUARTUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1)
1505 #define EUARTUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2)
1506 #define EUARTUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
1507 #define EUARTUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
1508 #define EUARTUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
1509 #define EUARTUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
1510 #define EUARTUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
1511 #define EUARTUFCR_TXTL_SHF 10 // Transmitter trigger level shift
1512 #define EUARTUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
1513 #define EUARTUSR1_RTSS (1 << 14) // RTS pin status
1514 #define EUARTUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
1515 #define EUARTUSR1_RTSD (1 << 12) // RTS delta
1516 #define EUARTUSR1_ESCF (1 << 11) // Escape seq interrupt flag
1517 #define EUARTUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
1518 #define EUARTUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
1519 #define EUARTUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
1520 #define EUARTUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
1521 #define EUARTUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
1522 #define EUARTUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
1523 #define EUARTUSR2_ADET (1 << 15) // Auto baud rate detect complete
1524 #define EUARTUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
1525 #define EUARTUSR2_IDLE (1 << 12) // Idle condition
1526 #define EUARTUSR2_ACST (1 << 11) // Autobaud counter stopped
1527 #define EUARTUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
1528 #define EUARTUSR2_WAKE (1 << 7) // Wake
1529 #define EUARTUSR2_RTSF (1 << 4) // RTS edge interrupt flag
1530 #define EUARTUSR2_TXDC (1 << 3) // Transmitter complete
1531 #define EUARTUSR2_BRCD (1 << 2) // Break condition
1532 #define EUARTUSR2_ORE (1 << 1) // Overrun error
1533 #define EUARTUSR2_RDR (1 << 0) // Recv data ready
1534 #define EUARTUTS_FRCPERR (1 << 13) // Force parity error
1535 #define EUARTUTS_LOOP (1 << 12) // Loop tx and rx
1536 #define EUARTUTS_TXEMPTY (1 << 6) // TxFIFO empty
1537 #define EUARTUTS_RXEMPTY (1 << 5) // RxFIFO empty
1538 #define EUARTUTS_TXFULL (1 << 4) // TxFIFO full
1539 #define EUARTUTS_RXFULL (1 << 3) // RxFIFO full
1540 #define EUARTUTS_SOFTRST (1 << 0) // Software reset
1541
1542 /* SDMA */
1543 #define SDMA_MC0PTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x000))
1544 #define SDMA_INTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x004))
1545 #define SDMA_STOP_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x008))
1546 #define SDMA_HSTART (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x00C))
1547 #define SDMA_EVTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x010))
1548 #define SDMA_DSPOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x014))
1549 #define SDMA_HOSTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x018))
1550 #define SDMA_EVTPEND (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x01C))
1551 #define SDMA_DSPENBL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x020))
1552 #define SDMA_RESET (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x024))
1553 #define SDMA_EVTERR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x028))
1554 #define SDMA_INTRMSK (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x02C))
1555 #define SDMA_PSW (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x030))
1556 #define SDMA_EVTERRDBG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x034))
1557 #define SDMA_CONFIG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x038))
1558 #define SDMA_ONCE_ENB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x040))
1559 #define SDMA_ONCE_DATA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x044))
1560 #define SDMA_ONCE_INSTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x048))
1561 #define SDMA_ONCE_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x04C))
1562 #define SDMA_ONCE_CMD (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x050))
1563 #define SDMA_EVT_MIRROR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x054))
1564 #define SDMA_ILLINSTADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x058))
1565 #define SDMA_CHN0ADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x05C))
1566 #define SDMA_ONCE_RTB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x060))
1567 #define SDMA_XTRIG_CONF1 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x070))
1568 #define SDMA_XTRIG_CONF2 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x074))
1569
1570 /* SDMA_CHNENBL: 0x080 - 0x0FC */
1571 #define SDMA_CHNENBL(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x080))[n]) /* 0..31 */
1572
1573 /* SDMA_CHNPRI: 0x100 - 0x17C */
1574 #define SDMA_CHNPRI(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x100))[n]) /* 0..31 */
1575
1576 #define SDMA_ONCE_COUNT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x200))
1577 #define SDMA_ONCE_ECTL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x204))
1578 #define SDMA_ONCE_EAA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x208))
1579 #define SDMA_ONCE_EAB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x20C))
1580 #define SDMA_ONCE_EAM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x210))
1581 #define SDMA_ONCE_ED (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x214))
1582 #define SDMA_ONCE_EDM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x218))
1583 #define SDMA_ONCE_PCMATCH (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x21C))
1584
1585 /* SDMA_RESET */
1586 #define SDMA_RESET_RESCHED (0x1 << 1)
1587 #define SDMA_RESET_RESET (0x1 << 0)
1588
1589 /* SDMA_PSW */
1590 #define SDMA_PSW_NCP (0x7 << 13)
1591 #define SDMA_PSW_NCR (0x1f << 8)
1592 #define SDMA_PSW_CCP (0x7 << 5)
1593 #define SDMA_PSW_CCR (0x1f << 0)
1594
1595 /* SDMA_CONFIG */
1596 #define SDMA_CONFIG_DSPDMA (0x1 << 12)
1597 #define SDMA_CONFIG_RTDOBS (0x1 << 11)
1598 #define SDMA_CONFIG_ACR (0x1 << 4)
1599 #define SDMA_CONFIG_CSM (0x3 << 0)
1600 #define SDMA_CONFIG_CSM_STATIC (0x0 << 0)
1601 #define SDMA_CONFIG_CSM_DYNAMIC_LOW_POWER (0x1 << 0)
1602 #define SDMA_CONFIG_CSM_DYNAMIC_NO_LOOP (0x2 << 0)
1603 #define SDMA_CONFIG_CSM_DYNAMIC (0x3 << 0)
1604
1605 /* SDMA_ONCE_ENB */
1606 #define SDMA_ONCE_ENB_ENB (0x1 << 0)
1607
1608 /* SDMA_ONCE_STAT */
1609 #define SDMA_ONCE_STAT_PST (0xf << 12)
1610 #define SDMA_ONCE_STAT_PST_PROGRAM (0x0 << 12)
1611 #define SDMA_ONCE_STAT_PST_DATA (0x1 << 12)
1612 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW (0x2 << 12)
1613 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP (0x3 << 12)
1614 #define SDMA_ONCE_STAT_PST_DEBUG (0x4 << 12)
1615 #define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT (0x5 << 12)
1616 #define SDMA_ONCE_STAT_PST_SLEEP (0x6 << 12)
1617 #define SDMA_ONCE_STAT_PST_SAVE (0x7 << 12)
1618 #define SDMA_ONCE_STAT_PST_PROGRAM_IN_SLEEP (0x8 << 12)
1619 #define SDMA_ONCE_STAT_PST_DATA_IN_SLEEP (0x9 << 12)
1620 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_SLEEP (0xa << 12)
1621 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP_IN_SLEEP (0xb << 12)
1622 #define SDMA_ONCE_STAT_PST_DEBUG_IN_SLEEP (0xc << 12)
1623 #define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT_IN_SLEEP (0xd << 12)
1624 #define SDMA_ONCE_STAT_PST_SLEEP_AFTER_RESET (0xe << 12)
1625 #define SDMA_ONCE_STAT_PST_RESTORE (0xf << 12)
1626 #define SDMA_ONCE_STAT_RCV (0x1 << 11)
1627 #define SDMA_ONCE_STAT_EDR (0x1 << 10)
1628 #define SDMA_ONCE_STAT_ODR (0x1 << 9)
1629 #define SDMA_ONCE_STAT_SWB (0x1 << 8)
1630 #define SDMA_ONCE_STAT_MST (0x1 << 7)
1631 #define SDMA_ONCE_STAT_ECDR (0x7 << 0)
1632 #define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRA_COND (0x1 << 0)
1633 #define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRB_COND (0x1 << 1)
1634 #define SDMA_ONCE_STAT_ECDR_MATCHED_DATA_COND (0x1 << 2)
1635
1636 /* SDMA_ONCE_CMD */
1637 #define SDMA_ONCE_CMD_RSTATUS 0x0
1638 #define SDMA_ONCE_CMD_DMOV 0x1
1639 #define SDMA_ONCE_CMD_EXEC_ONCE 0x2
1640 #define SDMA_ONCE_CMD_RUN_CORE 0x3
1641 #define SDMA_ONCE_CMD_EXEC_CORE 0x4
1642 #define SDMA_ONCE_CMD_DEBUG_RQST 0x5
1643 #define SDMA_ONCE_CMD_RBUFFER 0x6
1644 /* 7-15 reserved */
1645
1646 /* SDMA_CHN0ADDR */
1647 #define SDMA_CHN0ADDR_SMSZ (0x1 << 14)
1648 /* 13:0 = 0x0050 by default (std. boot code) */
1649
1650 /* SDMA_EVT_MIRROR */
1651 #define SDMA_EVT_MIRROR_EVENTS(n) (0x1 << (n))
1652
1653 /* SDMA_XTRIG_CONF1 */
1654 #define SDMA_XTRIG_CONF1_CNF3 (0x1 << 30)
1655 #define SDMA_XTRIG_CONF1_NUM3 (0x1f << 24)
1656 #define SDMA_XTRIG_CONF1_CNF2 (0x1 << 22)
1657 #define SDMA_XTRIG_CONF1_NUM2 (0x1f << 16)
1658 #define SDMA_XTRIG_CONF1_CNF1 (0x1 << 14)
1659 #define SDMA_XTRIG_CONF1_NUM1 (0x1f << 8)
1660 #define SDMA_XTRIG_CONF1_CNF0 (0x1 << 6)
1661 #define SDMA_XTRIG_CONF1_NUM0 (0x1f << 0)
1662
1663 /* SDMA_XTRIG_CONF2 */
1664 #define SDMA_XTRIG_CONF2_CNF7 (0x1 << 30)
1665 #define SDMA_XTRIG_CONF2_NUM7 (0x1f << 24)
1666 #define SDMA_XTRIG_CONF2_CNF6 (0x1 << 22)
1667 #define SDMA_XTRIG_CONF2_NUM6 (0x1f << 16)
1668 #define SDMA_XTRIG_CONF2_CNF5 (0x1 << 14)
1669 #define SDMA_XTRIG_CONF2_NUM5 (0x1f << 8)
1670 #define SDMA_XTRIG_CONF2_CNF4 (0x1 << 6)
1671 #define SDMA_XTRIG_CONF2_NUM4 (0x1f << 0)
1672
1673 /* SDMA_CHNENBL(n) */
1674 #define SDMA_CHNENBL_ENBL(n) (0x1 << (n))
1675
1676
1677 #define L2CC_ENABLED
1678
1679 /* Assuming 26MHz input clock */
1680 /* PD MFD MFI MFN */
1681 #define MPCTL_PARAM_208 ((1 << 26) + (0 << 16) + (8 << 10) + (0 << 0))
1682 #define MPCTL_PARAM_399 ((0 << 26) + (51 << 16) + (7 << 10) + (35 << 0))
1683 #define MPCTL_PARAM_532 ((0 << 26) + (51 << 16) + (10 << 10) + (12 << 0))
1684
1685 /* UPCTL PD MFD MFI MFN */
1686 #define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0))
1687 #define UPCTL_PARAM_240 (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
1688
1689 /* PDR0 */
1690 #define PDR0_208_104_52 0xFF870D48 /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
1691 #define PDR0_399_66_66 0xFF872B28 /* ARM=399MHz, HCLK=IPG=66.5MHz */
1692 #define PDR0_399_133_66 0xFF871650 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
1693 #define PDR0_532_133_66 0xFF871E58 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1694 #define PDR0_665_83_66 0xFF873D78 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1695 #define PDR0_665_133_66 0xFF872660 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1696
1697 #define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */
1698
1699 #define PBC_BSTAT2 0x2
1700 #define PBC_BCTRL1 0x4
1701 #define PBC_BCTRL1_CLR 0x6
1702 #define PBC_BCTRL2 0x8
1703 #define PBC_BCTRL2_CLR 0xA
1704 #define PBC_BCTRL3 0xC
1705 #define PBC_BCTRL3_CLR 0xE
1706 #define PBC_BCTRL4 0x10
1707 #define PBC_BCTRL4_CLR 0x12
1708 #define PBC_BSTAT1 0x14
1709 #define MX31EVB_CS_LAN_BASE (CS4_BASE_ADDR + 0x00020000 + 0x300)
1710 #define MX31EVB_CS_UART_BASE (CS4_BASE_ADDR + 0x00010000)
1711
1712 #define REDBOOT_IMAGE_SIZE 0x40000
1713
1714 #define SDRAM_WORKAROUND_FULL_PAGE
1715
1716 #define ARMHIPG_208_52_52 /* ARM: 208MHz, HCLK=IPG=52MHz*/
1717 #define ARMHIPG_52_52_52 /* ARM: 52MHz, HCLK=IPG=52MHz*/
1718 #define ARMHIPG_399_66_66
1719 #define ARMHIPG_399_133_66
1720
1721 /* MX31 EVB SDRAM is from 0x80000000, 64M */
1722 #define SDRAM_BASE_ADDR CSD0_BASE_ADDR
1723 #define SDRAM_SIZE 0x04000000
1724
1725 #define UART_WIDTH_32 /* internal UART is 32bit access only */
1726 #define EXT_UART_x16
1727
1728 #define UART_WIDTH_32 /* internal UART is 32bit access only */
1729
1730 #define FLASH_BURST_MODE_ENABLE 1
1731 #define SDRAM_COMPARE_CONST1 0x55555555
1732 #define SDRAM_COMPARE_CONST2 0xAAAAAAAA
1733 #define UART_FIFO_CTRL 0x881
1734 #define TIMEOUT 1000
1735
1736 /* Timer frequency */
1737 /* timer is based on ipg_clk */
1738 #define TIMER_FREQ (66000000)
1739
1740 #endif /* __IMX31L_H__ */
My public Rockbox git repo