firmware/target/arm/usb-drv-arc.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Driver for ARC USBOTG Device Controller
  11  *
  12  * Copyright (C) 2007 by Björn Stenberg
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  20  * KIND, either express or implied.
  21  *
  22  ****************************************************************************/
  23
  24 #include "system.h"
  25 #include "config.h"
  26 #include "string.h"
  27 #include "usb_ch9.h"
  28 #include "usb_core.h"
  29 #include "kernel.h"
  30 #include "panic.h"
  31 #include "usb_drv.h"
  32
  33 //#define LOGF_ENABLE
  34 #include "logf.h"
  35
  36 /* USB device mode registers (Little Endian) */
  37
  38 #define REG_ID               (*(volatile unsigned int *)(USB_BASE+0x000))
  39 #define REG_HWGENERAL        (*(volatile unsigned int *)(USB_BASE+0x004))
  40 #define REG_HWHOST           (*(volatile unsigned int *)(USB_BASE+0x008))
  41 #define REG_HWDEVICE         (*(volatile unsigned int *)(USB_BASE+0x00c))
  42 #define REG_TXBUF            (*(volatile unsigned int *)(USB_BASE+0x010))
  43 #define REG_RXBUF            (*(volatile unsigned int *)(USB_BASE+0x014))
  44 #define REG_CAPLENGTH        (*(volatile unsigned char*)(USB_BASE+0x100))
  45 #define REG_DCIVERSION       (*(volatile unsigned int *)(USB_BASE+0x120))
  46 #define REG_DCCPARAMS        (*(volatile unsigned int *)(USB_BASE+0x124))
  47 #define REG_USBCMD           (*(volatile unsigned int *)(USB_BASE+0x140))
  48 #define REG_USBSTS           (*(volatile unsigned int *)(USB_BASE+0x144))
  49 #define REG_USBINTR          (*(volatile unsigned int *)(USB_BASE+0x148))
  50 #define REG_FRINDEX          (*(volatile unsigned int *)(USB_BASE+0x14c))
  51 #define REG_DEVICEADDR       (*(volatile unsigned int *)(USB_BASE+0x154))
  52 #define REG_ENDPOINTLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158))
  53 #define REG_BURSTSIZE        (*(volatile unsigned int *)(USB_BASE+0x160))
  54 #define REG_ULPI             (*(volatile unsigned int *)(USB_BASE+0x170))
  55 #define REG_CONFIGFLAG       (*(volatile unsigned int *)(USB_BASE+0x180))
  56 #define REG_PORTSC1          (*(volatile unsigned int *)(USB_BASE+0x184))
  57 #define REG_OTGSC            (*(volatile unsigned int *)(USB_BASE+0x1a4))
  58 #define REG_USBMODE          (*(volatile unsigned int *)(USB_BASE+0x1a8))
  59 #define REG_ENDPTSETUPSTAT   (*(volatile unsigned int *)(USB_BASE+0x1ac))
  60 #define REG_ENDPTPRIME       (*(volatile unsigned int *)(USB_BASE+0x1b0))
  61 #define REG_ENDPTFLUSH       (*(volatile unsigned int *)(USB_BASE+0x1b4))
  62 #define REG_ENDPTSTATUS      (*(volatile unsigned int *)(USB_BASE+0x1b8))
  63 #define REG_ENDPTCOMPLETE    (*(volatile unsigned int *)(USB_BASE+0x1bc))
  64 #define REG_ENDPTCTRL0       (*(volatile unsigned int *)(USB_BASE+0x1c0))
  65 #define REG_ENDPTCTRL1       (*(volatile unsigned int *)(USB_BASE+0x1c4))
  66 #define REG_ENDPTCTRL2       (*(volatile unsigned int *)(USB_BASE+0x1c8))
  67 #define REG_ENDPTCTRL(_x_)   (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(_x_)))
  68
  69 /* Frame Index Register Bit Masks */
  70 #define USB_FRINDEX_MASKS                      (0x3fff)
  71
  72 /* USB CMD  Register Bit Masks */
  73 #define USBCMD_RUN                            (0x00000001)
  74 #define USBCMD_CTRL_RESET                     (0x00000002)
  75 #define USBCMD_PERIODIC_SCHEDULE_EN           (0x00000010)
  76 #define USBCMD_ASYNC_SCHEDULE_EN              (0x00000020)
  77 #define USBCMD_INT_AA_DOORBELL                (0x00000040)
  78 #define USBCMD_ASP                            (0x00000300)
  79 #define USBCMD_ASYNC_SCH_PARK_EN              (0x00000800)
  80 #define USBCMD_SUTW                           (0x00002000)
  81 #define USBCMD_ATDTW                          (0x00004000)
  82 #define USBCMD_ITC                            (0x00FF0000)
  83
  84 /* bit 15,3,2 are frame list size */
  85 #define USBCMD_FRAME_SIZE_1024                (0x00000000)
  86 #define USBCMD_FRAME_SIZE_512                 (0x00000004)
  87 #define USBCMD_FRAME_SIZE_256                 (0x00000008)
  88 #define USBCMD_FRAME_SIZE_128                 (0x0000000C)
  89 #define USBCMD_FRAME_SIZE_64                  (0x00008000)
  90 #define USBCMD_FRAME_SIZE_32                  (0x00008004)
  91 #define USBCMD_FRAME_SIZE_16                  (0x00008008)
  92 #define USBCMD_FRAME_SIZE_8                   (0x0000800C)
  93
  94 /* bit 9-8 are async schedule park mode count */
  95 #define USBCMD_ASP_00                         (0x00000000)
  96 #define USBCMD_ASP_01                         (0x00000100)
  97 #define USBCMD_ASP_10                         (0x00000200)
  98 #define USBCMD_ASP_11                         (0x00000300)
  99 #define USBCMD_ASP_BIT_POS                    (8)
 100
 101 /* bit 23-16 are interrupt threshold control */
 102 #define USBCMD_ITC_NO_THRESHOLD               (0x00000000)
 103 #define USBCMD_ITC_1_MICRO_FRM                (0x00010000)
 104 #define USBCMD_ITC_2_MICRO_FRM                (0x00020000)
 105 #define USBCMD_ITC_4_MICRO_FRM                (0x00040000)
 106 #define USBCMD_ITC_8_MICRO_FRM                (0x00080000)
 107 #define USBCMD_ITC_16_MICRO_FRM               (0x00100000)
 108 #define USBCMD_ITC_32_MICRO_FRM               (0x00200000)
 109 #define USBCMD_ITC_64_MICRO_FRM               (0x00400000)
 110 #define USBCMD_ITC_BIT_POS                    (16)
 111
 112 /* USB STS Register Bit Masks */
 113 #define USBSTS_INT                            (0x00000001)
 114 #define USBSTS_ERR                            (0x00000002)
 115 #define USBSTS_PORT_CHANGE                    (0x00000004)
 116 #define USBSTS_FRM_LST_ROLL                   (0x00000008)
 117 #define USBSTS_SYS_ERR                        (0x00000010) /* not used */
 118 #define USBSTS_IAA                            (0x00000020)
 119 #define USBSTS_RESET                          (0x00000040)
 120 #define USBSTS_SOF                            (0x00000080)
 121 #define USBSTS_SUSPEND                        (0x00000100)
 122 #define USBSTS_HC_HALTED                      (0x00001000)
 123 #define USBSTS_RCL                            (0x00002000)
 124 #define USBSTS_PERIODIC_SCHEDULE              (0x00004000)
 125 #define USBSTS_ASYNC_SCHEDULE                 (0x00008000)
 126
 127 /* USB INTR Register Bit Masks */
 128 #define USBINTR_INT_EN                        (0x00000001)
 129 #define USBINTR_ERR_INT_EN                    (0x00000002)
 130 #define USBINTR_PTC_DETECT_EN                 (0x00000004)
 131 #define USBINTR_FRM_LST_ROLL_EN               (0x00000008)
 132 #define USBINTR_SYS_ERR_EN                    (0x00000010)
 133 #define USBINTR_ASYN_ADV_EN                   (0x00000020)
 134 #define USBINTR_RESET_EN                      (0x00000040)
 135 #define USBINTR_SOF_EN                        (0x00000080)
 136 #define USBINTR_DEVICE_SUSPEND                (0x00000100)
 137
 138 /* ULPI Register Bit Masks */
 139 #define ULPI_ULPIWU                           (0x80000000)
 140 #define ULPI_ULPIRUN                          (0x40000000)
 141 #define ULPI_ULPIRW                           (0x20000000)
 142 #define ULPI_ULPISS                           (0x08000000)
 143 #define ULPI_ULPIPORT                         (0x07000000)
 144 #define ULPI_ULPIADDR                         (0x00FF0000)
 145 #define ULPI_ULPIDATRD                        (0x0000FF00)
 146 #define ULPI_ULPIDATWR                        (0x000000FF)
 147
 148 /* Device Address bit masks */
 149 #define USBDEVICEADDRESS_MASK                 (0xFE000000)
 150 #define USBDEVICEADDRESS_BIT_POS              (25)
 151
 152 /* endpoint list address bit masks */
 153 #define USB_EP_LIST_ADDRESS_MASK               (0xfffff800)
 154
 155 /* PORTSCX  Register Bit Masks */
 156 #define PORTSCX_CURRENT_CONNECT_STATUS         (0x00000001)
 157 #define PORTSCX_CONNECT_STATUS_CHANGE          (0x00000002)
 158 #define PORTSCX_PORT_ENABLE                    (0x00000004)
 159 #define PORTSCX_PORT_EN_DIS_CHANGE             (0x00000008)
 160 #define PORTSCX_OVER_CURRENT_ACT               (0x00000010)
 161 #define PORTSCX_OVER_CURRENT_CHG               (0x00000020)
 162 #define PORTSCX_PORT_FORCE_RESUME              (0x00000040)
 163 #define PORTSCX_PORT_SUSPEND                   (0x00000080)
 164 #define PORTSCX_PORT_RESET                     (0x00000100)
 165 #define PORTSCX_LINE_STATUS_BITS               (0x00000C00)
 166 #define PORTSCX_PORT_POWER                     (0x00001000)
 167 #define PORTSCX_PORT_INDICTOR_CTRL             (0x0000C000)
 168 #define PORTSCX_PORT_TEST_CTRL                 (0x000F0000)
 169 #define PORTSCX_WAKE_ON_CONNECT_EN             (0x00100000)
 170 #define PORTSCX_WAKE_ON_CONNECT_DIS            (0x00200000)
 171 #define PORTSCX_WAKE_ON_OVER_CURRENT           (0x00400000)
 172 #define PORTSCX_PHY_LOW_POWER_SPD              (0x00800000)
 173 #define PORTSCX_PORT_FORCE_FULL_SPEED          (0x01000000)
 174 #define PORTSCX_PORT_SPEED_MASK                (0x0C000000)
 175 #define PORTSCX_PORT_WIDTH                     (0x10000000)
 176 #define PORTSCX_PHY_TYPE_SEL                   (0xC0000000)
 177
 178 /* bit 11-10 are line status */
 179 #define PORTSCX_LINE_STATUS_SE0                (0x00000000)
 180 #define PORTSCX_LINE_STATUS_JSTATE             (0x00000400)
 181 #define PORTSCX_LINE_STATUS_KSTATE             (0x00000800)
 182 #define PORTSCX_LINE_STATUS_UNDEF              (0x00000C00)
 183 #define PORTSCX_LINE_STATUS_BIT_POS            (10)
 184
 185 /* bit 15-14 are port indicator control */
 186 #define PORTSCX_PIC_OFF                        (0x00000000)
 187 #define PORTSCX_PIC_AMBER                      (0x00004000)
 188 #define PORTSCX_PIC_GREEN                      (0x00008000)
 189 #define PORTSCX_PIC_UNDEF                      (0x0000C000)
 190 #define PORTSCX_PIC_BIT_POS                    (14)
 191
 192 /* bit 19-16 are port test control */
 193 #define PORTSCX_PTC_DISABLE                    (0x00000000)
 194 #define PORTSCX_PTC_JSTATE                     (0x00010000)
 195 #define PORTSCX_PTC_KSTATE                     (0x00020000)
 196 #define PORTSCX_PTC_SE0NAK                     (0x00030000)
 197 #define PORTSCX_PTC_PACKET                     (0x00040000)
 198 #define PORTSCX_PTC_FORCE_EN                   (0x00050000)
 199 #define PORTSCX_PTC_BIT_POS                    (16)
 200
 201 /* bit 27-26 are port speed */
 202 #define PORTSCX_PORT_SPEED_FULL                (0x00000000)
 203 #define PORTSCX_PORT_SPEED_LOW                 (0x04000000)
 204 #define PORTSCX_PORT_SPEED_HIGH                (0x08000000)
 205 #define PORTSCX_PORT_SPEED_UNDEF               (0x0C000000)
 206 #define PORTSCX_SPEED_BIT_POS                  (26)
 207
 208 /* bit 28 is parallel transceiver width for UTMI interface */
 209 #define PORTSCX_PTW                            (0x10000000)
 210 #define PORTSCX_PTW_8BIT                       (0x00000000)
 211 #define PORTSCX_PTW_16BIT                      (0x10000000)
 212
 213 /* bit 31-30 are port transceiver select */
 214 #define PORTSCX_PTS_UTMI                       (0x00000000)
 215 #define PORTSCX_PTS_CLASSIC                    (0x40000000)
 216 #define PORTSCX_PTS_ULPI                       (0x80000000)
 217 #define PORTSCX_PTS_FSLS                       (0xC0000000)
 218 #define PORTSCX_PTS_BIT_POS                    (30)
 219
 220 /* USB MODE Register Bit Masks */
 221 #define USBMODE_CTRL_MODE_IDLE                (0x00000000)
 222 #define USBMODE_CTRL_MODE_DEVICE              (0x00000002)
 223 #define USBMODE_CTRL_MODE_HOST                (0x00000003)
 224 #define USBMODE_CTRL_MODE_RSV                 (0x00000001)
 225 #define USBMODE_SETUP_LOCK_OFF                (0x00000008)
 226 #define USBMODE_STREAM_DISABLE                (0x00000010)
 227
 228 /* Endpoint Flush Register */
 229 #define EPFLUSH_TX_OFFSET                      (0x00010000)
 230 #define EPFLUSH_RX_OFFSET                      (0x00000000)
 231
 232 /* Endpoint Setup Status bit masks */
 233 #define EPSETUP_STATUS_MASK                   (0x0000003F)
 234 #define EPSETUP_STATUS_EP0                    (0x00000001)
 235
 236 /* ENDPOINTCTRLx  Register Bit Masks */
 237 #define EPCTRL_TX_ENABLE                       (0x00800000)
 238 #define EPCTRL_TX_DATA_TOGGLE_RST              (0x00400000)    /* Not EP0 */
 239 #define EPCTRL_TX_DATA_TOGGLE_INH              (0x00200000)    /* Not EP0 */
 240 #define EPCTRL_TX_TYPE                         (0x000C0000)
 241 #define EPCTRL_TX_DATA_SOURCE                  (0x00020000)    /* Not EP0 */
 242 #define EPCTRL_TX_EP_STALL                     (0x00010000)
 243 #define EPCTRL_RX_ENABLE                       (0x00000080)
 244 #define EPCTRL_RX_DATA_TOGGLE_RST              (0x00000040)    /* Not EP0 */
 245 #define EPCTRL_RX_DATA_TOGGLE_INH              (0x00000020)    /* Not EP0 */
 246 #define EPCTRL_RX_TYPE                         (0x0000000C)
 247 #define EPCTRL_RX_DATA_SINK                    (0x00000002)    /* Not EP0 */
 248 #define EPCTRL_RX_EP_STALL                     (0x00000001)
 249
 250 /* bit 19-18 and 3-2 are endpoint type */
 251 #define EPCTRL_EP_TYPE_CONTROL                 (0)
 252 #define EPCTRL_EP_TYPE_ISO                     (1)
 253 #define EPCTRL_EP_TYPE_BULK                    (2)
 254 #define EPCTRL_EP_TYPE_INTERRUPT               (3)
 255 #define EPCTRL_TX_EP_TYPE_SHIFT                (18)
 256 #define EPCTRL_RX_EP_TYPE_SHIFT                (2)
 257
 258 /* pri_ctrl Register Bit Masks */
 259 #define PRI_CTRL_PRI_LVL1                      (0x0000000C)
 260 #define PRI_CTRL_PRI_LVL0                      (0x00000003)
 261
 262 /* si_ctrl Register Bit Masks */
 263 #define SI_CTRL_ERR_DISABLE                    (0x00000010)
 264 #define SI_CTRL_IDRC_DISABLE                   (0x00000008)
 265 #define SI_CTRL_RD_SAFE_EN                     (0x00000004)
 266 #define SI_CTRL_RD_PREFETCH_DISABLE            (0x00000002)
 267 #define SI_CTRL_RD_PREFEFETCH_VAL              (0x00000001)
 268
 269 /* control Register Bit Masks */
 270 #define USB_CTRL_IOENB                         (0x00000004)
 271 #define USB_CTRL_ULPI_INT0EN                   (0x00000001)
 272
 273 /* OTGSC Register Bit Masks */
 274 #define OTGSC_B_SESSION_VALID                  (0x00000800)
 275 #define OTGSC_A_VBUS_VALID                     (0x00000200)
 276
 277 #define QH_MULT_POS                            (30)
 278 #define QH_ZLT_SEL                             (0x20000000)
 279 #define QH_MAX_PKT_LEN_POS                     (16)
 280 #define QH_IOS                                 (0x00008000)
 281 #define QH_NEXT_TERMINATE                      (0x00000001)
 282 #define QH_IOC                                 (0x00008000)
 283 #define QH_MULTO                               (0x00000C00)
 284 #define QH_STATUS_HALT                         (0x00000040)
 285 #define QH_STATUS_ACTIVE                       (0x00000080)
 286 #define EP_QUEUE_CURRENT_OFFSET_MASK         (0x00000FFF)
 287 #define EP_QUEUE_HEAD_NEXT_POINTER_MASK      (0xFFFFFFE0)
 288 #define EP_QUEUE_FRINDEX_MASK                (0x000007FF)
 289 #define EP_MAX_LENGTH_TRANSFER               (0x4000)
 290
 291 #define DTD_NEXT_TERMINATE                   (0x00000001)
 292 #define DTD_IOC                              (0x00008000)
 293 #define DTD_STATUS_ACTIVE                    (0x00000080)
 294 #define DTD_STATUS_HALTED                    (0x00000040)
 295 #define DTD_STATUS_DATA_BUFF_ERR             (0x00000020)
 296 #define DTD_STATUS_TRANSACTION_ERR           (0x00000008)
 297 #define DTD_RESERVED_FIELDS                  (0x80007300)
 298 #define DTD_ADDR_MASK                        (0xFFFFFFE0)
 299 #define DTD_PACKET_SIZE                      (0x7FFF0000)
 300 #define DTD_LENGTH_BIT_POS                   (16)
 301 #define DTD_ERROR_MASK                       (DTD_STATUS_HALTED | \
 302                                                DTD_STATUS_DATA_BUFF_ERR | \
 303                                                DTD_STATUS_TRANSACTION_ERR)
 304
 305 #define DTD_RESERVED_LENGTH_MASK             0x0001ffff
 306 #define DTD_RESERVED_IN_USE                  0x80000000
 307 #define DTD_RESERVED_PIPE_MASK               0x0ff00000
 308 #define DTD_RESERVED_PIPE_OFFSET             20
 309 /*-------------------------------------------------------------------------*/
 310
 311 /* manual: 32.13.2 Endpoint Transfer Descriptor (dTD) */
 312 struct transfer_descriptor {
 313     unsigned int next_td_ptr;           /* Next TD pointer(31-5), T(0) set
 314                                            indicate invalid */
 315     unsigned int size_ioc_sts;          /* Total bytes (30-16), IOC (15),
 316                                            MultO(11-10), STS (7-0)  */
 317     unsigned int buff_ptr0;             /* Buffer pointer Page 0 */
 318     unsigned int buff_ptr1;             /* Buffer pointer Page 1 */
 319     unsigned int buff_ptr2;             /* Buffer pointer Page 2 */
 320     unsigned int buff_ptr3;             /* Buffer pointer Page 3 */
 321     unsigned int buff_ptr4;             /* Buffer pointer Page 4 */
 322     unsigned int reserved;
 323 } __attribute__ ((packed));
 324
 325 static struct transfer_descriptor td_array[USB_NUM_ENDPOINTS*2]
 326     USB_DEVBSS_ATTR __attribute__((aligned(32)));
 327
 328 /* manual: 32.13.1 Endpoint Queue Head (dQH) */
 329 struct queue_head {
 330     unsigned int max_pkt_length;    /* Mult(31-30) , Zlt(29) , Max Pkt len
 331                                        and IOS(15) */
 332     unsigned int curr_dtd_ptr;      /* Current dTD Pointer(31-5) */
 333     struct transfer_descriptor dtd; /* dTD overlay */
 334     unsigned int setup_buffer[2];   /* Setup data 8 bytes */
 335     unsigned int reserved;          /* for software use, pointer to the first TD */
 336     unsigned int status;            /* for software use, status of chain in progress */
 337     unsigned int length;            /* for software use, transfered bytes of chain in progress */
 338     unsigned int wait;              /* for softwate use, indicates if the transfer is blocking */
 339 } __attribute__((packed));
 340
 341 static struct queue_head qh_array[USB_NUM_ENDPOINTS*2]
 342     USB_QHARRAY_ATTR;
 343
 344 static struct wakeup transfer_completion_signal[USB_NUM_ENDPOINTS*2]
 345     SHAREDBSS_ATTR;
 346
 347 static const unsigned int pipe2mask[] = {
 348     0x01, 0x010000,
 349     0x02, 0x020000,
 350     0x04, 0x040000,
 351     0x08, 0x080000,
 352     0x10, 0x100000,
 353 };
 354
 355 static char ep_allocation[USB_NUM_ENDPOINTS];
 356
 357 /*-------------------------------------------------------------------------*/
 358 static void transfer_completed(void);
 359 static void control_received(void);
 360 static int prime_transfer(int endpoint, void* ptr,
 361                           int len, bool send, bool wait);
 362 static void prepare_td(struct transfer_descriptor* td,
 363                        struct transfer_descriptor* previous_td,
 364                        void *ptr, int len,int pipe);
 365 static void bus_reset(void);
 366 static void init_control_queue_heads(void);
 367 static void init_bulk_queue_heads(void);
 368 static void init_endpoints(void);
 369 /*-------------------------------------------------------------------------*/
 370 static void usb_drv_stop(void)
 371 {
 372     /* disable interrupts */
 373     REG_USBINTR = 0;
 374     /* stop usb controller (disconnect) */
 375     REG_USBCMD &= ~USBCMD_RUN;
 376 }
 377
 378 void usb_drv_reset(void)
 379 {
 380     int oldlevel = disable_irq_save();
 381     REG_USBCMD &= ~USBCMD_RUN;
 382     restore_irq(oldlevel);
 383
 384 #ifdef USB_PORTSCX_PHY_TYPE
 385     /* If a PHY type is specified, set it now */
 386     REG_PORTSC1 = (REG_PORTSC1 & ~PORTSCX_PHY_TYPE_SEL) | USB_PORTSCX_PHY_TYPE;
 387 #endif
 388     sleep(HZ/20);
 389     REG_USBCMD |= USBCMD_CTRL_RESET;
 390     while (REG_USBCMD & USBCMD_CTRL_RESET);
 391
 392 #if CONFIG_CPU == PP5022 || CONFIG_CPU == PP5024
 393     /* On a CPU which identifies as a PP5022, this
 394        initialization must be done after USB is reset.
 395      */
 396     outl(inl(0x70000060) | 0xF, 0x70000060);
 397     outl(inl(0x70000028) | 0x10000, 0x70000028);
 398     outl(inl(0x70000028) & ~0x10000, 0x70000028);
 399     outl(inl(0x70000060) & ~0x20, 0x70000060);
 400     udelay(10);
 401     outl(inl(0x70000060) | 0x20, 0x70000060);
 402     udelay(10);
 403     outl((inl(0x70000060) & ~0xF) | 4, 0x70000060);
 404     udelay(10);
 405     outl(inl(0x70000060) & ~0x20, 0x70000060);
 406     udelay(10);
 407     outl(inl(0x70000060) & ~0xF, 0x70000060);
 408     udelay(10);
 409     outl(inl(0x70000060) | 0x20, 0x70000060);
 410     udelay(10);
 411     outl(inl(0x70000028) | 0x800, 0x70000028);
 412     outl(inl(0x70000028) & ~0x800, 0x70000028);
 413     while (inl(0x70000028) & 0x80);
 414 #endif
 415 }
 416
 417 /* One-time driver startup init */
 418 void usb_drv_startup(void)
 419 {
 420     /* Initialize all the signal objects once */
 421     int i;
 422     for(i=0;i<USB_NUM_ENDPOINTS*2;i++) {
 423         wakeup_init(&transfer_completion_signal[i]);
 424     }
 425 }
 426
 427 /* manual: 32.14.1 Device Controller Initialization */
 428 static void _usb_drv_init(bool attach)
 429 {
 430     usb_drv_reset();
 431
 432     REG_USBMODE = USBMODE_CTRL_MODE_DEVICE;
 433
 434 #ifdef USB_NO_HIGH_SPEED
 435     /* Force device to full speed */
 436     /* See 32.9.5.9.2 */
 437     REG_PORTSC1 |= PORTSCX_PORT_FORCE_FULL_SPEED;
 438 #endif
 439
 440     init_control_queue_heads();
 441     memset(td_array, 0, sizeof td_array);
 442
 443     REG_ENDPOINTLISTADDR = (unsigned int)qh_array;
 444     REG_DEVICEADDR = 0;
 445
 446     if (!attach) {
 447         /* enable RESET interrupt */
 448         REG_USBINTR = USBINTR_RESET_EN;
 449     }
 450     else
 451     {
 452         /* enable USB interrupts */
 453         REG_USBINTR =
 454             USBINTR_INT_EN |
 455             USBINTR_ERR_INT_EN |
 456             USBINTR_PTC_DETECT_EN |
 457             USBINTR_RESET_EN;
 458     }
 459
 460     usb_drv_int_enable(true);
 461
 462     /* go go go */
 463     REG_USBCMD |= USBCMD_RUN;
 464
 465     logf("usb_drv_init() finished");
 466     logf("usb id %x", REG_ID);
 467     logf("usb dciversion %x", REG_DCIVERSION);
 468     logf("usb dccparams %x", REG_DCCPARAMS);
 469
 470     /* now a bus reset will occur. see bus_reset() */
 471     (void)attach;
 472 }
 473
 474 void usb_drv_init(void)
 475 {
 476     _usb_drv_init(false);
 477 }
 478
 479 /* fully enable driver */
 480 void usb_drv_attach(void)
 481 {
 482     sleep(HZ/10);
 483     _usb_drv_init(true);
 484 }
 485
 486 void usb_drv_exit(void)
 487 {
 488     usb_drv_stop();
 489
 490     /* TODO : is one of these needed to save power ?
 491     REG_PORTSC1 |= PORTSCX_PHY_LOW_POWER_SPD;
 492     REG_USBCMD |= USBCMD_CTRL_RESET;
 493     */
 494
 495     usb_drv_int_enable(false);
 496 }
 497
 498 void usb_drv_int(void)
 499 {
 500     unsigned int usbintr = REG_USBINTR; /* Only watch enabled ints */
 501     unsigned int status = REG_USBSTS & usbintr;
 502
 503 #if 0
 504     if (status & USBSTS_INT) logf("int: usb ioc");
 505     if (status & USBSTS_ERR) logf("int: usb err");
 506     if (status & USBSTS_PORT_CHANGE) logf("int: portchange");
 507     if (status & USBSTS_RESET) logf("int: reset");
 508 #endif
 509
 510     /* usb transaction interrupt */
 511     if (status & USBSTS_INT) {
 512         REG_USBSTS = USBSTS_INT;
 513
 514         /* a control packet? */
 515         if (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0) {
 516             control_received();
 517         }
 518
 519         if (REG_ENDPTCOMPLETE)
 520             transfer_completed();
 521     }
 522
 523     /* error interrupt */
 524     if (status & USBSTS_ERR) {
 525         REG_USBSTS = USBSTS_ERR;
 526         logf("usb error int");
 527     }
 528
 529     /* reset interrupt */
 530     if (status & USBSTS_RESET) {
 531         REG_USBSTS = USBSTS_RESET;
 532
 533         if (UNLIKELY(usbintr == USBINTR_RESET_EN)) {
 534             /* USB detected - detach and inform */
 535             usb_drv_stop();
 536             usb_drv_usb_detect_event();
 537         }
 538         else
 539         {
 540             bus_reset();
 541             usb_core_bus_reset(); /* tell mom */
 542         }
 543     }
 544
 545     /* port change */
 546     if (status & USBSTS_PORT_CHANGE) {
 547         REG_USBSTS = USBSTS_PORT_CHANGE;
 548     }
 549 }
 550
 551 bool usb_drv_stalled(int endpoint,bool in)
 552 {
 553     if(in) {
 554         return ((REG_ENDPTCTRL(endpoint&0x7f) & EPCTRL_TX_EP_STALL)!=0);
 555     }
 556     else {
 557         return ((REG_ENDPTCTRL(endpoint&0x7f) & EPCTRL_RX_EP_STALL)!=0);
 558     }
 559
 560 }
 561 void usb_drv_stall(int endpoint, bool stall,bool in)
 562 {
 563     logf("%sstall %d", stall?"":"un", endpoint&0x7f);
 564
 565     if(in) {
 566         if (stall) {
 567             REG_ENDPTCTRL(endpoint&0x7f) |= EPCTRL_TX_EP_STALL;
 568         }
 569         else {
 570             REG_ENDPTCTRL(endpoint&0x7f) &= ~EPCTRL_TX_EP_STALL;
 571         }
 572     }
 573     else {
 574         if (stall) {
 575             REG_ENDPTCTRL(endpoint) |= EPCTRL_RX_EP_STALL;
 576         }
 577         else {
 578             REG_ENDPTCTRL(endpoint) &= ~EPCTRL_RX_EP_STALL;
 579         }
 580     }
 581 }
 582
 583 int usb_drv_send_nonblocking(int endpoint, void* ptr, int length)
 584 {
 585     return prime_transfer(endpoint&0x7f, ptr, length, true, false);
 586 }
 587
 588 int usb_drv_send(int endpoint, void* ptr, int length)
 589 {
 590     return prime_transfer(endpoint&0x7f, ptr, length, true, true);
 591 }
 592
 593 int usb_drv_recv(int endpoint, void* ptr, int length)
 594 {
 595     //logf("usbrecv(%x, %d)", ptr, length);
 596     return prime_transfer(endpoint&0x7f, ptr, length, false, false);
 597 }
 598
 599 int usb_drv_port_speed(void)
 600 {
 601     return (REG_PORTSC1 & 0x08000000) ? 1 : 0;
 602 }
 603
 604 bool usb_drv_connected(void)
 605 {
 606     return (REG_PORTSC1 &
 607         (PORTSCX_PORT_SUSPEND | PORTSCX_CURRENT_CONNECT_STATUS))
 608             == PORTSCX_CURRENT_CONNECT_STATUS;
 609 }
 610
 611 bool usb_drv_powered(void)
 612 {
 613     /* true = bus 4V4 ok */
 614     return (REG_OTGSC & OTGSC_A_VBUS_VALID) ? true : false;
 615 }
 616
 617 void usb_drv_set_address(int address)
 618 {
 619     REG_DEVICEADDR = address << USBDEVICEADDRESS_BIT_POS;
 620     init_bulk_queue_heads();
 621     init_endpoints();
 622 }
 623
 624 void usb_drv_reset_endpoint(int endpoint, bool send)
 625 {
 626     int pipe = (endpoint&0x7f) * 2 + (send ? 1 : 0);
 627     unsigned int mask = pipe2mask[pipe];
 628     REG_ENDPTFLUSH = mask;
 629     while (REG_ENDPTFLUSH & mask);
 630 }
 631
 632 void usb_drv_set_test_mode(int mode)
 633 {
 634     switch(mode){
 635         case 0:
 636             REG_PORTSC1 &= ~PORTSCX_PORT_TEST_CTRL;
 637             break;
 638         case 1:
 639             REG_PORTSC1 |= PORTSCX_PTC_JSTATE;
 640             break;
 641         case 2:
 642             REG_PORTSC1 |= PORTSCX_PTC_KSTATE;
 643             break;
 644         case 3:
 645             REG_PORTSC1 |= PORTSCX_PTC_SE0NAK;
 646             break;
 647         case 4:
 648             REG_PORTSC1 |= PORTSCX_PTC_PACKET;
 649             break;
 650         case 5:
 651             REG_PORTSC1 |= PORTSCX_PTC_FORCE_EN;
 652             break;
 653     }
 654     usb_drv_reset();
 655     REG_USBCMD |= USBCMD_RUN;
 656 }
 657
 658 /*-------------------------------------------------------------------------*/
 659
 660 /* manual: 32.14.5.2 */
 661 static int prime_transfer(int endpoint, void* ptr, int len, bool send, bool wait)
 662 {
 663     int rc = 0;
 664     int pipe = endpoint * 2 + (send ? 1 : 0);
 665     unsigned int mask = pipe2mask[pipe];
 666     struct queue_head* qh = &qh_array[pipe];
 667     static long last_tick;
 668     struct transfer_descriptor* new_td;
 669
 670     int oldlevel = disable_irq_save();
 671 /*
 672     if (send && endpoint > EP_CONTROL) {
 673         logf("usb: sent %d bytes", len);
 674     }
 675 */
 676     qh->status = 0;
 677     qh->length = 0;
 678     qh->wait   = wait;
 679
 680     new_td=&td_array[pipe];
 681     prepare_td(new_td, 0, ptr, len,pipe);
 682     //logf("starting ep %d %s",endpoint,send?"send":"receive");
 683
 684     qh->dtd.next_td_ptr = (unsigned int)new_td;
 685     qh->dtd.size_ioc_sts &= ~(QH_STATUS_HALT | QH_STATUS_ACTIVE);
 686
 687     REG_ENDPTPRIME |= mask;
 688
 689     if(endpoint == EP_CONTROL && (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0)) {
 690         /* 32.14.3.2.2 */
 691         logf("new setup arrived");
 692         rc = -4;
 693         goto pt_error;
 694     }
 695
 696     last_tick = current_tick;
 697     while ((REG_ENDPTPRIME & mask)) {
 698         if (REG_USBSTS & USBSTS_RESET) {
 699             rc = -1;
 700             goto pt_error;
 701         }
 702
 703         if (TIME_AFTER(current_tick, last_tick + HZ/4)) {
 704             logf("prime timeout");
 705             rc = -2;
 706             goto pt_error;
 707         }
 708     }
 709
 710     if (!(REG_ENDPTSTATUS & mask)) {
 711         logf("no prime! %d %d %x", endpoint, pipe, qh->dtd.size_ioc_sts & 0xff );
 712         rc = -3;
 713         goto pt_error;
 714     }
 715     if(endpoint == EP_CONTROL && (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0)) {
 716         /* 32.14.3.2.2 */
 717         logf("new setup arrived");
 718         rc = -4;
 719         goto pt_error;
 720     }
 721
 722     restore_irq(oldlevel);
 723
 724     if (wait) {
 725         /* wait for transfer to finish */
 726         wakeup_wait(&transfer_completion_signal[pipe], TIMEOUT_BLOCK);
 727         if(qh->status!=0) {
 728             /* No need to cancel wait here since it was done and the signal
 729              * came. */
 730             return -5;
 731         }
 732         //logf("all tds done");
 733     }
 734
 735 pt_error:
 736     if(rc<0)
 737         restore_irq(oldlevel);
 738
 739     /* Error status must make sure an abandoned wakeup signal isn't left */
 740     if (rc < 0 && wait) {
 741         /* Cancel wait */
 742         qh->wait = 0;
 743         /* Make sure to remove any signal if interrupt fired before we zeroed
 744          * qh->wait. Could happen during a bus reset for example. */
 745         wakeup_wait(&transfer_completion_signal[pipe], TIMEOUT_NOBLOCK);
 746     }
 747
 748     return rc;
 749 }
 750
 751 void usb_drv_cancel_all_transfers(void)
 752 {
 753     int i;
 754     REG_ENDPTFLUSH = ~0;
 755     while (REG_ENDPTFLUSH);
 756
 757     memset(td_array, 0, sizeof td_array);
 758     for(i=0;i<USB_NUM_ENDPOINTS*2;i++) {
 759         if(qh_array[i].wait) {
 760             qh_array[i].wait=0;
 761             qh_array[i].status=DTD_STATUS_HALTED;
 762             wakeup_signal(&transfer_completion_signal[i]);
 763         }
 764     }
 765 }
 766
 767 int usb_drv_request_endpoint(int dir)
 768 {
 769     int i, bit;
 770
 771     bit=(dir & USB_DIR_IN)? 2:1;
 772
 773     for (i=1; i < USB_NUM_ENDPOINTS; i++) {
 774         if((ep_allocation[i] & bit)!=0)
 775             continue;
 776         ep_allocation[i] |= bit;
 777         return i | dir;
 778     }
 779
 780     return -1;
 781 }
 782
 783 void usb_drv_release_endpoint(int ep)
 784 {
 785     int mask = (ep & USB_DIR_IN)? ~2:~1;
 786     ep_allocation[ep & 0x7f] &= mask;
 787 }
 788
 789
 790 static void prepare_td(struct transfer_descriptor* td,
 791                        struct transfer_descriptor* previous_td,
 792                        void *ptr, int len,int pipe)
 793 {
 794     //logf("adding a td : %d",len);
 795     memset(td, 0, sizeof(struct transfer_descriptor));
 796     td->next_td_ptr = DTD_NEXT_TERMINATE;
 797     td->size_ioc_sts = (len<< DTD_LENGTH_BIT_POS) |
 798         DTD_STATUS_ACTIVE | DTD_IOC;
 799     td->buff_ptr0 = (unsigned int)ptr;
 800     td->buff_ptr1 = ((unsigned int)ptr & 0xfffff000) + 0x1000;
 801     td->buff_ptr2 = ((unsigned int)ptr & 0xfffff000) + 0x2000;
 802     td->buff_ptr3 = ((unsigned int)ptr & 0xfffff000) + 0x3000;
 803     td->buff_ptr4 = ((unsigned int)ptr & 0xfffff000) + 0x4000;
 804     td->reserved |= DTD_RESERVED_LENGTH_MASK & len;
 805     td->reserved |= DTD_RESERVED_IN_USE;
 806     td->reserved |= (pipe << DTD_RESERVED_PIPE_OFFSET);
 807
 808     if (previous_td != 0) {
 809         previous_td->next_td_ptr=(unsigned int)td;
 810     }
 811 }
 812
 813 static void control_received(void)
 814 {
 815     int i;
 816     /* copy setup data from packet */
 817     static unsigned int tmp[2];
 818     tmp[0] = qh_array[0].setup_buffer[0];
 819     tmp[1] = qh_array[0].setup_buffer[1];
 820
 821     /* acknowledge packet recieved */
 822     REG_ENDPTSETUPSTAT = EPSETUP_STATUS_EP0;
 823
 824     /* Stop pending control transfers */
 825     for(i=0;i<2;i++) {
 826         if(qh_array[i].wait) {
 827             qh_array[i].wait=0;
 828             qh_array[i].status=DTD_STATUS_HALTED;
 829             wakeup_signal(&transfer_completion_signal[i]);
 830         }
 831     }
 832
 833     usb_core_control_request((struct usb_ctrlrequest*)tmp);
 834 }
 835
 836 static void transfer_completed(void)
 837 {
 838     int ep;
 839     unsigned int mask = REG_ENDPTCOMPLETE;
 840     REG_ENDPTCOMPLETE = mask;
 841
 842     for (ep=0; ep<USB_NUM_ENDPOINTS; ep++) {
 843         int dir;
 844         for (dir=0; dir<2; dir++) {
 845             int pipe = ep * 2 + dir;
 846             if (mask & pipe2mask[pipe]) {
 847                 struct queue_head* qh = &qh_array[pipe];
 848                 struct transfer_descriptor *td = &td_array[pipe];
 849
 850                 if(td->size_ioc_sts & DTD_STATUS_ACTIVE) {
 851                     /* TODO this shouldn't happen, but...*/
 852                     break;
 853                 }
 854                 if((td->size_ioc_sts & DTD_PACKET_SIZE) >> DTD_LENGTH_BIT_POS != 0 && dir==0) {
 855                     /* We got less data than we asked for. */
 856                 }
 857                 qh->length = (td->reserved & DTD_RESERVED_LENGTH_MASK) -
 858                     ((td->size_ioc_sts & DTD_PACKET_SIZE) >> DTD_LENGTH_BIT_POS);
 859                 if(td->size_ioc_sts & DTD_ERROR_MASK) {
 860                     logf("pipe %d err %x", pipe, td->size_ioc_sts & DTD_ERROR_MASK);
 861                     qh->status |= td->size_ioc_sts & DTD_ERROR_MASK;
 862                     /* TODO we need to handle this somehow. Flush the endpoint ? */
 863                 }
 864                 if(qh->wait) {
 865                     qh->wait=0;
 866                     wakeup_signal(&transfer_completion_signal[pipe]);
 867                 }
 868                 usb_core_transfer_complete(ep, dir?USB_DIR_IN:USB_DIR_OUT, qh->status, qh->length);
 869             }
 870         }
 871     }
 872 }
 873
 874 /* manual: 32.14.2.1 Bus Reset */
 875 static void bus_reset(void)
 876 {
 877     int i;
 878     logf("usb bus_reset");
 879
 880     REG_DEVICEADDR = 0;
 881     REG_ENDPTSETUPSTAT = REG_ENDPTSETUPSTAT;
 882     REG_ENDPTCOMPLETE  = REG_ENDPTCOMPLETE;
 883
 884     for (i=0; i<100; i++) {
 885         if (!REG_ENDPTPRIME)
 886             break;
 887
 888         if (REG_USBSTS & USBSTS_RESET) {
 889             logf("usb: double reset");
 890             return;
 891         }
 892
 893         udelay(100);
 894     }
 895     if (REG_ENDPTPRIME) {
 896         logf("usb: short reset timeout");
 897     }
 898
 899     usb_drv_cancel_all_transfers();
 900
 901     if (!(REG_PORTSC1 & PORTSCX_PORT_RESET)) {
 902         logf("usb: slow reset!");
 903     }
 904 }
 905
 906 /* manual: 32.14.4.1 Queue Head Initialization */
 907 static void init_control_queue_heads(void)
 908 {
 909     memset(qh_array, 0, sizeof qh_array);
 910
 911     /*** control ***/
 912     qh_array[EP_CONTROL].max_pkt_length = 64 << QH_MAX_PKT_LEN_POS | QH_IOS;
 913     qh_array[EP_CONTROL].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 914     qh_array[EP_CONTROL+1].max_pkt_length = 64 << QH_MAX_PKT_LEN_POS;
 915     qh_array[EP_CONTROL+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 916 }
 917 /* manual: 32.14.4.1 Queue Head Initialization */
 918 static void init_bulk_queue_heads(void)
 919 {
 920     int tx_packetsize;
 921     int rx_packetsize;
 922     int i;
 923
 924     if (usb_drv_port_speed()) {
 925         rx_packetsize = 512;
 926         tx_packetsize = 512;
 927     }
 928     else {
 929         rx_packetsize = 64;
 930         tx_packetsize = 64;
 931     }
 932     /* TODO: this should take ep_allocation into account */
 933
 934     /*** bulk ***/
 935     for(i=1;i<USB_NUM_ENDPOINTS;i++) {
 936         qh_array[i*2].max_pkt_length = rx_packetsize << QH_MAX_PKT_LEN_POS | QH_ZLT_SEL;
 937         qh_array[i*2].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 938         qh_array[i*2+1].max_pkt_length = tx_packetsize << QH_MAX_PKT_LEN_POS | QH_ZLT_SEL;
 939         qh_array[i*2+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 940     }
 941 }
 942
 943 static void init_endpoints(void)
 944 {
 945     int i;
 946     /* TODO: this should take ep_allocation into account */
 947     /* bulk */
 948     for(i=1;i<USB_NUM_ENDPOINTS;i++) {
 949         REG_ENDPTCTRL(i) =
 950             EPCTRL_RX_DATA_TOGGLE_RST | EPCTRL_RX_ENABLE |
 951             EPCTRL_TX_DATA_TOGGLE_RST | EPCTRL_TX_ENABLE |
 952             (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT) |
 953             (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT);
 954     }
 955 }