firmware/target/arm/system-pp5002.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Alan Korr
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "system.h"
  22
  23 #ifndef BOOTLOADER
  24 #include "adc-target.h"
  25 #include "button-target.h"
  26
  27 extern void TIMER1(void);
  28 extern void TIMER2(void);
  29
  30 void __attribute__((interrupt("IRQ"))) irq_handler(void)
  31 {
  32     if(CURRENT_CORE == CPU)
  33     {
  34         if (CPU_INT_STAT & TIMER1_MASK)
  35             TIMER1();
  36         else if (CPU_INT_STAT & TIMER2_MASK)
  37             TIMER2();
  38         else if (CPU_INT_STAT & GPIO_MASK)
  39         {
  40             if (GPIOA_INT_STAT)
  41                 ipod_3g_button_int();
  42 #ifdef IPOD_1G2G
  43             if (GPIOB_INT_STAT & 0x04)
  44                 ipod_2g_adc_int();
  45 #endif
  46         }
  47     }
  48     else
  49     {
  50         if (COP_INT_STAT & TIMER2_MASK)
  51             TIMER2();
  52     }
  53 }
  54
  55 #endif
  56
  57 /* TODO: The following two function have been lifted straight from IPL, and
  58    hence have a lot of numeric addresses used straight. I'd like to use
  59    #defines for these, but don't know what most of them are for or even what
  60    they should be named. Because of this I also have no way of knowing how
  61    to extend the funtions to do alternate cache configurations and/or
  62    some other CPU frequency scaling. */
  63
  64 #ifndef BOOTLOADER
  65 void ICODE_ATTR __attribute__((naked)) cpucache_flush(void)
  66 {
  67     asm volatile(
  68         "mov    r0, #0xf0000000 \n"
  69         "add    r0, r0, #0xc000 \n" /* r0 = CACHE_FLUSH_BASE */
  70         "add    r1, r0, #0x2000 \n" /* r1 = CACHE_FLUSH_BASE + CACHE_SIZE */
  71         "mov    r2, #0          \n"
  72     "1:                         \n"
  73         "str    r2, [r0], #16   \n" /* Flush */
  74         "cmp    r0, r1          \n"
  75         "blo    1b              \n"
  76         "bx     lr              \n"
  77     );
  78 }
  79
  80 void ICODE_ATTR  __attribute__((naked)) cpucache_invalidate(void)
  81 {
  82     asm volatile(
  83         "mov    r0, #0xf0000000 \n"
  84         "add    r2, r0, #0x4000 \n" /* r1 = CACHE_INVALIDATE_BASE */
  85         "add    r0, r0, #0xc000 \n" /* r0 = CACHE_FLUSH_BASE */
  86         "add    r1, r0, #0x2000 \n" /* r2 = CACHE_FLUSH_BASE + CACHE_SIZE */
  87         "mov    r3, #0          \n"
  88     "1:                         \n"
  89         "str    r3, [r0], #16   \n" /* Flush */
  90         "str    r3, [r2], #16   \n" /* Invalidate */
  91         "cmp    r0, r1          \n"
  92         "blo    1b              \n"
  93         "bx     lr              \n"
  94     );
  95 }
  96
  97 static void ipod_init_cache(void)
  98 {
  99 /* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
 100     PROC_STAT &= ~0x700;
 101     outl(0x4000, 0xcf004020);
 102
 103     CACHE_CTL = CACHE_CTL_INIT;
 104
 105     asm volatile(
 106         "mov    r0, #0xf0000000 \n"
 107         "add    r0, r0, #0x4000 \n" /* r0 = CACHE_INVALIDATE_BASE */
 108         "add    r1, r0, #0x2000 \n" /* r1 = CACHE_INVALIDATE_BASE + CACHE_SIZE */
 109         "mov    r2, #0          \n"
 110     "1:                         \n"
 111         "str    r2, [r0], #16   \n" /* Invalidate */
 112         "cmp    r0, r1          \n"
 113         "blo    1b              \n"
 114         : : : "r0", "r1", "r2"
 115     );
 116
 117     /* Cache if (addr & mask) >> 16 == (mask & match) >> 16:
 118      * yes: 0x00000000 - 0x03ffffff
 119      *  no: 0x04000000 - 0x1fffffff
 120      * yes: 0x20000000 - 0x23ffffff
 121      *  no: 0x24000000 - 0x3fffffff <= range containing uncached alias
 122      */
 123     CACHE_MASK = 0x00001c00;
 124     CACHE_OPERATION = 0x3fc0;
 125
 126     CACHE_CTL = CACHE_CTL_INIT | CACHE_CTL_RUN;
 127 }
 128
 129 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 130 void set_cpu_frequency(long frequency)
 131 #else
 132 static void pp_set_cpu_frequency(long frequency)
 133 #endif
 134 {
 135     cpu_frequency = frequency;
 136
 137     PLL_CONTROL |= 0x6000;     /* make sure some enable bits are set */
 138     CLOCK_ENABLE = 0x01;       /* select source #1 */
 139
 140     switch (frequency)
 141     {
 142       case CPUFREQ_MAX:
 143         PLL_UNLOCK   = 0xd19b; /* unlock frequencies > 66MHz */
 144         CLOCK_SOURCE = 0xa9;   /* source #1: 24 Mhz, source #2..#4: PLL */
 145         PLL_CONTROL  = 0xe000; /* PLL enabled */
 146         PLL_DIV      = 3;      /* 10/3 * 24MHz */
 147         PLL_MULT     = 10;
 148         udelay(200);           /* wait for relock */
 149         break;
 150
 151       case CPUFREQ_NORMAL:
 152         CLOCK_SOURCE = 0xa9;   /* source #1: 24 Mhz, source #2..#4: PLL */
 153         PLL_CONTROL  = 0xe000; /* PLL enabled */
 154         PLL_DIV      = 4;      /* 5/4 * 24MHz */
 155         PLL_MULT     = 5;
 156         udelay(200);           /* wait for relock */
 157         break;
 158
 159       case CPUFREQ_SLEEP:
 160         CLOCK_SOURCE = 0x51;   /* source #2: 32kHz, #1, #2, #4: 24MHz */
 161         PLL_CONTROL  = 0x6000; /* PLL disabled */
 162         udelay(10000);         /* let 32kHz source stabilize? */
 163         break;
 164
 165       default:
 166         CLOCK_SOURCE = 0x55;   /* source #1..#4: 24 Mhz */
 167         PLL_CONTROL  = 0x6000; /* PLL disabled */
 168         cpu_frequency = CPUFREQ_DEFAULT;
 169         break;
 170     }
 171     CLOCK_ENABLE = 0x02;       /* select source #2 */
 172 }
 173 #endif /* !BOOTLOADER */
 174
 175 void system_init(void)
 176 {
 177 #ifndef BOOTLOADER
 178     if (CURRENT_CORE == CPU)
 179     {
 180         /* Remap the flash ROM on CPU, keep hidden from COP:
 181          * 0x00000000-0x03ffffff = 0x20000000-0x23ffffff */
 182         MMAP1_LOGICAL  = 0x20003c00;
 183         MMAP1_PHYSICAL = 0x00003f84;
 184
 185 #if defined(IPOD_1G2G) || defined(IPOD_3G)
 186         DEV_EN = 0x0b9f; /* don't clock unused PP5002 hardware components */
 187         outl(0x0035, 0xcf005004);  /* DEV_EN2 ? */
 188 #endif
 189
 190         INT_FORCED_CLR = -1;
 191         CPU_INT_DIS    = -1;
 192         COP_INT_DIS    = -1;
 193
 194         GPIOA_INT_EN   = 0;
 195         GPIOB_INT_EN   = 0;
 196         GPIOC_INT_EN   = 0;
 197         GPIOD_INT_EN   = 0;
 198
 199 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 200 #if NUM_CORES > 1
 201         cpu_boost_init();
 202 #endif
 203 #else
 204         pp_set_cpu_frequency(CPUFREQ_MAX);
 205 #endif
 206     }
 207     ipod_init_cache();
 208 #endif
 209 }
 210
 211 void system_reboot(void)
 212 {
 213     DEV_RS |= 4;
 214     while (1);
 215 }
 216
 217 void system_exception_wait(void)
 218 {
 219     /* FIXME: we just need the right buttons */
 220     CPU_INT_DIS = -1;
 221     COP_INT_DIS = -1;
 222
 223     /* Halt */
 224     sleep_core(CURRENT_CORE);
 225     while (1);
 226 }
 227
 228 int system_memory_guard(int newmode)
 229 {
 230     (void)newmode;
 231     return 0;
 232 }