firmware/target/arm/imx31/mc13783-imx31.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (c) 2008 by Michael Sevakis
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "system.h"
  22 #include "cpu.h"
  23 #include "spi-imx31.h"
  24 #include "gpio-imx31.h"
  25 #include "mc13783.h"
  26 #include "debug.h"
  27 #include "kernel.h"
  28
  29 #ifdef BOOTLOADER
  30 #define PMIC_DRIVER_CLOSE
  31 #endif
  32
  33 /* This is all based on communicating with the MC13783 PMU which is on
  34  * CSPI2 with the chip select at 0. The LCD controller resides on
  35  * CSPI3 cs1, but we have no idea how to communicate to it */
  36 static struct spi_node mc13783_spi =
  37 {
  38     CSPI2_NUM,                     /* CSPI module 2 */
  39     CSPI_CONREG_CHIP_SELECT_SS0 |  /* Chip select 0 */
  40     CSPI_CONREG_DRCTL_DONT_CARE |  /* Don't care about CSPI_RDY */
  41     CSPI_CONREG_DATA_RATE_DIV_32 | /* Clock = IPG_CLK/32 = 2,062,500Hz. */
  42     CSPI_BITCOUNT(32-1) |          /* All 32 bits are to be transferred */
  43     CSPI_CONREG_SSPOL |            /* SS active high */
  44     CSPI_CONREG_SSCTL |            /* Negate SS between SPI bursts */
  45     CSPI_CONREG_MODE,              /* Master mode */
  46     0,                             /* SPI clock - no wait states */
  47 };
  48
  49 extern const struct mc13783_event_list mc13783_event_list;
  50
  51 static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)];
  52 static const char *mc13783_thread_name = "pmic";
  53 static struct wakeup mc13783_wake;
  54
  55 /* Tracking for which interrupts are enabled */
  56 static uint32_t pmic_int_enabled[2] =
  57     { 0x00000000, 0x00000000 };
  58
  59 static const unsigned char pmic_intm_regs[2] =
  60     { MC13783_INTERRUPT_MASK0, MC13783_INTERRUPT_MASK1 };
  61
  62 static const unsigned char pmic_ints_regs[2] =
  63     { MC13783_INTERRUPT_STATUS0, MC13783_INTERRUPT_STATUS1 };
  64
  65 #ifdef PMIC_DRIVER_CLOSE
  66 static bool pmic_close = false;
  67 static unsigned int mc13783_thread_id = 0;
  68 #endif
  69
  70 static void mc13783_interrupt_thread(void)
  71 {
  72     uint32_t pending[2];
  73
  74     /* Enable mc13783 GPIO event */
  75     gpio_enable_event(MC13783_EVENT_ID);
  76
  77     while (1)
  78     {
  79         const struct mc13783_event *event, *event_last;
  80
  81         wakeup_wait(&mc13783_wake, TIMEOUT_BLOCK);
  82
  83 #ifdef PMIC_DRIVER_CLOSE
  84         if (pmic_close)
  85             break;
  86 #endif
  87
  88         mc13783_read_regset(pmic_ints_regs, pending, 2);
  89
  90         /* Only clear interrupts being dispatched */
  91         pending[0] &= pmic_int_enabled[0];
  92         pending[1] &= pmic_int_enabled[1];
  93
  94         mc13783_write_regset(pmic_ints_regs, pending, 2);
  95
  96         /* Whatever is going to be serviced in this loop has been
  97          * acknowledged. Reenable interrupt and if anything was still
  98          * pending or became pending again, another signal will be
  99          * generated. */
 100         imx31_regset32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
 101
 102         event = mc13783_event_list.events;
 103         event_last = event + mc13783_event_list.count;
 104
 105         /* .count is surely expected to be > 0 */
 106         do
 107         {
 108             enum mc13783_event_sets set = event->set;
 109             uint32_t pnd = pending[set];
 110             uint32_t mask = event->mask;
 111
 112             if (pnd & mask)
 113             {
 114                 event->callback();
 115                 pnd &= ~mask;
 116                 pending[set] = pnd;
 117             }
 118
 119             if ((pending[0] | pending[1]) == 0)
 120                 break; /* Teminate early if nothing more to service */
 121         }
 122         while (++event < event_last);
 123     }
 124
 125 #ifdef PMIC_DRIVER_CLOSE
 126     gpio_disable_event(MC13783_EVENT_ID);
 127 #endif
 128 }
 129
 130 /* GPIO interrupt handler for mc13783 */
 131 void mc13783_event(void)
 132 {
 133     /* Mask the interrupt (unmasked when PMIC thread services it). */
 134     imx31_regclr32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
 135     MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
 136     wakeup_signal(&mc13783_wake);
 137 }
 138
 139 void mc13783_init(void)
 140 {
 141     /* Serial interface must have been initialized first! */
 142     wakeup_init(&mc13783_wake);
 143
 144     /* Enable the PMIC SPI module */
 145     spi_enable_module(&mc13783_spi);
 146
 147     /* Mask any PMIC interrupts for now - modules will enable them as
 148      * required */
 149     mc13783_write(MC13783_INTERRUPT_MASK0, 0xffffff);
 150     mc13783_write(MC13783_INTERRUPT_MASK1, 0xffffff);
 151
 152     MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
 153
 154 #ifdef PMIC_DRIVER_CLOSE
 155     mc13783_thread_id =
 156 #endif
 157         create_thread(mc13783_interrupt_thread,
 158             mc13783_thread_stack, sizeof(mc13783_thread_stack), 0,
 159             mc13783_thread_name IF_PRIO(, PRIORITY_REALTIME) IF_COP(, CPU));
 160 }
 161
 162 #ifdef PMIC_DRIVER_CLOSE
 163 void mc13783_close(void)
 164 {
 165     unsigned int thread_id = mc13783_thread_id;
 166
 167     if (thread_id == 0)
 168         return;
 169
 170     mc13783_thread_id = 0;
 171
 172     pmic_close = true;
 173     wakeup_signal(&mc13783_wake);
 174     thread_wait(thread_id);
 175 }
 176 #endif /* PMIC_DRIVER_CLOSE */
 177
 178 bool mc13783_enable_event(enum mc13783_event_ids id)
 179 {
 180     const struct mc13783_event * const event =
 181         &mc13783_event_list.events[id];
 182     int set = event->set;
 183     uint32_t mask = event->mask;
 184
 185     spi_lock(&mc13783_spi);
 186
 187     pmic_int_enabled[set] |= mask;
 188     mc13783_clear(pmic_intm_regs[set], mask);
 189
 190     spi_unlock(&mc13783_spi);
 191
 192     return true;
 193 }
 194
 195 void mc13783_disable_event(enum mc13783_event_ids id)
 196 {
 197     const struct mc13783_event * const event =
 198         &mc13783_event_list.events[id];
 199     int set = event->set;
 200     uint32_t mask = event->mask;
 201
 202     spi_lock(&mc13783_spi);
 203
 204     pmic_int_enabled[set] &= ~mask;
 205     mc13783_set(pmic_intm_regs[set], mask);
 206
 207     spi_unlock(&mc13783_spi);
 208 }
 209
 210 uint32_t mc13783_set(unsigned address, uint32_t bits)
 211 {
 212     spi_lock(&mc13783_spi);
 213
 214     uint32_t data = mc13783_read(address);
 215
 216     if (data != MC13783_DATA_ERROR)
 217         mc13783_write(address, data | bits);
 218
 219     spi_unlock(&mc13783_spi);
 220
 221     return data;
 222 }
 223
 224 uint32_t mc13783_clear(unsigned address, uint32_t bits)
 225 {
 226     spi_lock(&mc13783_spi);
 227
 228     uint32_t data = mc13783_read(address);
 229
 230     if (data != MC13783_DATA_ERROR)
 231         mc13783_write(address, data & ~bits);
 232
 233     spi_unlock(&mc13783_spi);
 234
 235     return data;
 236 }
 237
 238 int mc13783_write(unsigned address, uint32_t data)
 239 {
 240     struct spi_transfer xfer;
 241     uint32_t packet;
 242
 243     if (address >= MC13783_NUM_REGS)
 244         return -1;
 245
 246     packet = (1 << 31) | (address << 25) | (data & 0xffffff);
 247     xfer.txbuf = &packet;
 248     xfer.rxbuf = &packet;
 249     xfer.count = 1;
 250
 251     if (!spi_transfer(&mc13783_spi, &xfer))
 252         return -1;
 253
 254     return 1 - xfer.count;
 255 }
 256
 257 uint32_t mc13783_write_masked(unsigned address, uint32_t data, uint32_t mask)
 258 {
 259     uint32_t old;
 260
 261     spi_lock(&mc13783_spi);
 262
 263     old = mc13783_read(address);
 264
 265     if (old != MC13783_DATA_ERROR)
 266     {
 267         data = (old & ~mask) | (data & mask);
 268
 269         if (mc13783_write(address, data) != 1)
 270             old = MC13783_DATA_ERROR;
 271     }
 272
 273     spi_unlock(&mc13783_spi);
 274
 275     return old;
 276 }
 277
 278 int mc13783_write_regset(const unsigned char *regs, const uint32_t *data,
 279                          int count)
 280 {
 281     int i;
 282     struct spi_transfer xfer;
 283     uint32_t packets[MC13783_NUM_REGS];
 284
 285     if ((unsigned)count > MC13783_NUM_REGS)
 286         return -1;
 287
 288     for (i = 0; i < count; i++)
 289     {
 290         uint32_t reg = regs[i];
 291
 292         if (reg >= MC13783_NUM_REGS)
 293             return -1;
 294
 295         packets[i] = (1 << 31) | (reg << 25) | (data[i] & 0xffffff);
 296     }
 297
 298     xfer.txbuf = packets;
 299     xfer.rxbuf = packets;
 300     xfer.count = count;
 301
 302     if (!spi_transfer(&mc13783_spi, &xfer))
 303         return -1;
 304
 305     return count - xfer.count;
 306 }
 307
 308 uint32_t mc13783_read(unsigned address)
 309 {
 310     uint32_t packet;
 311     struct spi_transfer xfer;
 312
 313     if (address >= MC13783_NUM_REGS)
 314         return MC13783_DATA_ERROR;
 315
 316     packet = address << 25;
 317
 318     xfer.txbuf = &packet;
 319     xfer.rxbuf = &packet;
 320     xfer.count = 1;
 321
 322     if (!spi_transfer(&mc13783_spi, &xfer))
 323         return MC13783_DATA_ERROR;
 324
 325     return packet;
 326 }
 327
 328 int mc13783_read_regset(const unsigned char *regs, uint32_t *buffer,
 329                         int count)
 330 {
 331     int i;
 332     struct spi_transfer xfer;
 333
 334     if ((unsigned)count > MC13783_NUM_REGS)
 335         return -1;
 336
 337     for (i = 0; i < count; i++)
 338     {
 339         unsigned reg = regs[i];
 340
 341         if (reg >= MC13783_NUM_REGS)
 342             return -1;
 343
 344         buffer[i] = reg << 25;
 345     }
 346
 347     xfer.txbuf = buffer;
 348     xfer.rxbuf = buffer;
 349     xfer.count = count;
 350
 351     if (!spi_transfer(&mc13783_spi, &xfer))
 352         return -1;
 353
 354     return count - xfer.count;
 355 }