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FS#8961 - Anti-Aliased Fonts.
[kugel-rb.git] / firmware / target / mips / ingenic_jz47xx / system-jz4740.c
blobc5f99aba230b9311a4cf4e89ed632ed6abc1892e
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Maurus Cuelenaere
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22 #include "config.h"
23 #include "jz4740.h"
24 #include "mips.h"
25 #include "mmu-mips.h"
26 #include "panic.h"
27 #include "system.h"
28 #include "kernel.h"
29
30 #define EXTENDED_EXCEPTION_DESC 0
31 #if EXTENDED_EXCEPTION_DESC
32 #include "backlight-target.h"
33 #include "font.h"
34 #include "lcd.h"
35 #include "sprintf.h"
36 #endif
37
38 #define NUM_DMA 6
39 #define NUM_GPIO 128
40 #define IRQ_MAX (IRQ_GPIO_0 + NUM_GPIO)
41
42 static int irq;
43 static void UIRQ(void)
44 {
45 panicf("Unhandled interrupt occurred: %d", irq);
46 }
47
48 #define intr(name) extern __attribute__((weak,alias("UIRQ"))) void name (void)
49
50 intr(I2C);intr(EMC);intr(UHC);intr(UART0);intr(SADC);intr(MSC);intr(RTC);
51 intr(SSI);intr(CIM);intr(AIC);intr(ETH);intr(TCU2);intr(TCU1);intr(TCU0);
52 intr(UDC);intr(IPU);intr(LCD);
53
54 intr(DMA0);intr(DMA1);intr(DMA2);intr(DMA3);intr(DMA4);intr(DMA5);
55
56 intr(GPIO0);intr(GPIO1);intr(GPIO2);intr(GPIO3);intr(GPIO4);intr(GPIO5);
57 intr(GPIO6);intr(GPIO7);intr(GPIO8);intr(GPIO9);intr(GPIO10);intr(GPIO11);
58 intr(GPIO12);intr(GPIO13);intr(GPIO14);intr(GPIO15);intr(GPIO16);intr(GPIO17);
59 intr(GPIO18);intr(GPIO19);intr(GPIO20);intr(GPIO21);intr(GPIO22);intr(GPIO23);
60 intr(GPIO24);intr(GPIO25);intr(GPIO26);intr(GPIO27);intr(GPIO28);intr(GPIO29);
61 intr(GPIO30);intr(GPIO31);intr(GPIO32);intr(GPIO33);intr(GPIO34);intr(GPIO35);
62 intr(GPIO36);intr(GPIO37);intr(GPIO38);intr(GPIO39);intr(GPIO40);intr(GPIO41);
63 intr(GPIO42);intr(GPIO43);intr(GPIO44);intr(GPIO45);intr(GPIO46);intr(GPIO47);
64 intr(GPIO48);intr(GPIO49);intr(GPIO50);intr(GPIO51);intr(GPIO52);intr(GPIO53);
65 intr(GPIO54);intr(GPIO55);intr(GPIO56);intr(GPIO57);intr(GPIO58);intr(GPIO59);
66 intr(GPIO60);intr(GPIO61);intr(GPIO62);intr(GPIO63);intr(GPIO64);intr(GPIO65);
67 intr(GPIO66);intr(GPIO67);intr(GPIO68);intr(GPIO69);intr(GPIO70);intr(GPIO71);
68 intr(GPIO72);intr(GPIO73);intr(GPIO74);intr(GPIO75);intr(GPIO76);intr(GPIO77);
69 intr(GPIO78);intr(GPIO79);intr(GPIO80);intr(GPIO81);intr(GPIO82);intr(GPIO83);
70 intr(GPIO84);intr(GPIO85);intr(GPIO86);intr(GPIO87);intr(GPIO88);intr(GPIO89);
71 intr(GPIO90);intr(GPIO91);intr(GPIO92);intr(GPIO93);intr(GPIO94);intr(GPIO95);
72 intr(GPIO96);intr(GPIO97);intr(GPIO98);intr(GPIO99);intr(GPIO100);intr(GPIO101);
73 intr(GPIO102);intr(GPIO103);intr(GPIO104);intr(GPIO105);intr(GPIO106);
74 intr(GPIO107);intr(GPIO108);intr(GPIO109);intr(GPIO110);intr(GPIO111);
75 intr(GPIO112);intr(GPIO113);intr(GPIO114);intr(GPIO115);intr(GPIO116);
76 intr(GPIO117);intr(GPIO118);intr(GPIO119);intr(GPIO120);intr(GPIO121);
77 intr(GPIO122);intr(GPIO123);intr(GPIO124);intr(GPIO125);intr(GPIO126);
78 intr(GPIO127);
79
80 static void (* const irqvector[])(void) =
81 {
82 I2C,EMC,UHC,UIRQ,UIRQ,UIRQ,UIRQ,UIRQ,
83 UART0,UIRQ,UIRQ,SADC,UIRQ,MSC,RTC,SSI,
84 CIM,AIC,ETH,UIRQ,TCU2,TCU1,TCU0,UDC,
85 UIRQ,UIRQ,UIRQ,UIRQ,IPU,LCD,UIRQ,DMA0,
86 DMA1,DMA2,DMA3,DMA4,DMA5,UIRQ,UIRQ,UIRQ,
87 UIRQ,UIRQ,UIRQ,UIRQ,UIRQ,UIRQ,UIRQ,
88 GPIO0,GPIO1,GPIO2,GPIO3,GPIO4,GPIO5,GPIO6,GPIO7,
89 GPIO8,GPIO9,GPIO10,GPIO11,GPIO12,GPIO13,GPIO14,GPIO15,
90 GPIO16,GPIO17,GPIO18,GPIO19,GPIO20,GPIO21,GPIO22,GPIO23,
91 GPIO24,GPIO25,GPIO26,GPIO27,GPIO28,GPIO29,GPIO30,GPIO31,
92 GPIO32,GPIO33,GPIO34,GPIO35,GPIO36,GPIO37,GPIO38,GPIO39,
93 GPIO40,GPIO41,GPIO42,GPIO43,GPIO44,GPIO45,GPIO46,GPIO47,
94 GPIO48,GPIO49,GPIO50,GPIO51,GPIO52,GPIO53,GPIO54,GPIO55,
95 GPIO56,GPIO57,GPIO58,GPIO59,GPIO60,GPIO61,GPIO62,GPIO63,
96 GPIO64,GPIO65,GPIO66,GPIO67,GPIO68,GPIO69,GPIO70,GPIO71,
97 GPIO72,GPIO73,GPIO74,GPIO75,GPIO76,GPIO77,GPIO78,GPIO79,
98 GPIO80,GPIO81,GPIO82,GPIO83,GPIO84,GPIO85,GPIO86,GPIO87,
99 GPIO88,GPIO89,GPIO90,GPIO91,GPIO92,GPIO93,GPIO94,GPIO95,
100 GPIO96,GPIO97,GPIO98,GPIO99,GPIO100,GPIO101,GPIO102,GPIO103,
101 GPIO104,GPIO105,GPIO106,GPIO107,GPIO108,GPIO109,GPIO110,GPIO111,
102 GPIO112,GPIO113,GPIO114,GPIO115,GPIO116,GPIO117,GPIO118,GPIO119,
103 GPIO120,GPIO121,GPIO122,GPIO123,GPIO124,GPIO125,GPIO126,GPIO127
104 };
105
106 static unsigned int dma_irq_mask = 0;
107 static unsigned int gpio_irq_mask[4] = {0};
108
109 void system_enable_irq(unsigned int irq)
110 {
111 register unsigned int t;
112 if ((irq >= IRQ_GPIO_0) && (irq <= IRQ_GPIO_0 + NUM_GPIO))
113 {
114 __gpio_unmask_irq(irq - IRQ_GPIO_0);
115 t = (irq - IRQ_GPIO_0) >> 5;
116 gpio_irq_mask[t] |= (1 << ((irq - IRQ_GPIO_0) & 0x1f));
117 __intc_unmask_irq(IRQ_GPIO0 - t);
118 }
119 else if ((irq >= IRQ_DMA_0) && (irq <= IRQ_DMA_0 + NUM_DMA))
120 {
121 __dmac_channel_enable_irq(irq - IRQ_DMA_0);
122 dma_irq_mask |= (1 << (irq - IRQ_DMA_0));
123 __intc_unmask_irq(IRQ_DMAC);
124 }
125 else if (irq < 32)
126 __intc_unmask_irq(irq);
127 }
128
129 static void dis_irq(unsigned int irq)
130 {
131 register unsigned int t;
132 if ((irq >= IRQ_GPIO_0) && (irq <= IRQ_GPIO_0 + NUM_GPIO))
133 {
134 __gpio_mask_irq(irq - IRQ_GPIO_0);
135 t = (irq - IRQ_GPIO_0) >> 5;
136 gpio_irq_mask[t] &= ~(1 << ((irq - IRQ_GPIO_0) & 0x1f));
137 if (!gpio_irq_mask[t])
138 __intc_mask_irq(IRQ_GPIO0 - t);
139 }
140 else if ((irq >= IRQ_DMA_0) && (irq <= IRQ_DMA_0 + NUM_DMA))
141 {
142 __dmac_channel_disable_irq(irq - IRQ_DMA_0);
143 dma_irq_mask &= ~(1 << (irq - IRQ_DMA_0));
144 if (!dma_irq_mask)
145 __intc_mask_irq(IRQ_DMAC);
146 }
147 else if (irq < 32)
148 __intc_mask_irq(irq);
149 }
150
151 static void ack_irq(unsigned int irq)
152 {
153 if ((irq >= IRQ_GPIO_0) && (irq <= IRQ_GPIO_0 + NUM_GPIO))
154 {
155 __intc_ack_irq(IRQ_GPIO0 - ((irq - IRQ_GPIO_0)>>5));
156 __gpio_ack_irq(irq - IRQ_GPIO_0);
157 }
158 else if ((irq >= IRQ_DMA_0) && (irq <= IRQ_DMA_0 + NUM_DMA))
159 __intc_ack_irq(IRQ_DMAC);
160 else if (irq < 32)
161 __intc_ack_irq(irq);
162 }
163
164 static int get_irq_number(void)
165 {
166 static unsigned long ipl;
167 register int irq;
168
169 ipl |= REG_INTC_IPR;
170
171 if (UNLIKELY(ipl == 0))
172 return -1;
173
174 __asm__ __volatile__("negu $8, %0 \n"
175 "and $8, %0, $8 \n"
176 "clz %0, %1 \n"
177 "li $8, 31 \n"
178 "subu %0, $8, %0 \n"
179 : "=r" (irq)
180 : "r" (ipl)
181 : "t0"
182 );
183
184 if (UNLIKELY(irq < 0))
185 return -1;
186
187 ipl &= ~(1 << irq);
188
189 switch (irq)
190 {
191 case IRQ_GPIO0:
192 irq = __gpio_group_irq(0) + IRQ_GPIO_0;
193 break;
194 case IRQ_GPIO1:
195 irq = __gpio_group_irq(1) + IRQ_GPIO_0 + 32;
196 break;
197 case IRQ_GPIO2:
198 irq = __gpio_group_irq(2) + IRQ_GPIO_0 + 64;
199 break;
200 case IRQ_GPIO3:
201 irq = __gpio_group_irq(3) + IRQ_GPIO_0 + 96;
202 break;
203 case IRQ_DMAC:
204 irq = __dmac_get_irq() + IRQ_DMA_0;
205 break;
206 }
207
208 return irq;
209 }
210
211 void intr_handler(void)
212 {
213 register int irq = get_irq_number();
214 if(UNLIKELY(irq < 0))
215 return;
216
217 ack_irq(irq);
218 if(LIKELY(irq > 0))
219 irqvector[irq-1]();
220 }
221
222 #define EXC(x,y) case (x): return (y);
223 static char* parse_exception(unsigned int cause)
224 {
225 switch(cause & M_CauseExcCode)
226 {
227 EXC(EXC_INT, "Interrupt");
228 EXC(EXC_MOD, "TLB Modified");
229 EXC(EXC_TLBL, "TLB Exception (Load or Ifetch)");
230 EXC(EXC_ADEL, "Address Error (Load or Ifetch)");
231 EXC(EXC_ADES, "Address Error (Store)");
232 EXC(EXC_TLBS, "TLB Exception (Store)");
233 EXC(EXC_IBE, "Instruction Bus Error");
234 EXC(EXC_DBE, "Data Bus Error");
235 EXC(EXC_SYS, "Syscall");
236 EXC(EXC_BP, "Breakpoint");
237 EXC(EXC_RI, "Reserved Instruction");
238 EXC(EXC_CPU, "Coprocessor Unusable");
239 EXC(EXC_OV, "Overflow");
240 EXC(EXC_TR, "Trap Instruction");
241 EXC(EXC_FPE, "Floating Point Exception");
242 EXC(EXC_C2E, "COP2 Exception");
243 EXC(EXC_MDMX, "MDMX Exception");
244 EXC(EXC_WATCH, "Watch Exception");
245 EXC(EXC_MCHECK, "Machine Check Exception");
246 EXC(EXC_CacheErr, "Cache error caused re-entry to Debug Mode");
247 default:
248 return NULL;
249 }
250 }
251
252 void exception_handler(void* stack_ptr, unsigned int cause, unsigned int epc)
253 {
254 #if EXTENDED_EXCEPTION_DESC
255 (void)epc;
256
257 /* Depends on crt0.S ! */
258 char buffer[LCD_WIDTH/SYSFONT_WIDTH];
259 char *registers[] = { "ra", "fp", "gp", "t9", "t8", "s7", "s6", "s5", "s4",
260 "s3", "s2", "s1", "s0", "t7", "t6", "t5", "t4", "t3",
261 "t2", "t1", "t0", "a3", "a2", "a1", "a0", "v1", "v0",
262 "$1", "LO", "HI", "STATUS", "EPC" };
263 int i;
264
265 lcd_set_backdrop(NULL);
266 lcd_clear_display();
267 lcd_setfont(FONT_SYSFIXED);
268 _backlight_on();
269
270 snprintf(buffer, sizeof(buffer), "0x%08x at 0x%08x", read_c0_badvaddr(), epc);
271 lcd_puts(0, 0, parse_exception(cause));
272 lcd_puts(0, 1, buffer);
273 for(i=0; i< 0x80/4; i+=2)
274 {
275 unsigned int* ptr = (unsigned int*)(stack_ptr + i*4);
276 snprintf(buffer, sizeof(buffer), "%s: 0x%08x %s: 0x%08x", registers[i], *ptr, registers[i+1], *(ptr+1));
277 lcd_puts(0, 3 + i/2, buffer);
278 }
279 lcd_update();
280
281 system_exception_wait();
282 #else
283 panicf("Exception occurred: %s [0x%08x] at 0x%08x (stack at 0x%08x)", parse_exception(cause), read_c0_badvaddr(), epc, (unsigned int)stack_ptr);
284 #endif
285 }
286
287 void tlb_refill_handler(void)
288 {
289 panicf("TLB refill handler at 0x%08lx! [0x%x]", read_c0_epc(), read_c0_badvaddr());
290 }
291
292 void udelay(unsigned int usec)
293 {
294 unsigned int i = usec * (__cpm_get_cclk() / 2000000);
295 __asm__ __volatile__ (
296 ".set noreorder \n"
297 "1: \n"
298 "bne %0, $0, 1b \n"
299 "addi %0, %0, -1 \n"
300 ".set reorder \n"
301 : "=r" (i)
302 : "0" (i)
303 );
304 }
305
306 void mdelay(unsigned int msec)
307 {
308 unsigned int i;
309 for(i=0; i<msec; i++)
310 udelay(1000);
311 }
312
313 static int dma_count = 0;
314 void dma_enable(void)
315 {
316 if(++dma_count == 1)
317 {
318 __cpm_start_dmac();
319
320 REG_DMAC_DCCSR(0) = 0;
321 REG_DMAC_DCCSR(1) = 0;
322 REG_DMAC_DCCSR(2) = 0;
323 REG_DMAC_DCCSR(3) = 0;
324 REG_DMAC_DCCSR(4) = 0;
325 REG_DMAC_DCCSR(5) = 0;
326
327 REG_DMAC_DMACR = (DMAC_DMACR_PR_RR | DMAC_DMACR_DMAE);
328 }
329 }
330
331 void dma_disable(void)
332 {
333 if(--dma_count == 0)
334 {
335 REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE;
336 __cpm_stop_dmac();
337 }
338 }
339
340 /* PLL output clock = EXTAL * NF / (NR * NO)
341 *
342 * NF = FD + 2, NR = RD + 2
343 * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
344 */
345 static void pll_init(void) ICODE_ATTR;
346 static void pll_init(void)
347 {
348 register unsigned int cfcr, plcr1;
349 int n2FR[33] = {
350 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
351 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
352 9
353 };
354 int div[5] = {0, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
355 int nf, pllout2;
356
357 cfcr = CPM_CPCCR_CLKOEN |
358 CPM_CPCCR_PCS |
359 (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
360 (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
361 (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
362 (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
363 (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT) |
364 CPM_CPCCR_CE; /* Perform clock divisions immediately */
365
366 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CPU_FREQ : (CPU_FREQ / 2);
367
368 /* Init USB Host clock, pllout2 must be n*48MHz */
369 REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
370
371 nf = CPU_FREQ * 2 / CFG_EXTAL;
372 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
373 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
374 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
375 (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
376 CPM_CPPCR_PLLEN; /* enable PLL */
377
378 /* init PLL */
379 REG_CPM_CPCCR = cfcr;
380 REG_CPM_CPPCR = plcr1;
381 }
382
383 // SDRAM paramters
384 #define CFG_SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
385 #define CFG_SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
386 #define CFG_SDRAM_ROW 12 /* Row address: 11 to 13 */
387 #define CFG_SDRAM_COL 8 /* Column address: 8 to 12 */
388 #define CFG_SDRAM_CASL 2 /* CAS latency: 2 or 3 */
389
390 // SDRAM Timings, unit: ns
391 #define CFG_SDRAM_TRAS 45 /* RAS# Active Time */
392 #define CFG_SDRAM_RCD 20 /* RAS# to CAS# Delay */
393 #define CFG_SDRAM_TPC 20 /* RAS# Precharge Time */
394 #define CFG_SDRAM_TRWL 7 /* Write Latency Time */
395 #define CFG_SDRAM_TREF 7812 /* Refresh period: 8192 refresh cycles/64ms */
396
397 /*
398 * Init SDRAM memory.
399 */
400 static void sdram_init(void) ICODE_ATTR;
401 static void sdram_init(void)
402 {
403 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
404
405 unsigned int cas_latency_sdmr[2] = {
406 EMC_SDMR_CAS_2,
407 EMC_SDMR_CAS_3,
408 };
409
410 unsigned int cas_latency_dmcr[2] = {
411 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
412 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
413 };
414
415 int div[] = { 1, 2, 3, 4, 6, 8, 12, 16, 24, 32 };
416
417 cpu_clk = CPU_FREQ;
418 mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
419
420 //REG_EMC_BCR = 0; /* Disable bus release */
421 REG_EMC_RTCSR = 0; /* Disable clock for counting */
422 REG_EMC_RTCOR = 0;
423 REG_EMC_RTCNT = 0;
424
425 /* Fault DMCR value for mode register setting */
426 #define SDRAM_ROW0 11
427 #define SDRAM_COL0 8
428 #define SDRAM_BANK40 0
429
430 dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
431 ((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
432 (SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
433 (CFG_SDRAM_BW16 << EMC_DMCR_BW_BIT) |
434 EMC_DMCR_EPIN | cas_latency_dmcr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
435
436 /* Basic DMCR value */
437 dmcr = ((CFG_SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
438 ((CFG_SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
439 (CFG_SDRAM_BANK4 << EMC_DMCR_BA_BIT) |
440 (CFG_SDRAM_BW16 << EMC_DMCR_BW_BIT) |
441 EMC_DMCR_EPIN | cas_latency_dmcr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
442
443 /* SDRAM timimg */
444 ns = 1000000000 / mem_clk;
445 tmp = CFG_SDRAM_TRAS / ns;
446 if (tmp < 4)
447 tmp = 4;
448 if (tmp > 11)
449 tmp = 11;
450 dmcr |= ((tmp - 4) << EMC_DMCR_TRAS_BIT);
451 tmp = CFG_SDRAM_RCD / ns;
452 if (tmp > 3)
453 tmp = 3;
454 dmcr |= (tmp << EMC_DMCR_RCD_BIT);
455 tmp = CFG_SDRAM_TPC / ns;
456 if (tmp > 7)
457 tmp = 7;
458 dmcr |= (tmp << EMC_DMCR_TPC_BIT);
459 tmp = CFG_SDRAM_TRWL / ns;
460 if (tmp > 3)
461 tmp = 3;
462 dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
463 tmp = (CFG_SDRAM_TRAS + CFG_SDRAM_TPC) / ns;
464 if (tmp > 14)
465 tmp = 14;
466 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
467
468 /* SDRAM mode value */
469 sdmode = EMC_SDMR_BT_SEQ |
470 EMC_SDMR_OM_NORMAL |
471 EMC_SDMR_BL_4 | cas_latency_sdmr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
472
473 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
474 REG_EMC_DMCR = dmcr;
475 REG8(EMC_SDMR0 | sdmode) = 0;
476
477 /* Wait for precharge, > 200us */
478 tmp = (cpu_clk / 1000000) * 1000;
479 while (tmp--);
480
481 /* Stage 2. Enable auto-refresh */
482 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
483
484 tmp = CFG_SDRAM_TREF / ns;
485 tmp = tmp / 64 + 1;
486 if (tmp > 0xff)
487 tmp = 0xff;
488 REG_EMC_RTCOR = tmp;
489 REG_EMC_RTCNT = 0;
490 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
491
492 /* Wait for number of auto-refresh cycles */
493 tmp = (cpu_clk / 1000000) * 1000;
494 while (tmp--);
495
496 /* Stage 3. Mode Register Set */
497 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
498 REG8(EMC_SDMR0 | sdmode) = 0;
499
500 /* Set back to basic DMCR value */
501 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
502
503 /* everything is ok now */
504 }
505
506 /* Gets called *before* main */
507 void ICODE_ATTR system_main(void)
508 {
509 int i;
510
511 __dcache_writeback_all();
512 __icache_invalidate_all();
513
514 write_c0_status(1 << 28 | 1 << 10 ); /* Enable CP | Mask interrupt 2 */
515
516 /* Disable all interrupts */
517 for(i=0; i<IRQ_MAX; i++)
518 dis_irq(i);
519
520 mmu_init();
521 pll_init();
522 sdram_init();
523
524 /* Disable unneeded clocks, clocks are enabled when needed */
525 __cpm_stop_all();
526 __cpm_suspend_usbhost();
527
528 /* Enable interrupts at core level */
529 enable_interrupt();
530 }
531
532 void system_reboot(void)
533 {
534 REG_WDT_TCSR = WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN;
535 REG_WDT_TCNT = 0;
536 REG_WDT_TDR = JZ_EXTAL/1000; /* reset after 4ms */
537 REG_TCU_TSCR = TCU_TSSR_WDTSC; /* enable wdt clock */
538 REG_WDT_TCER = WDT_TCER_TCEN; /* wdt start */
539
540 while (1);
541 }
542
543 void system_exception_wait(void)
544 {
545 /* check for power button without including any .h file */
546 while(1)
547 {
548 if( (~REG_GPIO_PXPIN(3)) & (1 << 29) )
549 return;
550 asm volatile("nop");
551 }
552 }
553
554 void power_off(void)
555 {
556 /* Enable RTC clock */
557 __cpm_start_rtc();
558
559 /* Put system into hibernate mode */
560 __rtc_clear_alarm_flag();
561 __rtc_clear_hib_stat_all();
562 /* __rtc_set_scratch_pattern(0x12345678); */
563 __rtc_enable_alarm_wakeup();
564 __rtc_set_hrcr_val(0xFE0);
565 __rtc_set_hwfcr_val(0xFFFF << 4);
566 __rtc_power_down();
567
568 while(1);
569 }
570
571 void system_init(void)
572 {
573 }
574
575 int system_memory_guard(int newmode)
576 {
577 (void)newmode;
578 return 0;
579 }
580
581 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
582 void set_cpu_frequency(long frequency)
583 {
584 unsigned long cfcr = REG_CPM_CPCCR;
585 cfcr &= ~CPM_CPCCR_CDIV_MASK;
586
587 if(frequency == CPUFREQ_NORMAL)
588 cfcr |= (0 << CPM_CPCCR_CDIV_BIT);
589 else
590 cfcr |= (2 << CPM_CPCCR_CDIV_BIT);
591
592 REG_CPM_CPCCR = cfcr;
593 cpu_frequency = frequency;
594 }
595 #endif
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