firmware/target/arm/pcm-pp.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 by Michael Sevakis
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include <stdlib.h>
  22 #include "system.h"
  23 #include "kernel.h"
  24 #include "logf.h"
  25 #include "audio.h"
  26 #include "sound.h"
  27 #include "pcm.h"
  28
  29 #ifdef HAVE_WM8751
  30 #define MROBE100_44100HZ     (0x40|(0x11 << 1)|1)
  31 #endif
  32
  33 /** DMA **/
  34
  35 #ifdef CPU_PP502x
  36 /* 16-bit, L-R packed into 32 bits with left in the least significant halfword */
  37 #define SAMPLE_SIZE   16
  38 #else
  39 /* 32-bit, one left 32-bit sample followed by one right 32-bit sample */
  40 #define SAMPLE_SIZE   32
  41 #endif
  42
  43 struct dma_data
  44 {
  45 /* NOTE: The order of size and p is important if you use assembler
  46    optimised fiq handler, so don't change it. */
  47 #if SAMPLE_SIZE == 16
  48     uint32_t *p;
  49 #elif SAMPLE_SIZE == 32
  50     uint16_t *p;
  51 #endif
  52     size_t size;
  53 #if NUM_CORES > 1
  54     unsigned core;
  55 #endif
  56     int locked;
  57     int state;
  58 };
  59
  60 extern void *fiq_function;
  61
  62 /* Dispatch to the proper handler and leave the main vector table alone */
  63 void fiq_handler(void) ICODE_ATTR __attribute__((naked));
  64 void fiq_handler(void)
  65 {
  66     asm volatile (
  67         "ldr pc, [pc, #-4] \n"
  68     "fiq_function:         \n"
  69         ".word 0           \n"
  70     );
  71 }
  72
  73 /* TODO: Get simultaneous recording and playback to work. Just needs some tweaking */
  74
  75 /****************************************************************************
  76  ** Playback DMA transfer
  77  **/
  78 struct dma_data dma_play_data SHAREDBSS_ATTR =
  79 {
  80     /* Initialize to a locked, stopped state */
  81     .p = NULL,
  82     .size = 0,
  83 #if NUM_CORES > 1
  84     .core = 0x00,
  85 #endif
  86     .locked = 0,
  87     .state = 0
  88 };
  89
  90 static unsigned long pcm_freq SHAREDDATA_ATTR = HW_SAMPR_DEFAULT; /* 44.1 is default */
  91 #ifdef HAVE_WM8751
  92 /* Samplerate control for audio codec */
  93 static int sr_ctrl = MROBE100_44100HZ;
  94 #endif
  95
  96 void pcm_set_frequency(unsigned int frequency)
  97 {
  98 #if defined(HAVE_WM8731) || defined(HAVE_WM8721)
  99     pcm_freq = frequency;
 100 #else
 101     (void)frequency;
 102     pcm_freq = HW_SAMPR_DEFAULT;
 103 #endif
 104 #ifdef HAVE_WM8751
 105     sr_ctrl  = MROBE100_44100HZ;
 106 #endif
 107 }
 108
 109 void pcm_apply_settings(void)
 110 {
 111 #ifdef HAVE_WM8751
 112     audiohw_set_frequency(sr_ctrl);
 113 #endif
 114
 115 #if defined(HAVE_WM8731) || defined(HAVE_WM8721)
 116     audiohw_set_sample_rate(pcm_freq);
 117 #endif
 118     pcm_curr_sampr = pcm_freq;
 119 }
 120
 121 /* ASM optimised FIQ handler. Checks for the minimum allowed loop cycles by
 122  * evalutation of free IISFIFO-slots against available source buffer words.
 123  * Through this it is possible to move the check for IIS_TX_FREE_COUNT outside
 124  * the loop and do some further optimization. Right after the loops (source
 125  * buffer -> IISFIFO) are done we need to check whether we have to exit FIQ
 126  * handler (this must be done, if all free FIFO slots were filled) or we will
 127  * have to get some new source data. Important information kept from former
 128  * ASM implementation (not used anymore): GCC fails to make use of the fact
 129  * that FIQ mode has registers r8-r14 banked, and so does not need to be saved.
 130  * This routine uses only these registers, and so will never touch the stack
 131  * unless it actually needs to do so when calling pcm_callback_for_more.
 132  * C version is still included below for reference and testing.
 133  */
 134 #if 1
 135 void fiq_playback(void) ICODE_ATTR __attribute__((naked));
 136 void fiq_playback(void)
 137 {
 138     /* r10 contains IISCONFIG address (set in crt0.S to minimise code in actual
 139      * FIQ handler. r11 contains address of p (also set in crt0.S). Most other
 140      * addresses we need are generated by using offsets with these two.
 141      * r10 + 0x40 is IISFIFO_WR, and r10 + 0x0c is IISFIFO_CFG.
 142      * r8 and r9 contains local copies of p and size respectively.
 143      * r0-r3 and r12 is a working register.
 144      */
 145     asm volatile (
 146         "stmfd   sp!, { r0-r3, lr }  \n" /* stack scratch regs and lr */
 147
 148 #if CONFIG_CPU == PP5002
 149         "ldr     r12, =0xcf001040    \n" /* Some magic from iPodLinux */
 150         "ldr     r12, [r12]          \n"
 151 #endif
 152         "ldmia   r11, { r8-r9 }      \n" /* r8 = p, r9 = size */
 153         "cmp     r9, #0              \n" /* is size 0? */
 154         "beq     .more_data          \n" /* if so, ask pcmbuf for more data */
 155
 156 #if SAMPLE_SIZE == 16
 157     ".check_fifo:                    \n"
 158         "ldr     r0, [r10, %[cfg]]   \n" /* read IISFIFO_CFG to check FIFO status */
 159         "and     r0, r0, %[mask]     \n" /* r0 = IIS_TX_FREE_COUNT << 16 (PP502x) */
 160
 161         "mov     r1, r0, lsr #16     \n" /* number of free FIFO slots */
 162         "cmp     r1, r9, lsr #2      \n" /* number of words from source */
 163         "movgt   r1, r9, lsr #2      \n" /* r1 = amount of allowed loops */
 164         "sub     r9, r9, r1, lsl #2  \n" /* r1 words will be written in following loop */
 165
 166         "subs    r1, r1, #2          \n"
 167     ".fifo_loop_2:                   \n"
 168         "ldmgeia r8!, {r2, r12}      \n" /* load four samples */
 169         "strge   r2 , [r10, %[wr]]   \n" /* write sample 0-1 to IISFIFO_WR */
 170         "strge   r12, [r10, %[wr]]   \n" /* write sample 2-3 to IISFIFO_WR */
 171         "subges  r1, r1, #2          \n" /* one more loop? */
 172         "bge     .fifo_loop_2        \n" /* yes, continue */
 173
 174         "tst     r1, #1              \n" /* two samples (one word) left? */
 175         "ldrne   r12, [r8], #4       \n" /* load two samples */
 176         "strne   r12, [r10, %[wr]]   \n" /* write sample 0-1 to IISFIFO_WR */
 177
 178         "cmp     r9, #0              \n" /* either FIFO is full or source buffer is empty */
 179         "bgt     .exit               \n" /* if source buffer is not empty, FIFO must be full */
 180 #elif SAMPLE_SIZE == 32
 181     ".check_fifo:                    \n"
 182         "ldr     r0, [r10, %[cfg]]   \n" /* read IISFIFO_CFG to check FIFO status */
 183         "and     r0, r0, %[mask]     \n" /* r0 = IIS_TX_FREE_COUNT << 23 (PP5002) */
 184
 185         "movs    r1, r0, lsr #24     \n" /* number of free pairs of FIFO slots */
 186         "beq     .exit               \n" /* no complete pair? -> exit */
 187         "cmp     r1, r9, lsr #2      \n" /* number of words from source */
 188         "movgt   r1, r9, lsr #2      \n" /* r1 = amount of allowed loops */
 189         "sub     r9, r9, r1, lsl #2  \n" /* r1 words will be written in following loop */
 190
 191     ".fifo_loop:                     \n"
 192         "ldr     r12, [r8], #4       \n" /* load two samples */
 193         "mov     r2 , r12, lsl #16   \n" /* put left sample at the top bits */
 194         "str     r2 , [r10, %[wr]]   \n" /* write top sample to IISFIFO_WR */
 195         "str     r12, [r10, %[wr]]   \n" /* write low sample to IISFIFO_WR*/
 196         "subs    r1, r1, #1          \n" /* one more loop? */
 197         "bgt     .fifo_loop          \n" /* yes, continue */
 198
 199         "cmp     r9, #0              \n" /* either FIFO is full or source buffer is empty */
 200         "bgt     .exit               \n" /* if source buffer is not empty, FIFO must be full */
 201 #endif
 202
 203     ".more_data:                     \n"
 204         "ldr     r2, =pcm_callback_for_more \n"
 205         "ldr     r2, [r2]            \n" /* get callback address */
 206         "cmp     r2, #0              \n" /* check for null pointer */
 207         "stmneia r11, { r8-r9 }      \n" /* save internal copies of variables back */
 208         "movne   r0, r11             \n" /* r0 = &p */
 209         "addne   r1, r11, #4         \n" /* r1 = &size */
 210         "movne   lr, pc              \n" /* call pcm_callback_for_more */
 211         "bxne    r2                  \n"
 212         "ldmia   r11, { r8-r9 }      \n" /* reload p and size */
 213         "cmp     r9, #0              \n" /* did we actually get more data? */
 214         "bne     .check_fifo         \n"
 215         "ldr     r12, =pcm_play_dma_stop \n"
 216         "mov     lr, pc              \n"
 217         "bx      r12                 \n"
 218         "ldr     r12, =pcm_play_dma_stopped_callback \n"
 219         "mov     lr, pc              \n"
 220         "bx      r12                 \n"
 221
 222     ".exit:                          \n" /* (r8=0 if stopping, look above) */
 223         "stmia   r11, { r8-r9 }      \n" /* save p and size */
 224         "ldmfd   sp!, { r0-r3, lr }  \n"
 225         "subs    pc, lr, #4          \n" /* FIQ specific return sequence */
 226         ".ltorg                      \n"
 227         : /* These must only be integers! No regs */
 228         : [mask]"i"(IIS_TX_FREE_MASK),
 229           [cfg]"i"((int)&IISFIFO_CFG - (int)&IISCONFIG),
 230           [wr]"i"((int)&IISFIFO_WR - (int)&IISCONFIG)
 231     );
 232 }
 233 #else /* C version for reference */
 234 void fiq_playback(void) __attribute__((interrupt ("FIQ"))) ICODE_ATTR;
 235 /* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */
 236 void fiq_playback(void)
 237 {
 238     register pcm_more_callback_type get_more;
 239
 240 #if CONFIG_CPU == PP5002
 241     inl(0xcf001040);
 242 #endif
 243
 244     do {
 245         while (dma_play_data.size > 0) {
 246             if (IIS_TX_FREE_COUNT < 2) {
 247                 return;
 248             }
 249 #if SAMPLE_SIZE == 16
 250             IISFIFO_WR = *dma_play_data.p++;
 251 #elif SAMPLE_SIZE == 32
 252             IISFIFO_WR = *dma_play_data.p++ << 16;
 253             IISFIFO_WR = *dma_play_data.p++ << 16;
 254 #endif
 255             dma_play_data.size -= 4;
 256         }
 257
 258         /* p is empty, get some more data */
 259         get_more = pcm_callback_for_more;
 260         if (get_more) {
 261             get_more((unsigned char**)&dma_play_data.p,
 262                      &dma_play_data.size);
 263         }
 264     } while (dma_play_data.size);
 265
 266     /* No more data, so disable the FIFO/interrupt */
 267     pcm_play_dma_stop();
 268     pcm_play_dma_stopped_callback();
 269 }
 270 #endif /* ASM / C selection */
 271
 272 /* For the locks, FIQ must be disabled because the handler manipulates
 273    IISCONFIG and the operation is not atomic - dual core support
 274    will require other measures */
 275 void pcm_play_lock(void)
 276 {
 277     int status = disable_fiq_save();
 278
 279     if (++dma_play_data.locked == 1) {
 280         IIS_IRQTX_REG &= ~IIS_IRQTX;
 281     }
 282
 283     restore_fiq(status);
 284 }
 285
 286 void pcm_play_unlock(void)
 287 {
 288    int status = disable_fiq_save();
 289
 290     if (--dma_play_data.locked == 0 && dma_play_data.state != 0) {
 291         IIS_IRQTX_REG |= IIS_IRQTX;
 292     }
 293
 294    restore_fiq(status);
 295 }
 296
 297 static void play_start_pcm(void)
 298 {
 299     fiq_function = fiq_playback;
 300     pcm_apply_settings();
 301
 302     IISCONFIG &= ~IIS_TXFIFOEN;  /* Stop transmitting */
 303     dma_play_data.state = 1;
 304
 305     /* Fill the FIFO or start when data is used up */
 306     while (1) {
 307         if (IIS_TX_FREE_COUNT < 2 || dma_play_data.size == 0) {
 308             IISCONFIG |= IIS_TXFIFOEN; /* Start transmitting */
 309             return;
 310         }
 311
 312 #if SAMPLE_SIZE == 16
 313         IISFIFO_WR = *dma_play_data.p++;
 314 #elif SAMPLE_SIZE == 32
 315         IISFIFO_WR = *dma_play_data.p++ << 16;
 316         IISFIFO_WR = *dma_play_data.p++ << 16;
 317 #endif
 318         dma_play_data.size -= 4;
 319     }
 320 }
 321
 322 static void play_stop_pcm(void)
 323 {
 324     /* Disable TX interrupt */
 325     IIS_IRQTX_REG &= ~IIS_IRQTX;
 326     dma_play_data.state = 0;
 327 }
 328
 329 void pcm_play_dma_start(const void *addr, size_t size)
 330 {
 331     dma_play_data.p    = (void *)(((uintptr_t)addr + 2) & ~3);
 332     dma_play_data.size = (size & ~3);
 333
 334 #if NUM_CORES > 1
 335     /* This will become more important later - and different ! */
 336     dma_play_data.core = processor_id(); /* save initiating core */
 337 #endif
 338
 339     CPU_INT_PRIORITY |= IIS_MASK;   /* FIQ priority for I2S */
 340     CPU_INT_EN = IIS_MASK;
 341
 342     play_start_pcm();
 343 }
 344
 345 /* Stops the DMA transfer and interrupt */
 346 void pcm_play_dma_stop(void)
 347 {
 348     play_stop_pcm();
 349     dma_play_data.size = 0;
 350 #if NUM_CORES > 1
 351     dma_play_data.core = 0; /* no core in control */
 352 #endif
 353 }
 354
 355 void pcm_play_dma_pause(bool pause)
 356 {
 357     if (pause) {
 358         play_stop_pcm();
 359     } else {
 360         play_start_pcm();
 361     }
 362 }
 363
 364 size_t pcm_get_bytes_waiting(void)
 365 {
 366     return dma_play_data.size & ~3;
 367 }
 368
 369 void pcm_play_dma_init(void)
 370 {
 371     pcm_set_frequency(SAMPR_44);
 372
 373     /* Initialize default register values. */
 374     audiohw_init();
 375
 376     dma_play_data.size = 0;
 377 #if NUM_CORES > 1
 378     dma_play_data.core = 0; /* no core in control */
 379 #endif
 380
 381     IISCONFIG |= IIS_TXFIFOEN;
 382 }
 383
 384 void pcm_postinit(void)
 385 {
 386     audiohw_postinit();
 387     pcm_apply_settings();
 388 }
 389
 390 const void * pcm_play_dma_get_peak_buffer(int *count)
 391 {
 392     unsigned long addr = (unsigned long)dma_play_data.p;
 393     size_t cnt = dma_play_data.size;
 394     *count = cnt >> 2;
 395     return (void *)((addr + 2) & ~3);
 396 }
 397
 398 /****************************************************************************
 399  ** Recording DMA transfer
 400  **/
 401 #ifdef HAVE_RECORDING
 402 /* PCM recording interrupt routine lockout */
 403 static struct dma_data dma_rec_data SHAREDBSS_ATTR =
 404 {
 405     /* Initialize to a locked, stopped state */
 406     .p = NULL,
 407     .size = 0,
 408 #if NUM_CORES > 1
 409     .core = 0x00,
 410 #endif
 411     .locked = 0,
 412     .state  = 0
 413 };
 414
 415 /* For the locks, FIQ must be disabled because the handler manipulates
 416    IISCONFIG and the operation is not atomic - dual core support
 417    will require other measures */
 418 void pcm_rec_lock(void)
 419 {
 420     int status = disable_fiq_save();
 421
 422     if (++dma_rec_data.locked == 1)
 423         IIS_IRQRX_REG &= ~IIS_IRQRX;
 424
 425     restore_fiq(status);
 426 }
 427
 428 void pcm_rec_unlock(void)
 429 {
 430     int status = disable_fiq_save();
 431
 432     if (--dma_rec_data.locked == 0 && dma_rec_data.state != 0)
 433         IIS_IRQRX_REG |= IIS_IRQRX;
 434
 435     restore_fiq(status);
 436 }
 437
 438 /* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */
 439 void fiq_record(void) ICODE_ATTR __attribute__((interrupt ("FIQ")));
 440
 441 #if defined(SANSA_C200) || defined(SANSA_E200)
 442 void fiq_record(void)
 443 {
 444     register pcm_more_callback_type2 more_ready;
 445     register int32_t value;
 446
 447     if (audio_channels == 2) {
 448         /* RX is stereo */
 449         while (dma_rec_data.size > 0) {
 450             if (IIS_RX_FULL_COUNT < 2) {
 451                 return;
 452             }
 453
 454             /* Discard every other sample since ADC clock is 1/2 LRCK */
 455             value = IISFIFO_RD;
 456             IISFIFO_RD;
 457
 458             *dma_rec_data.p++ = value;
 459             dma_rec_data.size -= 4;
 460
 461             /* TODO: Figure out how to do IIS loopback */
 462             if (audio_output_source != AUDIO_SRC_PLAYBACK) {
 463                 if (IIS_TX_FREE_COUNT >= 16) {
 464                     /* Resync the output FIFO - it ran dry */
 465                     IISFIFO_WR = 0;
 466                     IISFIFO_WR = 0;
 467                 }
 468                 IISFIFO_WR = value;
 469                 IISFIFO_WR = value;
 470             }
 471         }
 472     }
 473     else {
 474         /* RX is left channel mono */
 475         while (dma_rec_data.size > 0) {
 476             if (IIS_RX_FULL_COUNT < 2) {
 477                 return;
 478             }
 479
 480             /* Discard every other sample since ADC clock is 1/2 LRCK */
 481             value = IISFIFO_RD;
 482             IISFIFO_RD;
 483
 484             value = (uint16_t)value | (value << 16);
 485
 486             *dma_rec_data.p++ = value;
 487             dma_rec_data.size -= 4;
 488
 489             if (audio_output_source != AUDIO_SRC_PLAYBACK) {
 490                 if (IIS_TX_FREE_COUNT >= 16) {
 491                     /* Resync the output FIFO - it ran dry */
 492                     IISFIFO_WR = 0;
 493                     IISFIFO_WR = 0;
 494                 }
 495
 496                 value = *((int32_t *)dma_rec_data.p - 1);
 497                 IISFIFO_WR = value;
 498                 IISFIFO_WR = value;
 499             }
 500         }
 501     }
 502
 503     more_ready = pcm_callback_more_ready;
 504
 505     if (more_ready == NULL || more_ready(0) < 0) {
 506         /* Finished recording */
 507         pcm_rec_dma_stop();
 508         pcm_rec_dma_stopped_callback();
 509     }
 510 }
 511
 512 #else
 513 void fiq_record(void)
 514 {
 515     register pcm_more_callback_type2 more_ready;
 516
 517     while (dma_rec_data.size > 0) {
 518         if (IIS_RX_FULL_COUNT < 2) {
 519             return;
 520         }
 521
 522 #if SAMPLE_SIZE == 16
 523         *dma_rec_data.p++ = IISFIFO_RD;
 524 #elif SAMPLE_SIZE == 32
 525         *dma_rec_data.p++ = IISFIFO_RD >> 16;
 526         *dma_rec_data.p++ = IISFIFO_RD >> 16;
 527 #endif
 528         dma_rec_data.size -= 4;
 529     }
 530
 531     more_ready = pcm_callback_more_ready;
 532
 533     if (more_ready == NULL || more_ready(0) < 0) {
 534         /* Finished recording */
 535         pcm_rec_dma_stop();
 536         pcm_rec_dma_stopped_callback();
 537     }
 538 }
 539
 540 #endif /* SANSA_E200 */
 541
 542 /* Continue transferring data in */
 543 void pcm_record_more(void *start, size_t size)
 544 {
 545     pcm_rec_peak_addr = start; /* Start peaking at dest */
 546     dma_rec_data.p    = start; /* Start of RX buffer    */
 547     dma_rec_data.size = size;  /* Bytes to transfer     */
 548 }
 549
 550 void pcm_rec_dma_stop(void)
 551 {
 552     /* disable interrupt */
 553     IIS_IRQRX_REG &= ~IIS_IRQRX;
 554
 555     dma_rec_data.state = 0;
 556     dma_rec_data.size = 0;
 557 #if NUM_CORES > 1
 558     dma_rec_data.core = 0x00;
 559 #endif
 560
 561     /* disable fifo */
 562     IISCONFIG &= ~IIS_RXFIFOEN;
 563     IISFIFO_CFG |= IIS_RXCLR;
 564 }
 565
 566 void pcm_rec_dma_start(void *addr, size_t size)
 567 {
 568     pcm_rec_dma_stop();
 569
 570     pcm_rec_peak_addr = addr;
 571     dma_rec_data.p    = addr;
 572     dma_rec_data.size = size;
 573 #if NUM_CORES > 1
 574     /* This will become more important later - and different ! */
 575     dma_rec_data.core = processor_id(); /* save initiating core */
 576 #endif
 577     /* setup FIQ handler */
 578     fiq_function = fiq_record;
 579
 580     /* interrupt on full fifo, enable record fifo interrupt */
 581     dma_rec_data.state = 1;
 582
 583     /* enable RX FIFO */
 584     IISCONFIG |= IIS_RXFIFOEN;
 585
 586     /* enable IIS interrupt as FIQ */
 587     CPU_INT_PRIORITY |= IIS_MASK;
 588     CPU_INT_EN = IIS_MASK;
 589 }
 590
 591 void pcm_rec_dma_close(void)
 592 {
 593     pcm_rec_dma_stop();
 594
 595 #if defined(IPOD_COLOR) || defined (IPOD_4G)
 596     /* The usual magic from IPL - I'm guessing this configures the headphone
 597        socket to be input or output - in this case, output. */
 598     GPIO_SET_BITWISE(GPIOI_OUTPUT_VAL, 0x40);
 599     GPIO_SET_BITWISE(GPIOA_OUTPUT_VAL, 0x04);
 600 #endif
 601 } /* pcm_close_recording */
 602
 603 void pcm_rec_dma_init(void)
 604 {
 605 #if defined(IPOD_COLOR) || defined (IPOD_4G)
 606     /* The usual magic from IPL - I'm guessing this configures the headphone
 607        socket to be input or output - in this case, input. */
 608     GPIO_CLEAR_BITWISE(GPIOI_OUTPUT_VAL, 0x40);
 609     GPIO_CLEAR_BITWISE(GPIOA_OUTPUT_VAL, 0x04);
 610 #endif
 611
 612     pcm_rec_dma_stop();
 613 } /* pcm_init */
 614
 615 const void * pcm_rec_dma_get_peak_buffer(int *count)
 616 {
 617     unsigned long addr = (unsigned long)pcm_rec_peak_addr;
 618     unsigned long end = (unsigned long)dma_rec_data.p;
 619     *count = (end >> 2) - (addr >> 2);
 620     return (void *)(addr & ~3);
 621 } /* pcm_rec_dma_get_peak_buffer */
 622
 623 #endif /* HAVE_RECORDING */