firmware/target/arm/imx31/gigabeat-s/system-imx31.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by James Espinoza
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "kernel.h"
  23 #include "system.h"
  24 #include "panic.h"
  25 #include "avic-imx31.h"
  26 #include "gpio-imx31.h"
  27 #include "mmu-imx31.h"
  28 #include "system-target.h"
  29 #include "lcd.h"
  30 #include "serial-imx31.h"
  31 #include "debug.h"
  32 #include "ccm-imx31.h"
  33 #include "mc13783.h"
  34 #include "dvfs_dptc-imx31.h"
  35
  36 static unsigned long product_rev;
  37 static unsigned long system_rev;
  38
  39 /** IC revision info routines **/
  40 unsigned int iim_system_rev(void)
  41 {
  42     return system_rev & IIM_SREV_SREV;
  43 }
  44
  45 unsigned int iim_prod_rev(void)
  46 {
  47     return product_rev;
  48 }
  49
  50 static void iim_init(void)
  51 {
  52     /* Initialize the IC revision info (required by SDMA) */
  53     ccm_module_clock_gating(CG_IIM, CGM_ON_RUN_WAIT);
  54     product_rev = IIM_PREV;
  55     system_rev = IIM_SREV;
  56 }
  57
  58 /** Watchdog timer routines **/
  59
  60 /* Initialize the watchdog timer */
  61 void watchdog_init(unsigned int half_seconds)
  62 {
  63     uint16_t wcr = ((half_seconds << WDOG_WCR_WT_POS) & WDOG_WCR_WT) |
  64                    WDOG_WCR_WOE |       /* WDOG output enabled */
  65                    WDOG_WCR_WDA |       /* WDOG assertion - no effect */
  66                    WDOG_WCR_SRS |       /* System reset - no effect */
  67                    WDOG_WCR_WRE;        /* Generate a WDOG signal */
  68
  69     ccm_module_clock_gating(CG_WDOG, CGM_ON_RUN_WAIT);
  70
  71     WDOG_WCR = wcr;
  72     WDOG_WSR = 0x5555;
  73     WDOG_WCR = wcr | WDOG_WCR_WDE; /* Enable timer - hardware does
  74                                       not allow a disable now */
  75     WDOG_WSR = 0xaaaa;
  76 }
  77
  78 /* Service the watchdog timer */
  79 void watchdog_service(void)
  80 {
  81     WDOG_WSR = 0x5555;
  82     WDOG_WSR = 0xaaaa;
  83 }
  84
  85 /** GPT timer routines - basis for udelay **/
  86
  87 /* Start the general-purpose timer (1MHz) */
  88 void gpt_start(void)
  89 {
  90     ccm_module_clock_gating(CG_GPT, CGM_ON_RUN_WAIT);
  91     unsigned int ipg_mhz = ccm_get_ipg_clk() / 1000000;
  92
  93     GPTCR &= ~GPTCR_EN; /* Disable counter */
  94     GPTCR |= GPTCR_SWR; /* Reset module */
  95     while (GPTCR & GPTCR_SWR);
  96     /* No output
  97      * No capture
  98      * Enable in run mode only (doesn't tick while in WFI)
  99      * Freerun mode (count to 0xFFFFFFFF and roll-over to 0x00000000)
 100      */
 101     GPTCR = GPTCR_FRR | GPTCR_CLKSRC_IPG_CLK;
 102     GPTPR = ipg_mhz - 1;
 103     GPTCR |= GPTCR_EN;
 104 }
 105
 106 /* Stop the general-purpose timer */
 107 void gpt_stop(void)
 108 {
 109     GPTCR &= ~GPTCR_EN;
 110 }
 111
 112 int system_memory_guard(int newmode)
 113 {
 114     (void)newmode;
 115     return 0;
 116 }
 117
 118 void system_reboot(void)
 119 {
 120     /* Multi-context so no SPI available (WDT?)  */
 121     while (1);
 122 }
 123
 124 void system_exception_wait(void)
 125 {
 126     /* Called in many contexts so button reading may be a chore */
 127     avic_disable_int(INT_ALL);
 128     core_idle();
 129     while (1);
 130 }
 131
 132 void system_init(void)
 133 {
 134     static const int disable_clocks[] =
 135     {
 136         /* CGR0 */
 137         CG_SD_MMC1,
 138         CG_SD_MMC2,
 139         CG_IIM,
 140         CG_SDMA,
 141         CG_CSPI3,
 142         CG_RNG,
 143         CG_UART1,
 144         CG_UART2,
 145         CG_SSI1,
 146         CG_I2C1,
 147         CG_I2C2,
 148         CG_I2C3,
 149
 150         /* CGR1 */
 151         CG_HANTRO,
 152         CG_MEMSTICK1,
 153         CG_MEMSTICK2,
 154         CG_CSI,
 155         CG_RTC,
 156         CG_WDOG,
 157         CG_PWM,
 158         CG_SIM,
 159         CG_ECT,
 160         CG_USBOTG,
 161         CG_KPP,
 162         CG_UART3,
 163         CG_UART4,
 164         CG_UART5,
 165         CG_1_WIRE,
 166
 167         /* CGR2 */
 168         CG_SSI2,
 169         CG_CSPI1,
 170         CG_CSPI2,
 171         CG_GACC,
 172         CG_RTIC,
 173         CG_FIR
 174     };
 175
 176     unsigned int i;
 177
 178     /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */
 179     imx31_regclr32(&CCM_CCMR, CCM_CCMR_LPM);
 180
 181     iim_init();
 182
 183     imx31_regset32(&SDHC1_CLOCK_CONTROL, STOP_CLK);
 184     imx31_regset32(&SDHC2_CLOCK_CONTROL, STOP_CLK);
 185     imx31_regset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP);
 186     imx31_regclr32(&UCR1_1, EUARTUCR1_UARTEN);
 187     imx31_regclr32(&UCR1_2, EUARTUCR1_UARTEN);
 188     imx31_regclr32(&UCR1_3, EUARTUCR1_UARTEN);
 189     imx31_regclr32(&UCR1_4, EUARTUCR1_UARTEN);
 190     imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN);
 191
 192     for (i = 0; i < ARRAYLEN(disable_clocks); i++)
 193         ccm_module_clock_gating(disable_clocks[i], CGM_OFF);
 194
 195     avic_init();
 196     gpt_start();
 197     gpio_init();
 198 }
 199
 200 void  __attribute__((naked)) imx31_regmod32(volatile uint32_t *reg_p,
 201                                             uint32_t value,
 202                                             uint32_t mask)
 203 {
 204     asm volatile("and    r1, r1, r2 \n"
 205                  "mrs    ip, cpsr   \n"
 206                  "cpsid  if         \n"
 207                  "ldr    r3, [r0]   \n"
 208                  "bic    r3, r3, r2 \n"
 209                  "orr    r3, r3, r1 \n"
 210                  "str    r3, [r0]   \n"
 211                  "msr    cpsr_c, ip \n"
 212                  "bx     lr         \n");
 213     (void)reg_p; (void)value; (void)mask;
 214 }
 215
 216 void __attribute__((naked)) imx31_regset32(volatile uint32_t *reg_p,
 217                                            uint32_t mask)
 218 {
 219     asm volatile("mrs    r3, cpsr   \n"
 220                  "cpsid  if         \n"
 221                  "ldr    r2, [r0]   \n"
 222                  "orr    r2, r2, r1 \n"
 223                  "str    r2, [r0]   \n"
 224                  "msr    cpsr_c, r3 \n"
 225                  "bx     lr         \n");
 226     (void)reg_p; (void)mask;
 227 }
 228
 229 void __attribute__((naked)) imx31_regclr32(volatile uint32_t *reg_p,
 230                                            uint32_t mask)
 231 {
 232     asm volatile("mrs    r3, cpsr   \n"
 233                  "cpsid  if         \n"
 234                  "ldr    r2, [r0]   \n"
 235                  "bic    r2, r2, r1 \n"
 236                  "str    r2, [r0]   \n"
 237                  "msr    cpsr_c, r3 \n"
 238                  "bx     lr         \n");
 239     (void)reg_p; (void)mask;
 240 }
 241
 242 #ifdef BOOTLOADER
 243 void system_prepare_fw_start(void)
 244 {
 245     dvfs_dptc_stop();
 246     disable_interrupt(IRQ_FIQ_STATUS);
 247     avic_disable_int(INT_ALL);
 248     mc13783_close();
 249     tick_stop();
 250 }
 251 #endif
 252
 253 inline void dumpregs(void)
 254 {
 255     asm volatile ("mov %0,r0\n\t"
 256                   "mov %1,r1\n\t"
 257                   "mov %2,r2\n\t"
 258                   "mov %3,r3":
 259                   "=r"(regs.r0),"=r"(regs.r1),
 260                   "=r"(regs.r2),"=r"(regs.r3):);
 261
 262     asm volatile ("mov %0,r4\n\t"
 263                   "mov %1,r5\n\t"
 264                   "mov %2,r6\n\t"
 265                   "mov %3,r7":
 266                   "=r"(regs.r4),"=r"(regs.r5),
 267                   "=r"(regs.r6),"=r"(regs.r7):);
 268
 269     asm volatile ("mov %0,r8\n\t"
 270                   "mov %1,r9\n\t"
 271                   "mov %2,r10\n\t"
 272                   "mov %3,r12":
 273                   "=r"(regs.r8),"=r"(regs.r9),
 274                   "=r"(regs.r10),"=r"(regs.r11):);
 275
 276     asm volatile ("mov %0,r12\n\t"
 277                    "mov %1,sp\n\t"
 278                    "mov %2,lr\n\t"
 279                    "mov %3,pc\n"
 280                    "sub %3,%3,#8":
 281                    "=r"(regs.r12),"=r"(regs.sp),
 282                    "=r"(regs.lr),"=r"(regs.pc):);
 283 #ifdef HAVE_SERIAL
 284     dprintf("Register Dump :\n");
 285     dprintf("R0=0x%x\tR1=0x%x\tR2=0x%x\tR3=0x%x\n",regs.r0,regs.r1,regs.r2,regs.r3);
 286     dprintf("R4=0x%x\tR5=0x%x\tR6=0x%x\tR7=0x%x\n",regs.r4,regs.r5,regs.r6,regs.r7);
 287     dprintf("R8=0x%x\tR9=0x%x\tR10=0x%x\tR11=0x%x\n",regs.r8,regs.r9,regs.r10,regs.r11);
 288     dprintf("R12=0x%x\tSP=0x%x\tLR=0x%x\tPC=0x%x\n",regs.r12,regs.sp,regs.lr,regs.pc);
 289     //dprintf("CPSR=0x%x\t\n",regs.cpsr);
 290 #endif
 291     DEBUGF("Register Dump :\n");
 292     DEBUGF("R0=0x%x\tR1=0x%x\tR2=0x%x\tR3=0x%x\n",regs.r0,regs.r1,regs.r2,regs.r3);
 293     DEBUGF("R4=0x%x\tR5=0x%x\tR6=0x%x\tR7=0x%x\n",regs.r4,regs.r5,regs.r6,regs.r7);
 294     DEBUGF("R8=0x%x\tR9=0x%x\tR10=0x%x\tR11=0x%x\n",regs.r8,regs.r9,regs.r10,regs.r11);
 295     DEBUGF("R12=0x%x\tSP=0x%x\tLR=0x%x\tPC=0x%x\n",regs.r12,regs.sp,regs.lr,regs.pc);
 296     //DEBUGF("CPSR=0x%x\t\n",regs.cpsr);
 297
 298  }
 299
 300 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 301
 302 void set_cpu_frequency(long frequency)
 303 {
 304     (void)freqency;
 305 }
 306
 307 #endif