firmware/target/arm/ata-target.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 by Barry Wardell
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #ifdef CPU_PP
  23
  24 /* primary channel */
  25 #define ATA_DATA        (*((volatile unsigned short*)(IDE_BASE + 0x1e0)))
  26 #define ATA_ERROR       (*((volatile unsigned char*)(IDE_BASE + 0x1e4)))
  27 #define ATA_NSECTOR     (*((volatile unsigned char*)(IDE_BASE + 0x1e8)))
  28 #define ATA_SECTOR      (*((volatile unsigned char*)(IDE_BASE + 0x1ec)))
  29 #define ATA_LCYL        (*((volatile unsigned char*)(IDE_BASE + 0x1f0)))
  30 #define ATA_HCYL        (*((volatile unsigned char*)(IDE_BASE + 0x1f4)))
  31 #define ATA_SELECT      (*((volatile unsigned char*)(IDE_BASE + 0x1f8)))
  32 #define ATA_COMMAND     (*((volatile unsigned char*)(IDE_BASE + 0x1fc)))
  33 #define ATA_CONTROL     (*((volatile unsigned char*)(IDE_BASE + 0x3f8)))
  34
  35 #define STATUS_BSY      0x80
  36 #define STATUS_RDY      0x40
  37 #define STATUS_DF       0x20
  38 #define STATUS_DRQ      0x08
  39 #define STATUS_ERR      0x01
  40 #define ERROR_ABRT      0x04
  41 #define ERROR_IDNF      0x10
  42
  43 #define WRITE_PATTERN1  0xa5
  44 #define WRITE_PATTERN2  0x5a
  45 #define WRITE_PATTERN3  0xaa
  46 #define WRITE_PATTERN4  0x55
  47
  48 #define READ_PATTERN1   0xa5
  49 #define READ_PATTERN2   0x5a
  50 #define READ_PATTERN3   0xaa
  51 #define READ_PATTERN4   0x55
  52
  53 #define READ_PATTERN1_MASK 0xff
  54 #define READ_PATTERN2_MASK 0xff
  55 #define READ_PATTERN3_MASK 0xff
  56 #define READ_PATTERN4_MASK 0xff
  57
  58 #if (CONFIG_CPU == PP5002)
  59
  60 #define SET_REG(reg,val) do { reg = (val); \
  61                               while (!(IDE_CFG_STATUS & 0x40)); \
  62                          } while (0)
  63 #define SET_16BITREG(reg,val) reg = (val)
  64
  65 /* Plain C reading and writing. See comment in ata-as-arm.S */
  66
  67 #elif defined CPU_PP502x
  68
  69 #define SET_REG(reg,val) reg = (val)
  70 #define SET_16BITREG(reg,val) reg = (val)
  71
  72 /* asm optimized reading and writing */
  73 #define ATA_OPTIMIZED_READING
  74 #define ATA_OPTIMIZED_WRITING
  75 void copy_read_sectors(unsigned char* buf, int wordcount);
  76 void copy_write_sectors(const unsigned char* buf, int wordcount);
  77
  78 #endif /* CONFIG_CPU */
  79
  80 #endif
  81
  82 void ata_reset(void);
  83 bool ata_is_coldstart(void);
  84 void ata_device_init(void);
  85
  86 #ifdef HAVE_ATA_DMA
  87
  88 /* IDE DMA controller registers */
  89 #define IDE_DMA_CONTROL (*(volatile unsigned long *)(0xc3000400))
  90 #define IDE_DMA_LENGTH  (*(volatile unsigned long *)(0xc3000408))
  91 #define IDE_DMA_ADDR    (*(volatile unsigned long *)(0xc300040C))
  92
  93 /* Maximum multi-word DMA mode supported by the controller */
  94 #define ATA_MAX_MWDMA 2
  95
  96 #ifndef BOOTLOADER
  97 /* The PP5020 supports UDMA 4, but it needs cpu boosting and only
  98  * improves performance by ~10% with a stock disk.
  99  * UDMA 2 is stable at 30 Mhz.
 100  * UDMA 1 is stable at 24 Mhz.
 101  */
 102 #if CPUFREQ_NORMAL >= 30000000
 103 #define ATA_MAX_UDMA 2
 104 #elif CPUFREQ_NORMAL >= 24000000
 105 #define ATA_MAX_UDMA 1
 106 #else
 107 #error "CPU speeds under 24Mhz have not been tested with DMA"
 108 #endif
 109 #else
 110 /* The bootloader runs at 24 Mhz and needs a slower mode */
 111 #define ATA_MAX_UDMA 1
 112 #endif
 113
 114 void ata_dma_set_mode(unsigned char mode);
 115 bool ata_dma_setup(void *addr, unsigned long bytes, bool write);
 116 bool ata_dma_finish(void);
 117
 118 #endif /* HAVE_ATA_DMA */