firmware/target/arm/usb-drv-arc.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Driver for ARC USBOTG Device Controller
  11  *
  12  * Copyright (C) 2007 by Björn Stenberg
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  20  * KIND, either express or implied.
  21  *
  22  ****************************************************************************/
  23
  24 #include "system.h"
  25 #include "config.h"
  26 #include "string.h"
  27 #include "usb_ch9.h"
  28 #include "usb_core.h"
  29 #include "kernel.h"
  30 #include "panic.h"
  31 #include "usb_drv.h"
  32
  33 //#define LOGF_ENABLE
  34 #include "logf.h"
  35
  36 /* USB device mode registers (Little Endian) */
  37
  38 #define REG_ID               (*(volatile unsigned int *)(USB_BASE+0x000))
  39 #define REG_HWGENERAL        (*(volatile unsigned int *)(USB_BASE+0x004))
  40 #define REG_HWHOST           (*(volatile unsigned int *)(USB_BASE+0x008))
  41 #define REG_HWDEVICE         (*(volatile unsigned int *)(USB_BASE+0x00c))
  42 #define REG_TXBUF            (*(volatile unsigned int *)(USB_BASE+0x010))
  43 #define REG_RXBUF            (*(volatile unsigned int *)(USB_BASE+0x014))
  44 #define REG_CAPLENGTH        (*(volatile unsigned char*)(USB_BASE+0x100))
  45 #define REG_DCIVERSION       (*(volatile unsigned int *)(USB_BASE+0x120))
  46 #define REG_DCCPARAMS        (*(volatile unsigned int *)(USB_BASE+0x124))
  47 #define REG_USBCMD           (*(volatile unsigned int *)(USB_BASE+0x140))
  48 #define REG_USBSTS           (*(volatile unsigned int *)(USB_BASE+0x144))
  49 #define REG_USBINTR          (*(volatile unsigned int *)(USB_BASE+0x148))
  50 #define REG_FRINDEX          (*(volatile unsigned int *)(USB_BASE+0x14c))
  51 #define REG_DEVICEADDR       (*(volatile unsigned int *)(USB_BASE+0x154))
  52 #define REG_ENDPOINTLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158))
  53 #define REG_BURSTSIZE        (*(volatile unsigned int *)(USB_BASE+0x160))
  54 #define REG_ULPI             (*(volatile unsigned int *)(USB_BASE+0x170))
  55 #define REG_CONFIGFLAG       (*(volatile unsigned int *)(USB_BASE+0x180))
  56 #define REG_PORTSC1          (*(volatile unsigned int *)(USB_BASE+0x184))
  57 #define REG_OTGSC            (*(volatile unsigned int *)(USB_BASE+0x1a4))
  58 #define REG_USBMODE          (*(volatile unsigned int *)(USB_BASE+0x1a8))
  59 #define REG_ENDPTSETUPSTAT   (*(volatile unsigned int *)(USB_BASE+0x1ac))
  60 #define REG_ENDPTPRIME       (*(volatile unsigned int *)(USB_BASE+0x1b0))
  61 #define REG_ENDPTFLUSH       (*(volatile unsigned int *)(USB_BASE+0x1b4))
  62 #define REG_ENDPTSTATUS      (*(volatile unsigned int *)(USB_BASE+0x1b8))
  63 #define REG_ENDPTCOMPLETE    (*(volatile unsigned int *)(USB_BASE+0x1bc))
  64 #define REG_ENDPTCTRL0       (*(volatile unsigned int *)(USB_BASE+0x1c0))
  65 #define REG_ENDPTCTRL1       (*(volatile unsigned int *)(USB_BASE+0x1c4))
  66 #define REG_ENDPTCTRL2       (*(volatile unsigned int *)(USB_BASE+0x1c8))
  67 #define REG_ENDPTCTRL(_x_)   (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(_x_)))
  68
  69 /* Frame Index Register Bit Masks */
  70 #define USB_FRINDEX_MASKS                      (0x3fff)
  71
  72 /* USB CMD  Register Bit Masks */
  73 #define USBCMD_RUN                            (0x00000001)
  74 #define USBCMD_CTRL_RESET                     (0x00000002)
  75 #define USBCMD_PERIODIC_SCHEDULE_EN           (0x00000010)
  76 #define USBCMD_ASYNC_SCHEDULE_EN              (0x00000020)
  77 #define USBCMD_INT_AA_DOORBELL                (0x00000040)
  78 #define USBCMD_ASP                            (0x00000300)
  79 #define USBCMD_ASYNC_SCH_PARK_EN              (0x00000800)
  80 #define USBCMD_SUTW                           (0x00002000)
  81 #define USBCMD_ATDTW                          (0x00004000)
  82 #define USBCMD_ITC                            (0x00FF0000)
  83
  84 /* bit 15,3,2 are frame list size */
  85 #define USBCMD_FRAME_SIZE_1024                (0x00000000)
  86 #define USBCMD_FRAME_SIZE_512                 (0x00000004)
  87 #define USBCMD_FRAME_SIZE_256                 (0x00000008)
  88 #define USBCMD_FRAME_SIZE_128                 (0x0000000C)
  89 #define USBCMD_FRAME_SIZE_64                  (0x00008000)
  90 #define USBCMD_FRAME_SIZE_32                  (0x00008004)
  91 #define USBCMD_FRAME_SIZE_16                  (0x00008008)
  92 #define USBCMD_FRAME_SIZE_8                   (0x0000800C)
  93
  94 /* bit 9-8 are async schedule park mode count */
  95 #define USBCMD_ASP_00                         (0x00000000)
  96 #define USBCMD_ASP_01                         (0x00000100)
  97 #define USBCMD_ASP_10                         (0x00000200)
  98 #define USBCMD_ASP_11                         (0x00000300)
  99 #define USBCMD_ASP_BIT_POS                    (8)
 100
 101 /* bit 23-16 are interrupt threshold control */
 102 #define USBCMD_ITC_NO_THRESHOLD               (0x00000000)
 103 #define USBCMD_ITC_1_MICRO_FRM                (0x00010000)
 104 #define USBCMD_ITC_2_MICRO_FRM                (0x00020000)
 105 #define USBCMD_ITC_4_MICRO_FRM                (0x00040000)
 106 #define USBCMD_ITC_8_MICRO_FRM                (0x00080000)
 107 #define USBCMD_ITC_16_MICRO_FRM               (0x00100000)
 108 #define USBCMD_ITC_32_MICRO_FRM               (0x00200000)
 109 #define USBCMD_ITC_64_MICRO_FRM               (0x00400000)
 110 #define USBCMD_ITC_BIT_POS                    (16)
 111
 112 /* USB STS Register Bit Masks */
 113 #define USBSTS_INT                            (0x00000001)
 114 #define USBSTS_ERR                            (0x00000002)
 115 #define USBSTS_PORT_CHANGE                    (0x00000004)
 116 #define USBSTS_FRM_LST_ROLL                   (0x00000008)
 117 #define USBSTS_SYS_ERR                        (0x00000010) /* not used */
 118 #define USBSTS_IAA                            (0x00000020)
 119 #define USBSTS_RESET                          (0x00000040)
 120 #define USBSTS_SOF                            (0x00000080)
 121 #define USBSTS_SUSPEND                        (0x00000100)
 122 #define USBSTS_HC_HALTED                      (0x00001000)
 123 #define USBSTS_RCL                            (0x00002000)
 124 #define USBSTS_PERIODIC_SCHEDULE              (0x00004000)
 125 #define USBSTS_ASYNC_SCHEDULE                 (0x00008000)
 126
 127 /* USB INTR Register Bit Masks */
 128 #define USBINTR_INT_EN                        (0x00000001)
 129 #define USBINTR_ERR_INT_EN                    (0x00000002)
 130 #define USBINTR_PTC_DETECT_EN                 (0x00000004)
 131 #define USBINTR_FRM_LST_ROLL_EN               (0x00000008)
 132 #define USBINTR_SYS_ERR_EN                    (0x00000010)
 133 #define USBINTR_ASYN_ADV_EN                   (0x00000020)
 134 #define USBINTR_RESET_EN                      (0x00000040)
 135 #define USBINTR_SOF_EN                        (0x00000080)
 136 #define USBINTR_DEVICE_SUSPEND                (0x00000100)
 137
 138 /* ULPI Register Bit Masks */
 139 #define ULPI_ULPIWU                           (0x80000000)
 140 #define ULPI_ULPIRUN                          (0x40000000)
 141 #define ULPI_ULPIRW                           (0x20000000)
 142 #define ULPI_ULPISS                           (0x08000000)
 143 #define ULPI_ULPIPORT                         (0x07000000)
 144 #define ULPI_ULPIADDR                         (0x00FF0000)
 145 #define ULPI_ULPIDATRD                        (0x0000FF00)
 146 #define ULPI_ULPIDATWR                        (0x000000FF)
 147
 148 /* Device Address bit masks */
 149 #define USBDEVICEADDRESS_MASK                 (0xFE000000)
 150 #define USBDEVICEADDRESS_BIT_POS              (25)
 151
 152 /* endpoint list address bit masks */
 153 #define USB_EP_LIST_ADDRESS_MASK               (0xfffff800)
 154
 155 /* PORTSCX  Register Bit Masks */
 156 #define PORTSCX_CURRENT_CONNECT_STATUS         (0x00000001)
 157 #define PORTSCX_CONNECT_STATUS_CHANGE          (0x00000002)
 158 #define PORTSCX_PORT_ENABLE                    (0x00000004)
 159 #define PORTSCX_PORT_EN_DIS_CHANGE             (0x00000008)
 160 #define PORTSCX_OVER_CURRENT_ACT               (0x00000010)
 161 #define PORTSCX_OVER_CURRENT_CHG               (0x00000020)
 162 #define PORTSCX_PORT_FORCE_RESUME              (0x00000040)
 163 #define PORTSCX_PORT_SUSPEND                   (0x00000080)
 164 #define PORTSCX_PORT_RESET                     (0x00000100)
 165 #define PORTSCX_LINE_STATUS_BITS               (0x00000C00)
 166 #define PORTSCX_PORT_POWER                     (0x00001000)
 167 #define PORTSCX_PORT_INDICTOR_CTRL             (0x0000C000)
 168 #define PORTSCX_PORT_TEST_CTRL                 (0x000F0000)
 169 #define PORTSCX_WAKE_ON_CONNECT_EN             (0x00100000)
 170 #define PORTSCX_WAKE_ON_CONNECT_DIS            (0x00200000)
 171 #define PORTSCX_WAKE_ON_OVER_CURRENT           (0x00400000)
 172 #define PORTSCX_PHY_LOW_POWER_SPD              (0x00800000)
 173 #define PORTSCX_PORT_FORCE_FULL_SPEED          (0x01000000)
 174 #define PORTSCX_PORT_SPEED_MASK                (0x0C000000)
 175 #define PORTSCX_PORT_WIDTH                     (0x10000000)
 176 #define PORTSCX_PHY_TYPE_SEL                   (0xC0000000)
 177
 178 /* bit 11-10 are line status */
 179 #define PORTSCX_LINE_STATUS_SE0                (0x00000000)
 180 #define PORTSCX_LINE_STATUS_JSTATE             (0x00000400)
 181 #define PORTSCX_LINE_STATUS_KSTATE             (0x00000800)
 182 #define PORTSCX_LINE_STATUS_UNDEF              (0x00000C00)
 183 #define PORTSCX_LINE_STATUS_BIT_POS            (10)
 184
 185 /* bit 15-14 are port indicator control */
 186 #define PORTSCX_PIC_OFF                        (0x00000000)
 187 #define PORTSCX_PIC_AMBER                      (0x00004000)
 188 #define PORTSCX_PIC_GREEN                      (0x00008000)
 189 #define PORTSCX_PIC_UNDEF                      (0x0000C000)
 190 #define PORTSCX_PIC_BIT_POS                    (14)
 191
 192 /* bit 19-16 are port test control */
 193 #define PORTSCX_PTC_DISABLE                    (0x00000000)
 194 #define PORTSCX_PTC_JSTATE                     (0x00010000)
 195 #define PORTSCX_PTC_KSTATE                     (0x00020000)
 196 #define PORTSCX_PTC_SE0NAK                     (0x00030000)
 197 #define PORTSCX_PTC_PACKET                     (0x00040000)
 198 #define PORTSCX_PTC_FORCE_EN                   (0x00050000)
 199 #define PORTSCX_PTC_BIT_POS                    (16)
 200
 201 /* bit 27-26 are port speed */
 202 #define PORTSCX_PORT_SPEED_FULL                (0x00000000)
 203 #define PORTSCX_PORT_SPEED_LOW                 (0x04000000)
 204 #define PORTSCX_PORT_SPEED_HIGH                (0x08000000)
 205 #define PORTSCX_PORT_SPEED_UNDEF               (0x0C000000)
 206 #define PORTSCX_SPEED_BIT_POS                  (26)
 207
 208 /* bit 28 is parallel transceiver width for UTMI interface */
 209 #define PORTSCX_PTW                            (0x10000000)
 210 #define PORTSCX_PTW_8BIT                       (0x00000000)
 211 #define PORTSCX_PTW_16BIT                      (0x10000000)
 212
 213 /* bit 31-30 are port transceiver select */
 214 #define PORTSCX_PTS_UTMI                       (0x00000000)
 215 #define PORTSCX_PTS_CLASSIC                    (0x40000000)
 216 #define PORTSCX_PTS_ULPI                       (0x80000000)
 217 #define PORTSCX_PTS_FSLS                       (0xC0000000)
 218 #define PORTSCX_PTS_BIT_POS                    (30)
 219
 220 /* USB MODE Register Bit Masks */
 221 #define USBMODE_CTRL_MODE_IDLE                (0x00000000)
 222 #define USBMODE_CTRL_MODE_DEVICE              (0x00000002)
 223 #define USBMODE_CTRL_MODE_HOST                (0x00000003)
 224 #define USBMODE_CTRL_MODE_RSV                 (0x00000001)
 225 #define USBMODE_SETUP_LOCK_OFF                (0x00000008)
 226 #define USBMODE_STREAM_DISABLE                (0x00000010)
 227
 228 /* Endpoint Flush Register */
 229 #define EPFLUSH_TX_OFFSET                      (0x00010000)
 230 #define EPFLUSH_RX_OFFSET                      (0x00000000)
 231
 232 /* Endpoint Setup Status bit masks */
 233 #define EPSETUP_STATUS_MASK                   (0x0000003F)
 234 #define EPSETUP_STATUS_EP0                    (0x00000001)
 235
 236 /* ENDPOINTCTRLx  Register Bit Masks */
 237 #define EPCTRL_TX_ENABLE                       (0x00800000)
 238 #define EPCTRL_TX_DATA_TOGGLE_RST              (0x00400000)    /* Not EP0 */
 239 #define EPCTRL_TX_DATA_TOGGLE_INH              (0x00200000)    /* Not EP0 */
 240 #define EPCTRL_TX_TYPE                         (0x000C0000)
 241 #define EPCTRL_TX_DATA_SOURCE                  (0x00020000)    /* Not EP0 */
 242 #define EPCTRL_TX_EP_STALL                     (0x00010000)
 243 #define EPCTRL_RX_ENABLE                       (0x00000080)
 244 #define EPCTRL_RX_DATA_TOGGLE_RST              (0x00000040)    /* Not EP0 */
 245 #define EPCTRL_RX_DATA_TOGGLE_INH              (0x00000020)    /* Not EP0 */
 246 #define EPCTRL_RX_TYPE                         (0x0000000C)
 247 #define EPCTRL_RX_DATA_SINK                    (0x00000002)    /* Not EP0 */
 248 #define EPCTRL_RX_EP_STALL                     (0x00000001)
 249
 250 /* bit 19-18 and 3-2 are endpoint type */
 251 #define EPCTRL_EP_TYPE_CONTROL                 (0)
 252 #define EPCTRL_EP_TYPE_ISO                     (1)
 253 #define EPCTRL_EP_TYPE_BULK                    (2)
 254 #define EPCTRL_EP_TYPE_INTERRUPT               (3)
 255 #define EPCTRL_TX_EP_TYPE_SHIFT                (18)
 256 #define EPCTRL_RX_EP_TYPE_SHIFT                (2)
 257
 258 /* pri_ctrl Register Bit Masks */
 259 #define PRI_CTRL_PRI_LVL1                      (0x0000000C)
 260 #define PRI_CTRL_PRI_LVL0                      (0x00000003)
 261
 262 /* si_ctrl Register Bit Masks */
 263 #define SI_CTRL_ERR_DISABLE                    (0x00000010)
 264 #define SI_CTRL_IDRC_DISABLE                   (0x00000008)
 265 #define SI_CTRL_RD_SAFE_EN                     (0x00000004)
 266 #define SI_CTRL_RD_PREFETCH_DISABLE            (0x00000002)
 267 #define SI_CTRL_RD_PREFEFETCH_VAL              (0x00000001)
 268
 269 /* control Register Bit Masks */
 270 #define USB_CTRL_IOENB                         (0x00000004)
 271 #define USB_CTRL_ULPI_INT0EN                   (0x00000001)
 272
 273 /* OTGSC Register Bit Masks */
 274 #define OTGSC_B_SESSION_VALID                  (0x00000800)
 275 #define OTGSC_A_VBUS_VALID                     (0x00000200)
 276
 277 #define QH_MULT_POS                            (30)
 278 #define QH_ZLT_SEL                             (0x20000000)
 279 #define QH_MAX_PKT_LEN_POS                     (16)
 280 #define QH_IOS                                 (0x00008000)
 281 #define QH_NEXT_TERMINATE                      (0x00000001)
 282 #define QH_IOC                                 (0x00008000)
 283 #define QH_MULTO                               (0x00000C00)
 284 #define QH_STATUS_HALT                         (0x00000040)
 285 #define QH_STATUS_ACTIVE                       (0x00000080)
 286 #define EP_QUEUE_CURRENT_OFFSET_MASK         (0x00000FFF)
 287 #define EP_QUEUE_HEAD_NEXT_POINTER_MASK      (0xFFFFFFE0)
 288 #define EP_QUEUE_FRINDEX_MASK                (0x000007FF)
 289 #define EP_MAX_LENGTH_TRANSFER               (0x4000)
 290
 291 #define DTD_NEXT_TERMINATE                   (0x00000001)
 292 #define DTD_IOC                              (0x00008000)
 293 #define DTD_STATUS_ACTIVE                    (0x00000080)
 294 #define DTD_STATUS_HALTED                    (0x00000040)
 295 #define DTD_STATUS_DATA_BUFF_ERR             (0x00000020)
 296 #define DTD_STATUS_TRANSACTION_ERR           (0x00000008)
 297 #define DTD_RESERVED_FIELDS                  (0x80007300)
 298 #define DTD_ADDR_MASK                        (0xFFFFFFE0)
 299 #define DTD_PACKET_SIZE                      (0x7FFF0000)
 300 #define DTD_LENGTH_BIT_POS                   (16)
 301 #define DTD_ERROR_MASK                       (DTD_STATUS_HALTED | \
 302                                                DTD_STATUS_DATA_BUFF_ERR | \
 303                                                DTD_STATUS_TRANSACTION_ERR)
 304
 305 #define DTD_RESERVED_LENGTH_MASK             0x0001ffff
 306 #define DTD_RESERVED_IN_USE                  0x80000000
 307 #define DTD_RESERVED_PIPE_MASK               0x0ff00000
 308 #define DTD_RESERVED_PIPE_OFFSET             20
 309 /*-------------------------------------------------------------------------*/
 310
 311 /* manual: 32.13.2 Endpoint Transfer Descriptor (dTD) */
 312 struct transfer_descriptor {
 313     unsigned int next_td_ptr;           /* Next TD pointer(31-5), T(0) set
 314                                            indicate invalid */
 315     unsigned int size_ioc_sts;          /* Total bytes (30-16), IOC (15),
 316                                            MultO(11-10), STS (7-0)  */
 317     unsigned int buff_ptr0;             /* Buffer pointer Page 0 */
 318     unsigned int buff_ptr1;             /* Buffer pointer Page 1 */
 319     unsigned int buff_ptr2;             /* Buffer pointer Page 2 */
 320     unsigned int buff_ptr3;             /* Buffer pointer Page 3 */
 321     unsigned int buff_ptr4;             /* Buffer pointer Page 4 */
 322     unsigned int reserved;
 323 } __attribute__ ((packed));
 324
 325 static struct transfer_descriptor td_array[USB_NUM_ENDPOINTS*2]
 326     USB_DEVBSS_ATTR __attribute__((aligned(32)));
 327
 328 /* manual: 32.13.1 Endpoint Queue Head (dQH) */
 329 struct queue_head {
 330     unsigned int max_pkt_length;    /* Mult(31-30) , Zlt(29) , Max Pkt len
 331                                        and IOS(15) */
 332     unsigned int curr_dtd_ptr;      /* Current dTD Pointer(31-5) */
 333     struct transfer_descriptor dtd; /* dTD overlay */
 334     unsigned int setup_buffer[2];   /* Setup data 8 bytes */
 335     unsigned int reserved;          /* for software use, pointer to the first TD */
 336     unsigned int status;            /* for software use, status of chain in progress */
 337     unsigned int length;            /* for software use, transfered bytes of chain in progress */
 338     unsigned int wait;              /* for softwate use, indicates if the transfer is blocking */
 339 } __attribute__((packed));
 340
 341 static struct queue_head qh_array[USB_NUM_ENDPOINTS*2]
 342     USB_QHARRAY_ATTR;
 343
 344 static struct wakeup transfer_completion_signal[USB_NUM_ENDPOINTS*2]
 345     SHAREDBSS_ATTR;
 346
 347 static const unsigned int pipe2mask[] = {
 348     0x01, 0x010000,
 349     0x02, 0x020000,
 350     0x04, 0x040000,
 351     0x08, 0x080000,
 352     0x10, 0x100000,
 353 };
 354
 355 static char ep_allocation[USB_NUM_ENDPOINTS];
 356
 357 /*-------------------------------------------------------------------------*/
 358 static void transfer_completed(void);
 359 static void control_received(void);
 360 static int prime_transfer(int endpoint, void* ptr,
 361                           int len, bool send, bool wait);
 362 static void prepare_td(struct transfer_descriptor* td,
 363                        struct transfer_descriptor* previous_td,
 364                        void *ptr, int len,int pipe);
 365 static void bus_reset(void);
 366 static void init_control_queue_heads(void);
 367 static void init_bulk_queue_heads(void);
 368 static void init_endpoints(void);
 369 /*-------------------------------------------------------------------------*/
 370 static void usb_drv_stop(void)
 371 {
 372     /* disable interrupts */
 373     REG_USBINTR = 0;
 374     /* stop usb controller (disconnect) */
 375     REG_USBCMD &= ~USBCMD_RUN;
 376 }
 377
 378 void usb_drv_reset(void)
 379 {
 380     int oldlevel = disable_irq_save();
 381     REG_USBCMD &= ~USBCMD_RUN;
 382     restore_irq(oldlevel);
 383
 384 #ifdef USB_PORTSCX_PHY_TYPE
 385     /* If a PHY type is specified, set it now */
 386     REG_PORTSC1 = (REG_PORTSC1 & ~PORTSCX_PHY_TYPE_SEL) | USB_PORTSCX_PHY_TYPE;
 387 #endif
 388     sleep(HZ/20);
 389     REG_USBCMD |= USBCMD_CTRL_RESET;
 390     while (REG_USBCMD & USBCMD_CTRL_RESET);
 391 }
 392
 393 /* One-time driver startup init */
 394 void usb_drv_startup(void)
 395 {
 396     /* Initialize all the signal objects once */
 397     int i;
 398     for(i=0;i<USB_NUM_ENDPOINTS*2;i++) {
 399         wakeup_init(&transfer_completion_signal[i]);
 400     }
 401 }
 402
 403 /* manual: 32.14.1 Device Controller Initialization */
 404 static void _usb_drv_init(bool attach)
 405 {
 406     usb_drv_reset();
 407
 408     REG_USBMODE = USBMODE_CTRL_MODE_DEVICE;
 409
 410 #ifdef USB_NO_HIGH_SPEED
 411     /* Force device to full speed */
 412     /* See 32.9.5.9.2 */
 413     REG_PORTSC1 |= PORTSCX_PORT_FORCE_FULL_SPEED;
 414 #endif
 415
 416     init_control_queue_heads();
 417     memset(td_array, 0, sizeof td_array);
 418
 419     REG_ENDPOINTLISTADDR = (unsigned int)qh_array;
 420     REG_DEVICEADDR = 0;
 421
 422     if (!attach) {
 423         /* enable RESET interrupt */
 424         REG_USBINTR = USBINTR_RESET_EN;
 425     }
 426     else
 427     {
 428         /* enable USB interrupts */
 429         REG_USBINTR =
 430             USBINTR_INT_EN |
 431             USBINTR_ERR_INT_EN |
 432             USBINTR_PTC_DETECT_EN |
 433             USBINTR_RESET_EN;
 434     }
 435
 436     usb_drv_int_enable(true);
 437
 438     /* go go go */
 439     REG_USBCMD |= USBCMD_RUN;
 440
 441     logf("usb_drv_init() finished");
 442     logf("usb id %x", REG_ID);
 443     logf("usb dciversion %x", REG_DCIVERSION);
 444     logf("usb dccparams %x", REG_DCCPARAMS);
 445
 446     /* now a bus reset will occur. see bus_reset() */
 447     (void)attach;
 448 }
 449
 450 void usb_drv_init(void)
 451 {
 452     _usb_drv_init(false);
 453 }
 454
 455 /* fully enable driver */
 456 void usb_drv_attach(void)
 457 {
 458     sleep(HZ/10);
 459     _usb_drv_init(true);
 460 }
 461
 462 void usb_drv_exit(void)
 463 {
 464     usb_drv_stop();
 465
 466     /* TODO : is one of these needed to save power ?
 467     REG_PORTSC1 |= PORTSCX_PHY_LOW_POWER_SPD;
 468     REG_USBCMD |= USBCMD_CTRL_RESET;
 469     */
 470
 471     usb_drv_int_enable(false);
 472 }
 473
 474 void usb_drv_int(void)
 475 {
 476     unsigned int usbintr = REG_USBINTR; /* Only watch enabled ints */
 477     unsigned int status = REG_USBSTS & usbintr;
 478
 479 #if 0
 480     if (status & USBSTS_INT) logf("int: usb ioc");
 481     if (status & USBSTS_ERR) logf("int: usb err");
 482     if (status & USBSTS_PORT_CHANGE) logf("int: portchange");
 483     if (status & USBSTS_RESET) logf("int: reset");
 484 #endif
 485
 486     /* usb transaction interrupt */
 487     if (status & USBSTS_INT) {
 488         REG_USBSTS = USBSTS_INT;
 489
 490         /* a control packet? */
 491         if (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0) {
 492             control_received();
 493         }
 494
 495         if (REG_ENDPTCOMPLETE)
 496             transfer_completed();
 497     }
 498
 499     /* error interrupt */
 500     if (status & USBSTS_ERR) {
 501         REG_USBSTS = USBSTS_ERR;
 502         logf("usb error int");
 503     }
 504
 505     /* reset interrupt */
 506     if (status & USBSTS_RESET) {
 507         REG_USBSTS = USBSTS_RESET;
 508
 509         if (UNLIKELY(usbintr == USBINTR_RESET_EN)) {
 510             /* USB detected - detach and inform */
 511             usb_drv_stop();
 512             /* A false reset may occur upon unplugging, be sure VBUS is above
 513              * the 4V4 threshold. */
 514             if (usb_drv_powered())
 515                 usb_drv_usb_detect_event();
 516         }
 517         else
 518         {
 519             bus_reset();
 520             usb_core_bus_reset(); /* tell mom */
 521         }
 522     }
 523
 524     /* port change */
 525     if (status & USBSTS_PORT_CHANGE) {
 526         REG_USBSTS = USBSTS_PORT_CHANGE;
 527     }
 528 }
 529
 530 bool usb_drv_stalled(int endpoint,bool in)
 531 {
 532     if(in) {
 533         return ((REG_ENDPTCTRL(endpoint&0x7f) & EPCTRL_TX_EP_STALL)!=0);
 534     }
 535     else {
 536         return ((REG_ENDPTCTRL(endpoint&0x7f) & EPCTRL_RX_EP_STALL)!=0);
 537     }
 538
 539 }
 540 void usb_drv_stall(int endpoint, bool stall,bool in)
 541 {
 542     logf("%sstall %d", stall?"":"un", endpoint&0x7f);
 543
 544     if(in) {
 545         if (stall) {
 546             REG_ENDPTCTRL(endpoint&0x7f) |= EPCTRL_TX_EP_STALL;
 547         }
 548         else {
 549             REG_ENDPTCTRL(endpoint&0x7f) &= ~EPCTRL_TX_EP_STALL;
 550         }
 551     }
 552     else {
 553         if (stall) {
 554             REG_ENDPTCTRL(endpoint) |= EPCTRL_RX_EP_STALL;
 555         }
 556         else {
 557             REG_ENDPTCTRL(endpoint) &= ~EPCTRL_RX_EP_STALL;
 558         }
 559     }
 560 }
 561
 562 int usb_drv_send_nonblocking(int endpoint, void* ptr, int length)
 563 {
 564     return prime_transfer(endpoint&0x7f, ptr, length, true, false);
 565 }
 566
 567 int usb_drv_send(int endpoint, void* ptr, int length)
 568 {
 569     return prime_transfer(endpoint&0x7f, ptr, length, true, true);
 570 }
 571
 572 int usb_drv_recv(int endpoint, void* ptr, int length)
 573 {
 574     //logf("usbrecv(%x, %d)", ptr, length);
 575     return prime_transfer(endpoint&0x7f, ptr, length, false, false);
 576 }
 577
 578 int usb_drv_port_speed(void)
 579 {
 580     return (REG_PORTSC1 & 0x08000000) ? 1 : 0;
 581 }
 582
 583 bool usb_drv_connected(void)
 584 {
 585     return (REG_PORTSC1 &
 586         (PORTSCX_PORT_SUSPEND | PORTSCX_CURRENT_CONNECT_STATUS))
 587             == PORTSCX_CURRENT_CONNECT_STATUS;
 588 }
 589
 590 bool usb_drv_powered(void)
 591 {
 592     /* true = bus 4V4 ok */
 593     return (REG_OTGSC & OTGSC_A_VBUS_VALID) ? true : false;
 594 }
 595
 596 void usb_drv_set_address(int address)
 597 {
 598     REG_DEVICEADDR = address << USBDEVICEADDRESS_BIT_POS;
 599     init_bulk_queue_heads();
 600     init_endpoints();
 601 }
 602
 603 void usb_drv_reset_endpoint(int endpoint, bool send)
 604 {
 605     int pipe = (endpoint&0x7f) * 2 + (send ? 1 : 0);
 606     unsigned int mask = pipe2mask[pipe];
 607     REG_ENDPTFLUSH = mask;
 608     while (REG_ENDPTFLUSH & mask);
 609 }
 610
 611 void usb_drv_set_test_mode(int mode)
 612 {
 613     switch(mode){
 614         case 0:
 615             REG_PORTSC1 &= ~PORTSCX_PORT_TEST_CTRL;
 616             break;
 617         case 1:
 618             REG_PORTSC1 |= PORTSCX_PTC_JSTATE;
 619             break;
 620         case 2:
 621             REG_PORTSC1 |= PORTSCX_PTC_KSTATE;
 622             break;
 623         case 3:
 624             REG_PORTSC1 |= PORTSCX_PTC_SE0NAK;
 625             break;
 626         case 4:
 627             REG_PORTSC1 |= PORTSCX_PTC_PACKET;
 628             break;
 629         case 5:
 630             REG_PORTSC1 |= PORTSCX_PTC_FORCE_EN;
 631             break;
 632     }
 633     usb_drv_reset();
 634     REG_USBCMD |= USBCMD_RUN;
 635 }
 636
 637 /*-------------------------------------------------------------------------*/
 638
 639 /* manual: 32.14.5.2 */
 640 static int prime_transfer(int endpoint, void* ptr, int len, bool send, bool wait)
 641 {
 642     int rc = 0;
 643     int pipe = endpoint * 2 + (send ? 1 : 0);
 644     unsigned int mask = pipe2mask[pipe];
 645     struct queue_head* qh = &qh_array[pipe];
 646     static long last_tick;
 647     struct transfer_descriptor* new_td;
 648
 649     int oldlevel = disable_irq_save();
 650 /*
 651     if (send && endpoint > EP_CONTROL) {
 652         logf("usb: sent %d bytes", len);
 653     }
 654 */
 655     qh->status = 0;
 656     qh->length = 0;
 657     qh->wait   = wait;
 658
 659     new_td=&td_array[pipe];
 660     prepare_td(new_td, 0, ptr, len,pipe);
 661     //logf("starting ep %d %s",endpoint,send?"send":"receive");
 662
 663     qh->dtd.next_td_ptr = (unsigned int)new_td;
 664     qh->dtd.size_ioc_sts &= ~(QH_STATUS_HALT | QH_STATUS_ACTIVE);
 665
 666     REG_ENDPTPRIME |= mask;
 667
 668     if(endpoint == EP_CONTROL && (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0)) {
 669         /* 32.14.3.2.2 */
 670         logf("new setup arrived");
 671         rc = -4;
 672         goto pt_error;
 673     }
 674
 675     last_tick = current_tick;
 676     while ((REG_ENDPTPRIME & mask)) {
 677         if (REG_USBSTS & USBSTS_RESET) {
 678             rc = -1;
 679             goto pt_error;
 680         }
 681
 682         if (TIME_AFTER(current_tick, last_tick + HZ/4)) {
 683             logf("prime timeout");
 684             rc = -2;
 685             goto pt_error;
 686         }
 687     }
 688
 689     if (!(REG_ENDPTSTATUS & mask)) {
 690         logf("no prime! %d %d %x", endpoint, pipe, qh->dtd.size_ioc_sts & 0xff );
 691         rc = -3;
 692         goto pt_error;
 693     }
 694     if(endpoint == EP_CONTROL && (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0)) {
 695         /* 32.14.3.2.2 */
 696         logf("new setup arrived");
 697         rc = -4;
 698         goto pt_error;
 699     }
 700
 701     restore_irq(oldlevel);
 702
 703     if (wait) {
 704         /* wait for transfer to finish */
 705         wakeup_wait(&transfer_completion_signal[pipe], TIMEOUT_BLOCK);
 706         if(qh->status!=0) {
 707             /* No need to cancel wait here since it was done and the signal
 708              * came. */
 709             return -5;
 710         }
 711         //logf("all tds done");
 712     }
 713
 714 pt_error:
 715     if(rc<0)
 716         restore_irq(oldlevel);
 717
 718     /* Error status must make sure an abandoned wakeup signal isn't left */
 719     if (rc < 0 && wait) {
 720         /* Cancel wait */
 721         qh->wait = 0;
 722         /* Make sure to remove any signal if interrupt fired before we zeroed
 723          * qh->wait. Could happen during a bus reset for example. */
 724         wakeup_wait(&transfer_completion_signal[pipe], TIMEOUT_NOBLOCK);
 725     }
 726
 727     return rc;
 728 }
 729
 730 void usb_drv_cancel_all_transfers(void)
 731 {
 732     int i;
 733     REG_ENDPTFLUSH = ~0;
 734     while (REG_ENDPTFLUSH);
 735
 736     memset(td_array, 0, sizeof td_array);
 737     for(i=0;i<USB_NUM_ENDPOINTS*2;i++) {
 738         if(qh_array[i].wait) {
 739             qh_array[i].wait=0;
 740             qh_array[i].status=DTD_STATUS_HALTED;
 741             wakeup_signal(&transfer_completion_signal[i]);
 742         }
 743     }
 744 }
 745
 746 int usb_drv_request_endpoint(int dir)
 747 {
 748     int i, bit;
 749
 750     bit=(dir & USB_DIR_IN)? 2:1;
 751
 752     for (i=1; i < USB_NUM_ENDPOINTS; i++) {
 753         if((ep_allocation[i] & bit)!=0)
 754             continue;
 755         ep_allocation[i] |= bit;
 756         return i | dir;
 757     }
 758
 759     return -1;
 760 }
 761
 762 void usb_drv_release_endpoint(int ep)
 763 {
 764     int mask = (ep & USB_DIR_IN)? ~2:~1;
 765     ep_allocation[ep & 0x7f] &= mask;
 766 }
 767
 768
 769 static void prepare_td(struct transfer_descriptor* td,
 770                        struct transfer_descriptor* previous_td,
 771                        void *ptr, int len,int pipe)
 772 {
 773     //logf("adding a td : %d",len);
 774     memset(td, 0, sizeof(struct transfer_descriptor));
 775     td->next_td_ptr = DTD_NEXT_TERMINATE;
 776     td->size_ioc_sts = (len<< DTD_LENGTH_BIT_POS) |
 777         DTD_STATUS_ACTIVE | DTD_IOC;
 778     td->buff_ptr0 = (unsigned int)ptr;
 779     td->buff_ptr1 = ((unsigned int)ptr & 0xfffff000) + 0x1000;
 780     td->buff_ptr2 = ((unsigned int)ptr & 0xfffff000) + 0x2000;
 781     td->buff_ptr3 = ((unsigned int)ptr & 0xfffff000) + 0x3000;
 782     td->buff_ptr4 = ((unsigned int)ptr & 0xfffff000) + 0x4000;
 783     td->reserved |= DTD_RESERVED_LENGTH_MASK & len;
 784     td->reserved |= DTD_RESERVED_IN_USE;
 785     td->reserved |= (pipe << DTD_RESERVED_PIPE_OFFSET);
 786
 787     if (previous_td != 0) {
 788         previous_td->next_td_ptr=(unsigned int)td;
 789     }
 790 }
 791
 792 static void control_received(void)
 793 {
 794     int i;
 795     /* copy setup data from packet */
 796     static unsigned int tmp[2];
 797     tmp[0] = qh_array[0].setup_buffer[0];
 798     tmp[1] = qh_array[0].setup_buffer[1];
 799
 800     /* acknowledge packet recieved */
 801     REG_ENDPTSETUPSTAT = EPSETUP_STATUS_EP0;
 802
 803     /* Stop pending control transfers */
 804     for(i=0;i<2;i++) {
 805         if(qh_array[i].wait) {
 806             qh_array[i].wait=0;
 807             qh_array[i].status=DTD_STATUS_HALTED;
 808             wakeup_signal(&transfer_completion_signal[i]);
 809         }
 810     }
 811
 812     usb_core_control_request((struct usb_ctrlrequest*)tmp);
 813 }
 814
 815 static void transfer_completed(void)
 816 {
 817     int ep;
 818     unsigned int mask = REG_ENDPTCOMPLETE;
 819     REG_ENDPTCOMPLETE = mask;
 820
 821     for (ep=0; ep<USB_NUM_ENDPOINTS; ep++) {
 822         int dir;
 823         for (dir=0; dir<2; dir++) {
 824             int pipe = ep * 2 + dir;
 825             if (mask & pipe2mask[pipe]) {
 826                 struct queue_head* qh = &qh_array[pipe];
 827                 struct transfer_descriptor *td = &td_array[pipe];
 828
 829                 if(td->size_ioc_sts & DTD_STATUS_ACTIVE) {
 830                     /* TODO this shouldn't happen, but...*/
 831                     break;
 832                 }
 833                 if((td->size_ioc_sts & DTD_PACKET_SIZE) >> DTD_LENGTH_BIT_POS != 0 && dir==0) {
 834                     /* We got less data than we asked for. */
 835                 }
 836                 qh->length = (td->reserved & DTD_RESERVED_LENGTH_MASK) -
 837                     ((td->size_ioc_sts & DTD_PACKET_SIZE) >> DTD_LENGTH_BIT_POS);
 838                 if(td->size_ioc_sts & DTD_ERROR_MASK) {
 839                     logf("pipe %d err %x", pipe, td->size_ioc_sts & DTD_ERROR_MASK);
 840                     qh->status |= td->size_ioc_sts & DTD_ERROR_MASK;
 841                     /* TODO we need to handle this somehow. Flush the endpoint ? */
 842                 }
 843                 if(qh->wait) {
 844                     qh->wait=0;
 845                     wakeup_signal(&transfer_completion_signal[pipe]);
 846                 }
 847                 usb_core_transfer_complete(ep, dir?USB_DIR_IN:USB_DIR_OUT, qh->status, qh->length);
 848             }
 849         }
 850     }
 851 }
 852
 853 /* manual: 32.14.2.1 Bus Reset */
 854 static void bus_reset(void)
 855 {
 856     int i;
 857     logf("usb bus_reset");
 858
 859     REG_DEVICEADDR = 0;
 860     REG_ENDPTSETUPSTAT = REG_ENDPTSETUPSTAT;
 861     REG_ENDPTCOMPLETE  = REG_ENDPTCOMPLETE;
 862
 863     for (i=0; i<100; i++) {
 864         if (!REG_ENDPTPRIME)
 865             break;
 866
 867         if (REG_USBSTS & USBSTS_RESET) {
 868             logf("usb: double reset");
 869             return;
 870         }
 871
 872         udelay(100);
 873     }
 874     if (REG_ENDPTPRIME) {
 875         logf("usb: short reset timeout");
 876     }
 877
 878     usb_drv_cancel_all_transfers();
 879
 880     if (!(REG_PORTSC1 & PORTSCX_PORT_RESET)) {
 881         logf("usb: slow reset!");
 882     }
 883 }
 884
 885 /* manual: 32.14.4.1 Queue Head Initialization */
 886 static void init_control_queue_heads(void)
 887 {
 888     memset(qh_array, 0, sizeof qh_array);
 889
 890     /*** control ***/
 891     qh_array[EP_CONTROL].max_pkt_length = 64 << QH_MAX_PKT_LEN_POS | QH_IOS;
 892     qh_array[EP_CONTROL].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 893     qh_array[EP_CONTROL+1].max_pkt_length = 64 << QH_MAX_PKT_LEN_POS;
 894     qh_array[EP_CONTROL+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 895 }
 896 /* manual: 32.14.4.1 Queue Head Initialization */
 897 static void init_bulk_queue_heads(void)
 898 {
 899     int tx_packetsize;
 900     int rx_packetsize;
 901     int i;
 902
 903     if (usb_drv_port_speed()) {
 904         rx_packetsize = 512;
 905         tx_packetsize = 512;
 906     }
 907     else {
 908         rx_packetsize = 64;
 909         tx_packetsize = 64;
 910     }
 911     /* TODO: this should take ep_allocation into account */
 912
 913     /*** bulk ***/
 914     for(i=1;i<USB_NUM_ENDPOINTS;i++) {
 915         qh_array[i*2].max_pkt_length = rx_packetsize << QH_MAX_PKT_LEN_POS | QH_ZLT_SEL;
 916         qh_array[i*2].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 917         qh_array[i*2+1].max_pkt_length = tx_packetsize << QH_MAX_PKT_LEN_POS | QH_ZLT_SEL;
 918         qh_array[i*2+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 919     }
 920 }
 921
 922 static void init_endpoints(void)
 923 {
 924     int i;
 925     /* TODO: this should take ep_allocation into account */
 926     /* bulk */
 927     for(i=1;i<USB_NUM_ENDPOINTS;i++) {
 928         REG_ENDPTCTRL(i) =
 929             EPCTRL_RX_DATA_TOGGLE_RST | EPCTRL_RX_ENABLE |
 930             EPCTRL_TX_DATA_TOGGLE_RST | EPCTRL_TX_ENABLE |
 931             (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT) |
 932             (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT);
 933     }
 934 }