firmware/target/arm/as3525/sd-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 /* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
  24
  25 #include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
  26 #include "fat.h"
  27 #include "thread.h"
  28 #include "led.h"
  29 #include "sdmmc.h"
  30 #include "system.h"
  31 #include "cpu.h"
  32 #include <stdio.h>
  33 #include <stdlib.h>
  34 #include <string.h>
  35 #include "as3525.h"
  36 #include "pl180.h"  /* SD controller */
  37 #include "pl081.h"  /* DMA controller */
  38 #include "dma-target.h" /* DMA request lines */
  39 #include "clock-target.h"
  40 #include "panic.h"
  41 #ifdef HAVE_BUTTON_LIGHT
  42 #include "backlight-target.h"
  43 #endif
  44 #include "stdbool.h"
  45 #include "ata_idle_notify.h"
  46 #include "sd.h"
  47 #include "usb.h"
  48
  49 #ifdef HAVE_HOTSWAP
  50 #include "disk.h"
  51 #endif
  52
  53 /* command flags */
  54 #define MCI_NO_RESP     (0<<0)
  55 #define MCI_RESP        (1<<0)
  56 #define MCI_LONG_RESP   (1<<1)
  57
  58 /* ARM PL180 registers */
  59 #define MCI_POWER(i)       (*(volatile unsigned char *) (pl180_base[i]+0x00))
  60 #define MCI_CLOCK(i)       (*(volatile unsigned long *) (pl180_base[i]+0x04))
  61 #define MCI_ARGUMENT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x08))
  62 #define MCI_COMMAND(i)     (*(volatile unsigned long *) (pl180_base[i]+0x0C))
  63 #define MCI_RESPCMD(i)     (*(volatile unsigned long *) (pl180_base[i]+0x10))
  64 #define MCI_RESP0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x14))
  65 #define MCI_RESP1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x18))
  66 #define MCI_RESP2(i)       (*(volatile unsigned long *) (pl180_base[i]+0x1C))
  67 #define MCI_RESP3(i)       (*(volatile unsigned long *) (pl180_base[i]+0x20))
  68 #define MCI_DATA_TIMER(i)  (*(volatile unsigned long *) (pl180_base[i]+0x24))
  69 #define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
  70 #define MCI_DATA_CTRL(i)   (*(volatile unsigned char *) (pl180_base[i]+0x2C))
  71 #define MCI_DATA_CNT(i)    (*(volatile unsigned short*) (pl180_base[i]+0x30))
  72 #define MCI_STATUS(i)      (*(volatile unsigned long *) (pl180_base[i]+0x34))
  73 #define MCI_CLEAR(i)       (*(volatile unsigned long *) (pl180_base[i]+0x38))
  74 #define MCI_MASK0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x3C))
  75 #define MCI_MASK1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x40))
  76 #define MCI_SELECT(i)      (*(volatile unsigned long *) (pl180_base[i]+0x44))
  77 #define MCI_FIFO_CNT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x48))
  78
  79 #define MCI_DATA_ERROR    \
  80     ( MCI_DATA_CRC_FAIL   \
  81     | MCI_DATA_TIMEOUT    \
  82     | MCI_TX_UNDERRUN     \
  83     | MCI_RX_OVERRUN      \
  84     | MCI_START_BIT_ERR)
  85
  86 #define MCI_RESPONSE_ERROR    \
  87     ( MCI_CMD_TIMEOUT         \
  88     | MCI_CMD_CRC_FAIL)
  89
  90 #define MCI_FIFO(i)        ((unsigned long *) (pl180_base[i]+0x80))
  91 /* volumes */
  92 #define     INTERNAL_AS3525 0   /* embedded SD card */
  93 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  94
  95 static const int pl180_base[NUM_DRIVES] = {
  96             NAND_FLASH_BASE
  97 #ifdef HAVE_MULTIDRIVE
  98             , SD_MCI_BASE
  99 #endif
 100 };
 101
 102 static int sd_wait_for_tran_state(const int drive);
 103 static int sd_select_bank(signed char bank);
 104 static int sd_init_card(const int drive);
 105 static void init_pl180_controller(const int drive);
 106
 107 #define BLOCKS_PER_BANK 0x7a7800u
 108
 109 static tCardInfo card_info[NUM_DRIVES];
 110
 111 /* maximum timeouts recommanded in the SD Specification v2.00 */
 112 #define SD_MAX_READ_TIMEOUT     ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
 113 #define SD_MAX_WRITE_TIMEOUT    ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
 114
 115 /* for compatibility */
 116 static long last_disk_activity = -1;
 117
 118 #define MIN_YIELD_PERIOD 5  /* ticks */
 119 static long next_yield = 0;
 120
 121 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 122 static const char         sd_thread_name[] = "ata/sd";
 123 static struct mutex       sd_mtx;
 124 static struct event_queue sd_queue;
 125 bool sd_enabled = false;
 126
 127 #if defined(HAVE_MULTIDRIVE)
 128 static bool hs_card = false;
 129 #define EXT_SD_BITS (1<<2)
 130 #endif
 131
 132 static struct wakeup transfer_completion_signal;
 133 static volatile unsigned int transfer_error[NUM_VOLUMES];
 134 #define PL180_MAX_TRANSFER_ERRORS 10
 135
 136 #define UNALIGNED_NUM_SECTORS 10
 137 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 138 static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
 139
 140
 141 static inline void mci_delay(void) { udelay(1000) ; }
 142
 143
 144 static inline bool card_detect_target(void)
 145 {
 146 #if defined(HAVE_MULTIDRIVE)
 147     return !(GPIOA_PIN(2));
 148 #else
 149     return false;
 150 #endif
 151 }
 152
 153
 154 #ifdef HAVE_HOTSWAP
 155 static int sd1_oneshot_callback(struct timeout *tmo)
 156 {
 157     (void)tmo;
 158
 159     /* This is called only if the state was stable for 300ms - check state
 160      * and post appropriate event. */
 161     if (card_detect_target())
 162     {
 163         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 164     }
 165     else
 166         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 167
 168     return 0;
 169 }
 170
 171 void sd_gpioa_isr(void)
 172 {
 173     static struct timeout sd1_oneshot;
 174     if (GPIOA_MIS & EXT_SD_BITS)
 175         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 176     /* acknowledge interrupt */
 177     GPIOA_IC = EXT_SD_BITS;
 178 }
 179 #endif  /* HAVE_HOTSWAP */
 180
 181 void INT_NAND(void)
 182 {
 183     const int status = MCI_STATUS(INTERNAL_AS3525);
 184
 185     transfer_error[INTERNAL_AS3525] = status & MCI_DATA_ERROR;
 186
 187     wakeup_signal(&transfer_completion_signal);
 188     MCI_CLEAR(INTERNAL_AS3525) = status;
 189 }
 190
 191 #ifdef HAVE_MULTIDRIVE
 192 void INT_MCI0(void)
 193 {
 194     const int status = MCI_STATUS(SD_SLOT_AS3525);
 195
 196     transfer_error[SD_SLOT_AS3525] = status & MCI_DATA_ERROR;
 197
 198     wakeup_signal(&transfer_completion_signal);
 199     MCI_CLEAR(SD_SLOT_AS3525) = status;
 200 }
 201 #endif
 202
 203 static bool send_cmd(const int drive, const int cmd, const int arg,
 204                      const int flags, long *response)
 205 {
 206     int status;
 207
 208     unsigned cmd_retries = 6;
 209     while(cmd_retries--)
 210     {
 211         /* Clear old status flags */
 212         MCI_CLEAR(drive) = 0x7ff;
 213
 214         /* Load command argument or clear if none */
 215         MCI_ARGUMENT(drive) = arg;
 216
 217         /* Construct MCI_COMMAND & enable CPSM */
 218         MCI_COMMAND(drive) =
 219            /*b0:5*/  cmd
 220            /* b6 */| ((flags & (MCI_RESP|MCI_LONG_RESP)) ? MCI_COMMAND_RESPONSE : 0)
 221            /* b7 */| ((flags & MCI_LONG_RESP) ? MCI_COMMAND_LONG_RESPONSE : 0)
 222            /* b8   | MCI_COMMAND_INTERRUPT */
 223            /* b9   | MCI_COMMAND_PENDING */  /*Only used with stream data transfer*/
 224            /* b10*/| MCI_COMMAND_ENABLE;     /* Enables CPSM */
 225
 226         /* Wait while cmd completes then disable CPSM */
 227         while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);
 228         MCI_COMMAND(drive) = 0;
 229
 230         status = MCI_STATUS(drive);
 231
 232         /*  Handle command responses */
 233         if(flags & MCI_RESP)                /* CMD expects response */
 234         {
 235             response[0] = MCI_RESP0(drive); /* Always prepare short response */
 236
 237             if(status & MCI_RESPONSE_ERROR) /* timeout or crc failure */
 238                 continue;
 239
 240             if(status & MCI_CMD_RESP_END)   /* Response passed CRC check */
 241             {
 242                 if(flags & MCI_LONG_RESP)
 243                 {   /* response[0] has already been read */
 244                     response[1] = MCI_RESP1(drive);
 245                     response[2] = MCI_RESP2(drive);
 246                     response[3] = MCI_RESP3(drive);
 247                 }
 248                 return true;
 249             }
 250         }
 251         else if(status & MCI_CMD_SENT)  /* CMD sent, no response required */
 252             return true;
 253     }
 254
 255     return false;
 256 }
 257
 258 #define MCI_FULLSPEED     (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS)     /* MCLK   */
 259 #define MCI_HALFSPEED     (MCI_CLOCK_ENABLE)                        /* MCLK/2 */
 260 #define MCI_QUARTERSPEED  (MCI_CLOCK_ENABLE | 1)                    /* MCLK/4 */
 261 #define MCI_IDENTSPEED    (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV)  /* IDENT  */
 262
 263 static int sd_init_card(const int drive)
 264 {
 265     unsigned long response;
 266     long init_timeout;
 267     bool sd_v2 = false;
 268
 269     /* MCLCK on and set to 400kHz ident frequency  */
 270     MCI_CLOCK(drive) = MCI_IDENTSPEED;
 271
 272     /* 100 - 400kHz clock required for Identification Mode  */
 273     /*  Start of Card Identification Mode ************************************/
 274
 275     /* CMD0 Go Idle  */
 276     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 277         return -1;
 278     mci_delay();
 279
 280     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 281       Non v2 cards will not respond to this command*/
 282     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 283         if((response & 0xFFF) == 0x1AA)
 284             sd_v2 = true;
 285
 286     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 287     init_timeout = current_tick + HZ;
 288
 289     do {
 290         /* this timeout is the only valid error for this loop*/
 291         if(TIME_AFTER(current_tick, init_timeout))
 292             return -2;
 293
 294         /* app_cmd */
 295         send_cmd(drive, SD_APP_CMD, 0, MCI_RESP, &response);
 296
 297         /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 298         send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 299                         MCI_RESP, &card_info[drive].ocr);
 300
 301     } while(!(card_info[drive].ocr & (1<<31)));
 302
 303     /* CMD2 send CID */
 304     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP,
 305                             card_info[drive].cid))
 306         return -3;
 307
 308     /* CMD3 send RCA */
 309     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP,
 310                 &card_info[drive].rca))
 311         return -4;
 312
 313     /*  End of Card Identification Mode   ************************************/
 314
 315 #ifdef HAVE_MULTIDRIVE        /*  The internal SDs are v1 */
 316
 317     /* Try to switch V2 cards to HS timings, non HS seem to ignore this */
 318     if(sd_v2)
 319     {
 320         /*  CMD7 w/rca: Select card to put it in TRAN state */
 321         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 322             return -5;
 323
 324         if(sd_wait_for_tran_state(drive))
 325             return -6;
 326         /* CMD6 */
 327         if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
 328             return -7;
 329         mci_delay();
 330
 331         /*  go back to STBY state so we can read csd */
 332         /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 333         if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 334             return -8;
 335         mci_delay();
 336     }
 337 #endif /*  HAVE_MULTIDRIVE  */
 338
 339     /* CMD9 send CSD */
 340     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 341                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 342         return -9;
 343
 344     sd_parse_csd(&card_info[drive]);
 345
 346 #if defined(HAVE_MULTIDRIVE)
 347     hs_card = (card_info[drive].speed == 50000000);
 348 #endif
 349
 350     /* Boost MCICLK to operating speed */
 351     if(drive == INTERNAL_AS3525)
 352         MCI_CLOCK(drive) = MCI_HALFSPEED;  /* MCICLK = IDE_CLK/2 = 25 MHz  */
 353 #if defined(HAVE_MULTIDRIVE)
 354     else
 355         /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
 356         MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
 357 #endif
 358
 359     /*  CMD7 w/rca: Select card to put it in TRAN state */
 360     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 361         return -10;
 362
 363 #if 0 /* FIXME : it seems that write corrupts the filesystem */
 364     /*  Switch to to 4 bit widebus mode  */
 365     if(sd_wait_for_tran_state(drive) < 0)
 366         return -11;
 367     /* CMD55 */             /*  Response is requested due to timing issue  */
 368     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 369         return -14;
 370     /* ACMD42  */
 371     if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_RESP, &response))
 372         return -15;
 373     /* CMD55 */              /*  Response is requested due to timing issue  */
 374     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 375         return -12;
 376     /* ACMD6  */
 377     if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_RESP, &response))
 378         return -13;
 379     /* Now that card is widebus make controller aware */
 380     MCI_CLOCK(drive) |= MCI_CLOCK_WIDEBUS;
 381 #endif
 382
 383     /*
 384      * enable bank switching
 385      * without issuing this command, we only have access to 1/4 of the blocks
 386      * of the first bank (0x1E9E00 blocks, which is the size reported in the
 387      * CSD register)
 388      */
 389     if(drive == INTERNAL_AS3525)
 390     {
 391         const int ret = sd_select_bank(-1);
 392         if(ret < 0)
 393             return ret -16;
 394
 395         /*  CMD7 w/rca = 0: Unselect card to put it in STBY state */
 396         if(!send_cmd(drive, SD_SELECT_CARD, 0, MCI_NO_RESP, NULL))
 397             return -17;
 398         mci_delay();
 399
 400         /* CMD9 send CSD again, so we got the correct number of blocks */
 401         if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 402                      MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 403             return -18;
 404
 405         sd_parse_csd(&card_info[drive]);
 406         /* The OF is stored in the first blocks */
 407         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
 408
 409         /*  CMD7 w/rca: Select card to put it in TRAN state */
 410         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 411             return -19;
 412     }
 413
 414     card_info[drive].initialized = 1;
 415
 416     return 0;
 417 }
 418
 419 static void sd_thread(void) __attribute__((noreturn));
 420 static void sd_thread(void)
 421 {
 422     struct queue_event ev;
 423     bool idle_notified = false;
 424
 425     while (1)
 426     {
 427         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 428
 429         switch ( ev.id )
 430         {
 431 #ifdef HAVE_HOTSWAP
 432         case SYS_HOTSWAP_INSERTED:
 433         case SYS_HOTSWAP_EXTRACTED:
 434         {
 435             int microsd_init = 1;
 436             fat_lock();          /* lock-out FAT activity first -
 437                                     prevent deadlocking via disk_mount that
 438                                     would cause a reverse-order attempt with
 439                                     another thread */
 440             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 441                                     into driver that bypass the fat cache */
 442
 443             /* We now have exclusive control of fat cache and ata */
 444
 445             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 446                                     descriptors aren't leaked and any busy
 447                                     ones are invalid if mounting */
 448
 449             /* Force card init for new card, re-init for re-inserted one or
 450              * clear if the last attempt to init failed with an error. */
 451             card_info[SD_SLOT_AS3525].initialized = 0;
 452
 453             if (ev.id == SYS_HOTSWAP_INSERTED)
 454             {
 455                 sd_enable(true);
 456                 init_pl180_controller(SD_SLOT_AS3525);
 457                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 458                 if (microsd_init < 0) /* initialisation failed */
 459                     panicf("microSD init failed : %d", microsd_init);
 460
 461                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 462             }
 463
 464             /*
 465              * Mount succeeded, or this was an EXTRACTED event,
 466              * in both cases notify the system about the changed filesystems
 467              */
 468             if (microsd_init)
 469                 queue_broadcast(SYS_FS_CHANGED, 0);
 470
 471             /* Access is now safe */
 472             mutex_unlock(&sd_mtx);
 473             fat_unlock();
 474             sd_enable(false);
 475         }
 476             break;
 477 #endif
 478         case SYS_TIMEOUT:
 479             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 480             {
 481                 idle_notified = false;
 482             }
 483             else
 484             {
 485                 /* never let a timer wrap confuse us */
 486                 next_yield = current_tick;
 487
 488                 if (!idle_notified)
 489                 {
 490                     call_storage_idle_notifys(false);
 491                     idle_notified = true;
 492                 }
 493             }
 494             break;
 495
 496         case SYS_USB_CONNECTED:
 497             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 498             /* Wait until the USB cable is extracted again */
 499             usb_wait_for_disconnect(&sd_queue);
 500
 501             break;
 502         case SYS_USB_DISCONNECTED:
 503             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 504             break;
 505         }
 506     }
 507 }
 508
 509 static void init_pl180_controller(const int drive)
 510 {
 511     MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;
 512     MCI_CLEAR(drive) = 0x7ff;
 513
 514     MCI_MASK0(drive) = MCI_DATA_ERROR | MCI_DATA_END;
 515     MCI_MASK1(drive) = 0;
 516 #ifdef HAVE_MULTIDRIVE
 517     VIC_INT_ENABLE =
 518         (drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
 519     /* clear previous irq */
 520     GPIOA_IC = EXT_SD_BITS;
 521     /* enable edge detecting */
 522     GPIOA_IS &= ~EXT_SD_BITS;
 523     /* detect both raising and falling edges */
 524     GPIOA_IBE |= EXT_SD_BITS;
 525     /* enable the card detect interrupt */
 526     GPIOA_IE |= EXT_SD_BITS;
 527
 528 #else
 529     VIC_INT_ENABLE = INTERRUPT_NAND;
 530 #endif
 531
 532     MCI_POWER(drive) = MCI_POWER_UP | (MCI_VDD_3_0);  /*  OF Setting  */
 533     mci_delay();
 534
 535     MCI_POWER(drive) |= MCI_POWER_ON;
 536     mci_delay();
 537
 538     MCI_SELECT(drive) = 0;
 539
 540     /* Pl180 clocks get turned on at start of card init */
 541 }
 542
 543 int sd_init(void)
 544 {
 545     int ret;
 546     CGU_IDE =   (1<<6)                  /*  enable non AHB interface*/
 547             |   (AS3525_IDE_DIV << 2)
 548             |    AS3525_CLK_PLLA;       /* clock source = PLLA */
 549
 550     CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
 551 #ifdef HAVE_MULTIDRIVE
 552     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 553     CCU_IO &= ~(1<<3);           /* bits 3:2 = 01, xpd is SD interface */
 554     CCU_IO |= (1<<2);
 555 #endif
 556
 557     wakeup_init(&transfer_completion_signal);
 558
 559     init_pl180_controller(INTERNAL_AS3525);
 560     ret = sd_init_card(INTERNAL_AS3525);
 561     if(ret < 0)
 562         return ret;
 563 #ifdef HAVE_MULTIDRIVE
 564     init_pl180_controller(SD_SLOT_AS3525);
 565 #endif
 566
 567     /* init mutex */
 568     mutex_init(&sd_mtx);
 569
 570     queue_init(&sd_queue, true);
 571     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 572             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 573
 574     sd_enabled = true;
 575     sd_enable(false);
 576
 577     return 0;
 578 }
 579
 580 #ifdef HAVE_HOTSWAP
 581 bool sd_removable(IF_MD_NONVOID(int drive))
 582 {
 583     return (drive==1);
 584 }
 585
 586 bool sd_present(IF_MD_NONVOID(int drive))
 587 {
 588     return (drive == 0) ? true : card_detect_target();
 589 }
 590 #endif /* HAVE_HOTSWAP */
 591
 592 static int sd_wait_for_tran_state(const int drive)
 593 {
 594     unsigned long response = 0;
 595     unsigned int timeout = current_tick + 5 * HZ;
 596
 597     while (1)
 598     {
 599         if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP,
 600                     &response))
 601             return -1;
 602
 603         if (((response >> 9) & 0xf) == SD_TRAN)
 604             return 0;
 605
 606         if(TIME_AFTER(current_tick, timeout))
 607             return -2;
 608
 609         if (TIME_AFTER(current_tick, next_yield))
 610         {
 611             yield();
 612             next_yield = current_tick + MIN_YIELD_PERIOD;
 613         }
 614     }
 615 }
 616
 617 static int sd_select_bank(signed char bank)
 618 {
 619     int ret;
 620     unsigned loops = 0;
 621
 622     memset(uncached_buffer, 0, 512);
 623     if(bank == -1)
 624     {   /* enable bank switching */
 625         uncached_buffer[0] = 16;
 626         uncached_buffer[1] = 1;
 627         uncached_buffer[2] = 10;
 628     }
 629     else
 630         uncached_buffer[0] = bank;
 631
 632     do {
 633         if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 634             panicf("SD bank %d error : 0x%x", bank,
 635                     transfer_error[INTERNAL_AS3525]);
 636
 637         ret = sd_wait_for_tran_state(INTERNAL_AS3525);
 638         if (ret < 0)
 639             return ret - 2;
 640
 641         if(!send_cmd(INTERNAL_AS3525, SD_SWITCH_FUNC, 0x80ffffef, MCI_NO_RESP,
 642                      NULL))
 643             return -1;
 644
 645         mci_delay();
 646
 647         if(!send_cmd(INTERNAL_AS3525, 35, 0, MCI_NO_RESP, NULL))
 648             return -2;
 649
 650         mci_delay();
 651
 652         dma_retain();
 653         /* we don't use the uncached buffer here, because we need the
 654          * physical memory address for DMA transfers */
 655         dma_enable_channel(0, aligned_buffer, MCI_FIFO(INTERNAL_AS3525),
 656             DMA_PERI_SD, DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8,
 657             NULL);
 658
 659         MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT;
 660         MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
 661         MCI_DATA_CTRL(INTERNAL_AS3525) =  (1<<0) /* enable */   |
 662                                 (0<<1) /* transfer direction */ |
 663                                 (1<<3) /* DMA */                |
 664                                 (9<<4) /* 2^9 = 512 */ ;
 665
 666         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 667         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 668
 669         /*  Wait for FIFO to empty, card may still be in PRG state  */
 670         while(MCI_STATUS(INTERNAL_AS3525) & MCI_TX_ACTIVE );
 671
 672         dma_release();
 673
 674     } while(transfer_error[INTERNAL_AS3525]);
 675
 676     card_info[INTERNAL_AS3525].current_bank = (bank == -1) ? 0 : bank;
 677
 678     return 0;
 679 }
 680
 681 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 682                                int count, void* buf, const bool write)
 683 {
 684 #ifndef HAVE_MULTIDRIVE
 685     const int drive = 0;
 686 #endif
 687     int ret = 0;
 688     unsigned loops = 0;
 689     bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
 690
 691     mutex_lock(&sd_mtx);
 692     sd_enable(true);
 693     led(true);
 694
 695     if (card_info[drive].initialized <= 0)
 696     {
 697         ret = sd_init_card(drive);
 698         if (!(card_info[drive].initialized))
 699             goto sd_transfer_error_nodma;
 700     }
 701
 702     if(count < 0) /* XXX: why is it signed ? */
 703     {
 704         ret = -20;
 705         goto sd_transfer_error_nodma;
 706     }
 707     if((start+count) > card_info[drive].numblocks)
 708     {
 709         ret = -21;
 710         goto sd_transfer_error_nodma;
 711     }
 712
 713     /* skip SanDisk OF */
 714     if (drive == INTERNAL_AS3525)
 715         start += AMS_OF_SIZE;
 716
 717     last_disk_activity = current_tick;
 718
 719     dma_retain();
 720
 721     if(aligned)
 722     {
 723         if(write)
 724             clean_dcache_range(buf, count * SECTOR_SIZE);
 725         else
 726             dump_dcache_range(buf, count * SECTOR_SIZE);
 727     }
 728
 729     while(count)
 730     {
 731         /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
 732          * register, so we have to transfer maximum 127 sectors at a time. */
 733         unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
 734         void *dma_buf;
 735         const int cmd =
 736             write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 737         unsigned long bank_start = start;
 738         unsigned long status;
 739
 740         /* Only switch banks for internal storage */
 741         if(drive == INTERNAL_AS3525)
 742         {
 743             unsigned int bank = 0;
 744             while(bank_start >= BLOCKS_PER_BANK)
 745             {
 746                 bank_start -= BLOCKS_PER_BANK;
 747                 bank++;
 748             }
 749
 750             /* Switch bank if needed */
 751             if(card_info[INTERNAL_AS3525].current_bank != bank)
 752             {
 753                 ret = sd_select_bank(bank);
 754                 if (ret < 0)
 755                 {
 756                     ret -= 20;
 757                     goto sd_transfer_error;
 758                 }
 759             }
 760
 761             /* Do not cross a bank boundary in a single transfer loop */
 762             if((transfer + bank_start) > BLOCKS_PER_BANK)
 763                 transfer = BLOCKS_PER_BANK - bank_start;
 764         }
 765
 766         /* Set bank_start to the correct unit (blocks or bytes) */
 767         if(!(card_info[drive].ocr & (1<<30)))   /* not SDHC */
 768             bank_start *= SD_BLOCK_SIZE;
 769
 770         if(aligned)
 771         {
 772             dma_buf = AS3525_PHYSICAL_ADDR(buf);
 773         }
 774         else
 775         {
 776             dma_buf = aligned_buffer;
 777             if(transfer > UNALIGNED_NUM_SECTORS)
 778                 transfer = UNALIGNED_NUM_SECTORS;
 779
 780             if(write)
 781                 memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 782         }
 783
 784         ret = sd_wait_for_tran_state(drive);
 785         if (ret < 0)
 786         {
 787             ret -= 2*20;
 788             goto sd_transfer_error;
 789         }
 790
 791         if(!send_cmd(drive, cmd, bank_start, MCI_NO_RESP, NULL))
 792         {
 793             ret -= 3*20;
 794             goto sd_transfer_error;
 795         }
 796
 797         if(write)
 798         {
 799             dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
 800                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 801                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 802
 803             /*Small delay for writes prevents data crc failures at lower freqs*/
 804 #ifdef HAVE_MULTIDRIVE
 805             if((drive == SD_SLOT_AS3525) && !hs_card)
 806             {
 807                 int write_delay = 125;
 808                 while(write_delay--);
 809             }
 810 #endif
 811         }
 812         else
 813             dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
 814                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 815                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 816
 817         MCI_DATA_TIMER(drive) = write ?
 818                 SD_MAX_WRITE_TIMEOUT : SD_MAX_READ_TIMEOUT;
 819         MCI_DATA_LENGTH(drive) = transfer * SD_BLOCK_SIZE;
 820         MCI_DATA_CTRL(drive) =  (1<<0) /* enable */                     |
 821                                 (!write<<1) /* transfer direction */    |
 822                                 (1<<3) /* DMA */                        |
 823                                 (9<<4) /* 2^9 = 512 */ ;
 824
 825         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 826         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 827
 828         /*  Wait for FIFO to empty, card may still be in PRG state for writes */
 829         while(MCI_STATUS(drive) & MCI_TX_ACTIVE);
 830
 831         last_disk_activity = current_tick;
 832
 833         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_RESP, &status))
 834         {
 835             ret = -4*20;
 836             goto sd_transfer_error;
 837         }
 838
 839         if(!transfer_error[drive])
 840         {
 841             if(!write && !aligned)
 842                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 843             buf += transfer * SD_BLOCK_SIZE;
 844             start += transfer;
 845             count -= transfer;
 846             loops = 0;  /* reset errors counter */
 847         }
 848         else if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 849                 panicf("SD Xfer %s err:0x%x Disk%d", (write? "write": "read"),
 850                                                   transfer_error[drive], drive);
 851     }
 852
 853 sd_transfer_error:
 854
 855     dma_release();
 856
 857 sd_transfer_error_nodma:
 858
 859     led(false);
 860     sd_enable(false);
 861
 862     if (ret)    /* error */
 863         card_info[drive].initialized = 0;
 864
 865     mutex_unlock(&sd_mtx);
 866     return ret;
 867 }
 868
 869 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 870                      void* buf)
 871 {
 872     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 873 }
 874
 875 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 876                      const void* buf)
 877 {
 878     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 879 }
 880
 881 long sd_last_disk_activity(void)
 882 {
 883     return last_disk_activity;
 884 }
 885
 886 void sd_enable(bool on)
 887 {
 888 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 889     extern int buttonlight_is_on;
 890 #endif
 891
 892 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 893     static bool cpu_boosted = false;
 894 #endif
 895
 896     if (sd_enabled == on)
 897         return; /* nothing to do */
 898
 899     sd_enabled = on;
 900
 901     if(on)
 902     {
 903 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 904         /* buttonlight AMSes need a bit of special handling for the buttonlight
 905          * here due to the dual mapping of GPIOD and XPD */
 906         CCU_IO |= (1<<2);              /* XPD is SD-MCI interface (b3:2 = 01) */
 907         if (buttonlight_is_on)
 908             GPIOD_DIR &= ~(1<<7);
 909         else
 910             _buttonlight_off();
 911 #endif
 912
 913 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 914         if(card_detect_target())  /* If SD card present Boost cpu for voltage */
 915         {
 916             cpu_boosted = true;
 917             cpu_boost(true);
 918         }
 919 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 920     }
 921     else
 922     {
 923 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 924         if(cpu_boosted)
 925         {
 926             cpu_boost(false);
 927             cpu_boosted = false;
 928         }
 929 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 930
 931 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 932         CCU_IO &= ~(1<<2);           /* XPD is general purpose IO (b3:2 = 00) */
 933         if (buttonlight_is_on)
 934             _buttonlight_on();
 935 #endif
 936     }
 937 }
 938
 939 tCardInfo *card_get_info_target(int card_no)
 940 {
 941     return &card_info[card_no];
 942 }
 943
 944 #ifdef CONFIG_STORAGE_MULTI
 945 int sd_num_drives(int first_drive)
 946 {
 947     /* We don't care which logical drive number(s) we have been assigned */
 948     (void)first_drive;
 949
 950     return NUM_DRIVES;
 951 }
 952 #endif /* CONFIG_STORAGE_MULTI */