firmware/target/arm/as3525/usb-drv-as3525v2.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2010 Amaury Pouly
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef __USB_DRV_AS3525v2_H__
  22 #define __USB_DRV_AS3525v2_H__
  23
  24 #include "as3525v2.h"
  25
  26 /* All multi-bit fields in the driver use the following convention.
  27  * If the register name is NAME, then there is one define NAME_bit_pos
  28  * which holds the bit position and one define NAME_bits which holds
  29  * a mask of the bits within the register.
  30  * These macros allow easy access and construction of such fields */
  31 /* Usage:
  32  * - extract(reg_name,field_name)
  33      note: the field_name must not be prefix with the reg name */
  34 #define extract(reg_name, field_name) \
  35     ((reg_name & reg_name##_##field_name##_bits) >> reg_name##_##field_name##_bit_pos)
  36
  37 #define USB_DEVICE                  (USB_BASE + 0x0800)   /** USB Device base address */
  38
  39 /**
  40  * Core Global Registers
  41  */
  42 #define BASE_REG(offset) (*(volatile unsigned long *)(USB_BASE + offset))
  43
  44 /** OTG Control and Status Register */
  45 #define GOTGCTL     BASE_REG(0x000)
  46
  47 /** OTG Interrupt Register */
  48 #define GOTGINT     BASE_REG(0x004)
  49
  50 /** Core AHB Configuration Register */
  51 #define GAHBCFG                         BASE_REG(0x008)
  52 #define GAHBCFG_glblintrmsk             (1 << 0) /** Global interrupt mask */
  53 #define GAHBCFG_hburstlen_bit_pos       1
  54 #define GAHBCFG_INT_DMA_BURST_SINGLE    0
  55 #define GAHBCFG_INT_DMA_BURST_INCR      1 /** note: the linux patch has several other value, this is one picked for internal dma */
  56 #define GAHBCFG_INT_DMA_BURST_INCR4     3
  57 #define GAHBCFG_INT_DMA_BURST_INCR8     5
  58 #define GAHBCFG_INT_DMA_BURST_INCR16    7
  59 #define GAHBCFG_dma_enable              (1 << 5) /** Enable DMA */
  60
  61 /** Core USB Configuration Register */
  62 #define GUSBCFG                         BASE_REG(0x00C)
  63 #define GUSBCFG_toutcal_bit_pos         0
  64 #define GUSBCFG_toutcal_bits            (0x7 << GUSBCFG_toutcal_bit_pos)
  65 #define GUSBCFG_phy_if                  (1 << 3) /** select utmi bus width ? */
  66 #define GUSBCFG_ulpi_utmi_sel           (1 << 4) /** select ulpi:1 or utmi:0 */
  67 #define GUSBCFG_fsintf                  (1 << 5)
  68 #define GUSBCFG_physel                  (1 << 6)
  69 #define GUSBCFG_ddrsel                  (1 << 7)
  70 #define GUSBCFG_srpcap                  (1 << 8)
  71 #define GUSBCFG_hnpcapp                 (1 << 9)
  72 #define GUSBCFG_usbtrdtim_bit_pos       10
  73 #define GUSBCFG_usbtrdtim_bits          (0xf << GUSBCFG_usbtrdtim_bit_pos)
  74 #define GUSBCFG_nptxfrwnden             (1 << 14)
  75 #define GUSBCFG_phylpwrclksel           (1 << 15)
  76 #define GUSBCFG_otgutmifssel            (1 << 16)
  77 #define GUSBCFG_ulpi_fsls               (1 << 17)
  78 #define GUSBCFG_ulpi_auto_res           (1 << 18)
  79 #define GUSBCFG_ulpi_clk_sus_m          (1 << 19)
  80 #define GUSBCFG_ulpi_ext_vbus_drv       (1 << 20)
  81 #define GUSBCFG_ulpi_int_vbus_indicator (1 << 21)
  82 #define GUSBCFG_term_sel_dl_pulse       (1 << 22)
  83 #define GUSBCFG_force_host_mode         (1 << 29)
  84 #define GUSBCFG_force_device_mode       (1 << 30)
  85 #define GUSBCFG_corrupt_tx_packet       (1 << 31)
  86
  87 /** Core Reset Register */
  88 #define GRSTCTL                 BASE_REG(0x010)
  89 #define GRSTCTL_csftrst         (1 << 0) /** Core soft reset */
  90 #define GRSTCTL_hsftrst         (1 << 1) /** Hclk soft reset */
  91 #define GRSTCTL_intknqflsh      (1 << 3) /** In Token Sequence Learning Queue Flush */
  92 #define GRSTCTL_rxfflsh_flush   (1 << 4) /** RxFIFO Flush */
  93 #define GRSTCTL_txfflsh_flush   (1 << 5) /** TxFIFO Flush */
  94 #define GRSTCTL_txfnum_bit_pos  6 /** TxFIFO Number */
  95 #define GRSTCTL_txfnum_bits     (0x1f << 6)
  96 #define GRSTCTL_ahbidle         (1 << 31) /** AHB idle state*/
  97
  98 /** Core Interrupt Register */
  99 #define GINTSTS             BASE_REG(0x014)
 100 /* NOTE: GINTSTS bits are the same as in GINTMSK plus this one */
 101 #define GINTSTS_curmode     (1 << 0) /** Current mode, 0 for device */
 102
 103 /** Core Interrupt Mask Register */
 104 #define GINTMSK                 BASE_REG(0x018)
 105 #define GINTMSK_modemismatch    (1 << 1) /** mode mismatch ? */
 106 #define GINTMSK_otgintr         (1 << 2)
 107 #define GINTMSK_sofintr         (1 << 3)
 108 #define GINTMSK_rxstsqlvl       (1 << 4)
 109 #define GINTMSK_nptxfempty      (1 << 5) /** Non-periodic TX fifo empty ? */
 110 #define GINTMSK_ginnakeff       (1 << 6)
 111 #define GINTMSK_goutnakeff      (1 << 7)
 112 #define GINTMSK_i2cintr         (1 << 9)
 113 #define GINTMSK_erlysuspend     (1 << 10)
 114 #define GINTMSK_usbsuspend      (1 << 11) /** USB suspend */
 115 #define GINTMSK_usbreset        (1 << 12) /** USB reset */
 116 #define GINTMSK_enumdone        (1 << 13) /** Enumeration done */
 117 #define GINTMSK_isooutdrop      (1 << 14)
 118 #define GINTMSK_eopframe        (1 << 15)
 119 #define GINTMSK_epmismatch      (1 << 17) /** endpoint mismatch ? */
 120 #define GINTMSK_inepintr        (1 << 18) /** in pending ? */
 121 #define GINTMSK_outepintr       (1 << 19) /** out pending ? */
 122 #define GINTMSK_incomplisoin    (1 << 20) /** ISP in complete ? */
 123 #define GINTMSK_incomplisoout   (1 << 21) /** ISO out complete ? */
 124 #define GINTMSK_portintr        (1 << 24) /** Port status change ? */
 125 #define GINTMSK_hcintr          (1 << 25)
 126 #define GINTMSK_ptxfempty       (1 << 26) /** Periodic TX fifof empty ? */
 127 #define GINTMSK_conidstschng    (1 << 28)
 128 #define GINTMSK_disconnect      (1 << 29) /** Disconnect */
 129 #define GINTMSK_sessreqintr     (1 << 30) /** Session request */
 130 #define GINTMSK_wkupintr        (1 << 31) /** Wake up */
 131
 132 /** Receive Status Debug Read Register (Read Only) */
 133 #define GRXSTSR     BASE_REG(0x01C)
 134
 135 /** Receive Status Read /Pop Register (Read Only) */
 136 #define GRXSTSP     BASE_REG(0x020)
 137
 138 /** Receive FIFO Size Register */
 139 #define GRXFSIZ     BASE_REG(0x024)
 140
 141 /** Periodic Transmit FIFO Size Register */
 142 #define GNPTXFSIZ   BASE_REG(0x028)
 143
 144 /** Non-Periodic Transmit FIFO/Queue Status Register */
 145 #define GNPTXSTS    BASE_REG(0x02C)
 146
 147 /** I2C Access Register */
 148 #define GI2CCTL     BASE_REG(0x030)
 149
 150 /** PHY Vendor Control Register */
 151 #define GPVNDCTL    BASE_REG(0x034)
 152
 153 /** General Purpose Input/Output Register */
 154 #define GGPIO       BASE_REG(0x038)
 155
 156 /** User ID Register */
 157 #define GUID        BASE_REG(0x03C)
 158
 159 /** Synopsys ID Register */
 160 #define GSNPSID     BASE_REG(0x040)
 161
 162 /** User HW Config1 Register */
 163 #define GHWCFG1             BASE_REG(0x044)
 164 #define GHWCFG1_IN_EP(ep)   (1 << (2 * (ep))) /** 1 if EP(ep) has in cap */
 165 #define GHWCFG1_OUT_EP(ep)  (1 << (1 + 2 * (ep))) /** same for out */
 166
 167 /** User HW Config2 Register */
 168 #define GHWCFG2                     BASE_REG(0x048)
 169 #define GHWCFG2_ARCH_bit_pos        3 /** Architecture */
 170 #define GHWCFG2_ARCH_bits           (0x3 << GHWCFG2_ARCH_bit_pos)
 171 #define GHWCFG2_HS_PHY_TYPE_bit_pos 6 /** High speed PHY type */
 172 #define GHWCFG2_HS_PHY_TYPE_bits    (0x3 << GHWCFG2_HS_PHY_TYPE_bit_pos)
 173 #define GHWCFG2_FS_PHY_TYPE_bit_pos 8 /** Full speed PHY type */
 174 #define GHWCFG2_FS_PHY_TYPE_bits    (0x3 << GHWCFG2_FS_PHY_TYPE_bit_pos)
 175 #define GHWCFG2_NUM_EP_bit_pos      10 /** Number of endpoints */
 176 #define GHWCFG2_NUM_EP_bits         (0xf << GHWCFG2_NUM_EP_bit_pos)
 177 #define GHWCFG2_DYN_FIFO            (1 << 19) /** Dynamic FIFO */
 178 /* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_SS_PHY_TYPE */
 179 #define PHY_TYPE_UNSUPPORTED        0
 180 #define PHY_TYPE_UTMI               1
 181 #define INT_DMA_ARCH                2
 182
 183 /** User HW Config3 Register */
 184 #define GHWCFG3     BASE_REG(0x04C)
 185
 186 /** User HW Config4 Register */
 187 #define GHWCFG4     BASE_REG(0x050)
 188
 189 /* 1<=ep<=15, don't use ep=0 !!! */
 190 /** Device IN Endpoint Transmit FIFO (ep) Size Register */
 191 #define DIEPTXFSIZ(ep)  BASE_REG(0x100 + 4 * (ep))
 192
 193 /** Build the content of a FIFO size register like DIEPTXFSIZ(i) and GNPTXFSIZ*/
 194 #define MAKE_FIFOSIZE_DATA(startadr, depth) \
 195     (((startadr) & 0xffff) | ((depth) << 16))
 196 /** Retrieve fifo size for such registers */
 197 #define GET_FIFOSIZE_DEPTH(data) \
 198     ((data) >> 16)
 199 /** Retrieve fifo start address for such registers */
 200 #define GET_FIFOSIZE_START_ADR(data) \
 201     ((data) & 0xffff)
 202
 203
 204
 205
 206
 207 #define GHWCFG3_DFIFO_LEN               (GHWCFG3 >> 16) /** Total fifo size */
 208
 209 #define GHWCFG4_UTMI_PHY_DATA_WIDTH     ((GHWCFG4 >> 14) & 0x3) /** UTMI+ data bus width (format is unsure) */
 210 #define GHWCFG4_DED_FIFO_EN             ((GHWCFG4 >> 25) & 0x1) /** Dedicated Tx FIFOs */
 211 #define GHWCFG4_NUM_IN_EP               ((GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */
 212
 213
 214
 215 /**
 216  * Device Registers Base Addresses
 217  */
 218 #define DEV_REG(offset) (*(volatile unsigned long *)(USB_DEVICE + offset))
 219
 220 #define DCFG        DEV_REG(0x00) /** Device Configuration Register */
 221 #define DCTL        DEV_REG(0x04) /** Device Control Register */
 222 #define DSTS        DEV_REG(0x08) /** Device Status Register */
 223 #define DIEPMSK     DEV_REG(0x10) /** Device IN Endpoint Common Interrupt Mask Register */
 224 #define DOEPMSK     DEV_REG(0x14) /** Device OUT Endpoint Common Interrupt Mask Register */
 225 #define DAINT       DEV_REG(0x18) /** Device All Endpoints Interrupt Register */
 226 #define DAINTMSK    DEV_REG(0x1C) /** Device Endpoints Interrupt Mask Register */
 227 #define DTKNQR1     DEV_REG(0x20) /** Device IN Token Sequence Learning Queue Read Register 1 */
 228 #define DTKNQR2     DEV_REG(0x24) /** Device IN Token Sequence Learning Queue Register 2 */
 229 #define DTKNQP      DEV_REG(0x28) /** Device IN Token Queue Pop register */
 230 /* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h.
 231  *        the previous registers exists but has a different name :( */
 232 #define DVBUSDIS    DEV_REG(0x28) /** Device VBUS discharge register*/
 233 #define DVBUSPULSE  DEV_REG(0x2C) /** Device VBUS pulse register */
 234 #define DTKNQR3     DEV_REG(0x30) /** Device IN Token Queue Read Register 3 (RO) */
 235 #define DTHRCTL     DEV_REG(0x30) /** Device Thresholding control register */
 236 #define DTKNQR4     DEV_REG(0x34) /** Device IN Token Queue Read Register 4 (RO) */
 237 #define FFEMPTYMSK  DEV_REG(0x34) /** Device IN EPs empty Inr. Mask Register */
 238
 239 #define DCTL_rmtwkupsig                 (1 << 0) /** Remote Wakeup */
 240 #define DCTL_sftdiscon                  (1 << 1) /** Soft Disconnect */
 241 #define DCTL_gnpinnaksts                (1 << 2) /** Global Non-Periodic IN NAK Status */
 242 #define DCTL_goutnaksts                 (1 << 3) /** Global OUT NAK Status */
 243 #define DCTL_tstctl_bit_pos             4 /** Test Control */
 244 #define DCTL_tstctl_bits                (0x7 << DCTL_tstctl_bit_pos)
 245 #define DCTL_sgnpinnak                  (1 << 7) /** Set Global Non-Periodic IN NAK */
 246 #define DCTL_cgnpinnak                  (1 << 8) /** Clear Global Non-Periodic IN NAK */
 247 #define DCTL_sgoutnak                   (1 << 9) /** Set Global OUT NAK */
 248 #define DCTL_cgoutnak                   (1 << 10) /** Clear Global OUT NAK */
 249 /* "documented" in constants.h only */
 250 #define DCTL_pwronprgdone               (1 << 11) /** Power on Program Done ? */
 251
 252 #define DCFG_devspd_bits                0x3 /** Device Speed */
 253 #define DCFG_devspd_hs_phy_hs           0 /** High speed PHY running at high speed */
 254 #define DCFG_devspd_hs_phy_fs           1 /** High speed PHY running at full speed */
 255 #define DCFG_nzstsouthshk               (1 << 2) /** Non Zero Length Status OUT Handshake */
 256 #define DCFG_devadr_bit_pos             4 /** Device Address */
 257 #define DCFG_devadr_bits                (0x7f << DCFG_devadr_bit_pos)
 258 #define DCFG_perfrint_bit_pos           11 /** Periodic Frame Interval */
 259 #define DCFG_perfrint_bits              (0x3 << DCFG_perfrint_bit_pos)
 260 #define DCFG_FRAME_INTERVAL_80          0
 261 #define DCFG_FRAME_INTERVAL_85          1
 262 #define DCFG_FRAME_INTERVAL_90          2
 263 #define DCFG_FRAME_INTERVAL_95          3
 264
 265 #define DSTS_suspsts                    (1 << 0) /** Suspend status */
 266 #define DSTS_enumspd_bit_pos            1 /** Enumerated speed */
 267 #define DSTS_enumspd_bits               (0x3 << DSTS_enumspd_bit_pos)
 268 #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
 269 #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
 270 #define DSTS_ENUMSPD_LS_PHY_6MHZ           2
 271 #define DSTS_ENUMSPD_FS_PHY_48MHZ          3
 272 #define DSTS_errticerr                  (1 << 3) /** Erratic errors ? */
 273 #define DSTS_soffn_bit_pos              7 /** Frame or Microframe Number of the received SOF */
 274 #define DSTS_soffn_bits                 (0x3fff << DSTS_soffn_bit_pos)
 275
 276 #define DTHRCTL_non_iso_thr_en          (1 << 0)
 277 #define DTHRCTL_iso_thr_en              (1 << 1)
 278 #define DTHRCTL_tx_thr_len_bit_pos      2
 279 #define DTHRCTL_tx_thr_len_bits         (0x1FF << DTHRCTL_tx_thr_len_bit_pos)
 280 #define DTHRCTL_rx_thr_en               (1 << 16)
 281 #define DTHRCTL_rx_thr_len_bit_pos      17
 282 #define DTHRCTL_rx_thr_len_bits         (0x1FF << DTHRCTL_rx_thr_len_bit_pos)
 283
 284 /* 0<=ep<=15, you can use ep=0 */
 285 /** Device IN Endpoint (ep) Control Register */
 286 #define DIEPCTL(ep)     DEV_REG(0x100 + (ep) * 0x20)
 287 /** Device IN Endpoint (ep) Interrupt Register */
 288 #define DIEPINT(ep)     DEV_REG(0x100 + (ep) * 0x20 + 0x8)
 289 /** Device IN Endpoint (ep) Transfer Size Register */
 290 #define DIEPTSIZ(ep)    DEV_REG(0x100 + (ep) * 0x20 + 0x10)
 291 /** Device IN Endpoint (ep) DMA Address Register */
 292 #define DIEPDMA(ep)     DEV_REG(0x100 + (ep) * 0x20 + 0x14)
 293 /** Device IN Endpoint (ep) Transmit FIFO Status Register */
 294 #define DTXFSTS(ep)     DEV_REG(0x100 + (ep) * 0x20 + 0x18)
 295
 296 /* the following also apply to DIEPMSK */
 297 #define DIEPINT_xfercompl       (1 << 0) /** Transfer complete */
 298 #define DIEPINT_epdisabled      (1 << 1) /** Endpoint disabled */
 299 #define DIEPINT_ahberr          (1 << 2) /** AHB error */
 300 #define DIEPINT_timeout         (1 << 3) /** Timeout handshake (non-iso TX) */
 301 #define DIEPINT_intktxfemp      (1 << 4) /** IN token received with tx fifo empty */
 302 #define DIEPINT_intknepmis      (1 << 5) /** IN token received with ep mismatch */
 303 #define DIEPINT_inepnakeff      (1 << 6) /** IN endpoint NAK effective */
 304 #define DIEPINT_emptyintr       (1 << 7) /** linux doc broken on this, empty fifo ? */
 305 #define DIEPINT_txfifoundrn     (1 << 8) /** linux doc void on this, tx fifo underrun ? */
 306
 307 /* the following also apply to DOEPMSK */
 308 #define DOEPINT_xfercompl       (1 << 0) /** Transfer complete */
 309 #define DOEPINT_epdisabled      (1 << 1) /** Endpoint disabled */
 310 #define DOEPINT_ahberr          (1 << 2) /** AHB error */
 311 #define DOEPINT_setup           (1 << 3) /** Setup Phase Done (control EPs)*/
 312
 313 /* 0<=ep<=15, you can use ep=0 */
 314 /** Device OUT Endpoint (ep) Control Register */
 315 #define DOEPCTL(ep)     DEV_REG(0x300 + (ep) * 0x20)
 316 /** Device OUT Endpoint (ep) Frame number Register */
 317 #define DOEPFN(ep)      DEV_REG(0x300 + (ep) * 0x20 + 0x4)
 318 /** Device Endpoint (ep) Interrupt Register */
 319 #define DOEPINT(ep)     DEV_REG(0x300 + (ep) * 0x20 + 0x8)
 320 /** Device OUT Endpoint (ep) Transfer Size Register */
 321 #define DOEPTSIZ(ep)    DEV_REG(0x300 + (ep) * 0x20 + 0x10)
 322 /** Device Endpoint (ep) DMA Address Register */
 323 #define DOEPDMA(ep)     DEV_REG(0x300 + (ep) * 0x20 + 0x14)
 324
 325 #define PCGCCTL         BASE_REG(0xE00) /** Power and Clock Gating Control Register */
 326
 327
 328 /** Maximum Packet Size
 329  * IN/OUT EPn
 330  * IN/OUT EP0 - 2 bits
 331  *  2'b00: 64 Bytes
 332  *  2'b01: 32
 333  *  2'b10: 16
 334  *  2'b11: 8 */
 335 #define DEPCTL_mps_bits         0x7ff
 336 #define DEPCTL_mps_bit_pos      0
 337 #define DEPCTL_MPS_64           0
 338 #define DEPCTL_MPS_32           1
 339 #define DEPCTL_MPS_16           2
 340 #define DEPCTL_MPS_8            3
 341 /** Next Endpoint
 342  * IN EPn/IN EP0
 343  * OUT EPn/OUT EP0 - reserved */
 344 #define DEPCTL_nextep_bit_pos   11
 345 #define DEPCTL_nextep_bits      (0xf << DEPCTL_nextep_bit_pos)
 346 #define DEPCTL_usbactep         (1 << 15) /** USB Active Endpoint */
 347 /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
 348  * This field contains the PID of the packet going to
 349  * be received or transmitted on this endpoint. The
 350  * application should program the PID of the first
 351  * packet going to be received or transmitted on this
 352  * endpoint , after the endpoint is
 353  * activated. Application use the SetD1PID and
 354  * SetD0PID fields of this register to program either
 355  * D0 or D1 PID.
 356  *
 357  * The encoding for this field is
 358  * - 0: D0
 359  * - 1: D1
 360  */
 361 #define DEPCTL_dpid             (1 << 16)
 362 #define DEPCTL_naksts           (1 << 17) /** NAK Status */
 363 /** Endpoint Type
 364  *  2'b00: Control
 365  *  2'b01: Isochronous
 366  *  2'b10: Bulk
 367  *  2'b11: Interrupt */
 368 #define DEPCTL_eptype_bit_pos   18
 369 #define DEPCTL_eptype_bits      (0x3 << DEPCTL_eptype_bit_pos)
 370 /** Snoop Mode
 371  * OUT EPn/OUT EP0
 372  * IN EPn/IN EP0 - reserved */
 373 #define DEPCTL_snp              (1 << 20)
 374 #define DEPCTL_stall            (1 << 21) /** Stall Handshake */
 375 /** Tx Fifo Number
 376  * IN EPn/IN EP0
 377  * OUT EPn/OUT EP0 - reserved */
 378 #define DEPCTL_txfnum_bit_pos   22
 379 #define DEPCTL_txfnum_bits      (0xf << DEPCTL_txfnum_bit_pos)
 380
 381 #define DEPCTL_cnak             (1 << 26) /** Clear NAK */
 382 #define DEPCTL_snak             (1 << 27) /** Set NAK */
 383 /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
 384  * Writing to this field sets the Endpoint DPID (DPID)
 385  * field in this register to DATA0. Set Even
 386  * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
 387  * Writing to this field sets the Even/Odd
 388  * (micro)frame (EO_FrNum) field to even (micro)
 389  * frame.
 390  */
 391 #define DEPCTL_setd0pid         (1 << 28)
 392 /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
 393  * Writing to this field sets the Endpoint DPID (DPID)
 394  * field in this register to DATA1 Set Odd
 395  * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
 396  * Writing to this field sets the Even/Odd
 397  * (micro)frame (EO_FrNum) field to odd (micro) frame.
 398  */
 399 #define DEPCTL_setd1pid         (1 << 29)
 400 #define DEPCTL_epdis            (1 << 30) /** Endpoint disable */
 401 #define DEPCTL_epena            (1 << 31) /** Endpoint enable */
 402
 403
 404 /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */
 405 #define DEPTSIZ_xfersize_bits   0x7ffff /** Transfer Size */
 406 #define DEPTSIZ_pkcnt_bit_pos   19 /** Packet Count */
 407 #define DEPTSIZ_pkcnt_bits      (0x3ff << DEPTSIZ_pkcnt_bit_pos)
 408 #define DEPTSIZ_mc_bit_pos      29 /** Multi Count - Periodic IN endpoints */
 409 #define DEPTSIZ_mc_bits         (0x3 << DEPTSIZ_mc_bit_pos)
 410
 411 /* idem but for i=0 */
 412 #define DEPTSIZ0_xfersize_bits   0x7f /** Transfer Size */
 413 #define DEPTSIZ0_pkcnt_bit_pos   19 /** Packet Count */
 414 #define DEPTSIZ0_pkcnt_bits      (0x1 << DEPTSIZ0_pkcnt_bit_pos)
 415 #define DEPTSIZ0_supcnt_bit_pos  29 /** Setup Packet Count (DOEPTSIZ0 Only) */
 416 #define DEPTSIZ0_supcnt_bits     (0x3 << DEPTSIZ0_supcnt_bit_pos)
 417
 418 /* valid for DAINT and DAINTMSK, for 0<=ep<=15 */
 419 #define DAINT_IN_EP(i)      (1 << (i))
 420 #define DAINT_OUT_EP(i)     (1 << ((i) + 16))
 421
 422 /**
 423  * Parameters
 424  */
 425 #define USE_CUSTOM_FIFO_LAYOUT
 426
 427 #ifdef USE_CUSTOM_FIFO_LAYOUT
 428 /* Data fifo: includes RX fifo, non period TX fifo and periodic fifos
 429  * NOTE: this is a hardware parameter, it cannot be changed ! */
 430 #define DATA_FIFO_DEPTH     0x535
 431 /* size of the FX fifo */
 432 #define RX_FIFO_SIZE        0x100
 433 /* size of the non periodic TX fifo */
 434 #define NPTX_FIFO_SIZE      0x100
 435 /* size of each TX ep fifo size */
 436 #define EPTX_FIFO_SIZE      0x100
 437 #endif /* USE_CUSTOM_FIFO_LAYOUT */
 438
 439 /* Number of IN/OUT endpoints */
 440 #define NUM_IN_EP           3
 441 #define NUM_OUT_EP          2
 442
 443 /* List of IN enpoints */
 444 #define IN_EP_LIST          1, 3, 5
 445 #define OUT_EP_LIST         2, 4
 446
 447 #endif /* __USB_DRV_AS3525v2_H__ */