firmware/target/arm/as3525/sd-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 /* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
  24
  25 #include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
  26 #include "fat.h"
  27 #include "thread.h"
  28 #include "led.h"
  29 #include "sdmmc.h"
  30 #include "system.h"
  31 #include "cpu.h"
  32 #include <stdio.h>
  33 #include <stdlib.h>
  34 #include <string.h>
  35 #include "as3525.h"
  36 #include "pl180.h"  /* SD controller */
  37 #include "pl081.h"  /* DMA controller */
  38 #include "dma-target.h" /* DMA request lines */
  39 #include "clock-target.h"
  40 #include "panic.h"
  41 #ifdef HAVE_BUTTON_LIGHT
  42 #include "backlight-target.h"
  43 #endif
  44 #include "stdbool.h"
  45 #include "ata_idle_notify.h"
  46 #include "sd.h"
  47 #include "usb.h"
  48
  49 #ifdef HAVE_HOTSWAP
  50 #include "disk.h"
  51 #endif
  52
  53 /* command flags */
  54 #define MCI_NO_FLAGS    (0<<0)
  55 #define MCI_RESP        (1<<0)
  56 #define MCI_LONG_RESP   (1<<1)
  57 #define MCI_ARG         (1<<2)
  58
  59 /* ARM PL180 registers */
  60 #define MCI_POWER(i)       (*(volatile unsigned char *) (pl180_base[i]+0x00))
  61 #define MCI_CLOCK(i)       (*(volatile unsigned long *) (pl180_base[i]+0x04))
  62 #define MCI_ARGUMENT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x08))
  63 #define MCI_COMMAND(i)     (*(volatile unsigned long *) (pl180_base[i]+0x0C))
  64 #define MCI_RESPCMD(i)     (*(volatile unsigned long *) (pl180_base[i]+0x10))
  65 #define MCI_RESP0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x14))
  66 #define MCI_RESP1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x18))
  67 #define MCI_RESP2(i)       (*(volatile unsigned long *) (pl180_base[i]+0x1C))
  68 #define MCI_RESP3(i)       (*(volatile unsigned long *) (pl180_base[i]+0x20))
  69 #define MCI_DATA_TIMER(i)  (*(volatile unsigned long *) (pl180_base[i]+0x24))
  70 #define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
  71 #define MCI_DATA_CTRL(i)   (*(volatile unsigned char *) (pl180_base[i]+0x2C))
  72 #define MCI_DATA_CNT(i)    (*(volatile unsigned short*) (pl180_base[i]+0x30))
  73 #define MCI_STATUS(i)      (*(volatile unsigned long *) (pl180_base[i]+0x34))
  74 #define MCI_CLEAR(i)       (*(volatile unsigned long *) (pl180_base[i]+0x38))
  75 #define MCI_MASK0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x3C))
  76 #define MCI_MASK1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x40))
  77 #define MCI_SELECT(i)      (*(volatile unsigned long *) (pl180_base[i]+0x44))
  78 #define MCI_FIFO_CNT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x48))
  79
  80 #define MCI_DATA_ERROR    \
  81     ( MCI_DATA_CRC_FAIL   \
  82     | MCI_DATA_TIMEOUT    \
  83     | MCI_TX_UNDERRUN     \
  84     | MCI_RX_OVERRUN      \
  85     | MCI_START_BIT_ERR)
  86
  87 #define MCI_RESPONSE_ERROR    \
  88     ( MCI_CMD_TIMEOUT         \
  89     | MCI_CMD_CRC_FAIL)
  90
  91 #define MCI_FIFO(i)        ((unsigned long *) (pl180_base[i]+0x80))
  92 /* volumes */
  93 #define     INTERNAL_AS3525 0   /* embedded SD card */
  94 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  95
  96 static const int pl180_base[NUM_DRIVES] = {
  97             NAND_FLASH_BASE
  98 #ifdef HAVE_MULTIDRIVE
  99             , SD_MCI_BASE
 100 #endif
 101 };
 102
 103 static int sd_wait_for_tran_state(const int drive);
 104 static int sd_select_bank(signed char bank);
 105 static int sd_init_card(const int drive);
 106 static void init_pl180_controller(const int drive);
 107
 108 #define BLOCKS_PER_BANK 0x7a7800u
 109
 110 static tCardInfo card_info[NUM_DRIVES];
 111
 112 /* maximum timeouts recommanded in the SD Specification v2.00 */
 113 #define SD_MAX_READ_TIMEOUT     ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
 114 #define SD_MAX_WRITE_TIMEOUT    ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
 115
 116 /* for compatibility */
 117 static long last_disk_activity = -1;
 118
 119 #define MIN_YIELD_PERIOD 5  /* ticks */
 120 static long next_yield = 0;
 121
 122 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 123 static const char         sd_thread_name[] = "ata/sd";
 124 static struct mutex       sd_mtx;
 125 static struct event_queue sd_queue;
 126 #ifndef BOOTLOADER
 127 bool sd_enabled = false;
 128 #endif
 129
 130 #if defined(HAVE_MULTIDRIVE)
 131 static bool hs_card = false;
 132 #define EXT_SD_BITS (1<<2)
 133 #endif
 134
 135 static struct wakeup transfer_completion_signal;
 136 static volatile unsigned int transfer_error[NUM_VOLUMES];
 137 #define PL180_MAX_TRANSFER_ERRORS 10
 138
 139 #define UNALIGNED_NUM_SECTORS 10
 140 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 141 static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
 142
 143
 144 static inline void mci_delay(void) { udelay(1000) ; }
 145
 146
 147 static inline bool card_detect_target(void)
 148 {
 149 #if defined(HAVE_MULTIDRIVE)
 150     return !(GPIOA_PIN(2));
 151 #else
 152     return false;
 153 #endif
 154 }
 155
 156
 157 #ifdef HAVE_HOTSWAP
 158 static int sd1_oneshot_callback(struct timeout *tmo)
 159 {
 160     (void)tmo;
 161
 162     /* This is called only if the state was stable for 300ms - check state
 163      * and post appropriate event. */
 164     if (card_detect_target())
 165     {
 166         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 167     }
 168     else
 169         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 170
 171     return 0;
 172 }
 173
 174 void sd_gpioa_isr(void)
 175 {
 176     static struct timeout sd1_oneshot;
 177     if (GPIOA_MIS & EXT_SD_BITS)
 178         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 179     /* acknowledge interrupt */
 180     GPIOA_IC = EXT_SD_BITS;
 181 }
 182 #endif  /* HAVE_HOTSWAP */
 183
 184 void INT_NAND(void)
 185 {
 186     const int status = MCI_STATUS(INTERNAL_AS3525);
 187
 188     transfer_error[INTERNAL_AS3525] = status & MCI_DATA_ERROR;
 189
 190     wakeup_signal(&transfer_completion_signal);
 191     MCI_CLEAR(INTERNAL_AS3525) = status;
 192 }
 193
 194 #ifdef HAVE_MULTIDRIVE
 195 void INT_MCI0(void)
 196 {
 197     const int status = MCI_STATUS(SD_SLOT_AS3525);
 198
 199     transfer_error[SD_SLOT_AS3525] = status & MCI_DATA_ERROR;
 200
 201     wakeup_signal(&transfer_completion_signal);
 202     MCI_CLEAR(SD_SLOT_AS3525) = status;
 203 }
 204 #endif
 205
 206 static bool send_cmd(const int drive, const int cmd, const int arg,
 207                      const int flags, long *response)
 208 {
 209     int status;
 210
 211     unsigned cmd_retries = 6;
 212     while(cmd_retries--)
 213     {
 214         /* Clear old status flags */
 215         MCI_CLEAR(drive) = 0x7ff;
 216
 217         /* Load command argument or clear if none */
 218         MCI_ARGUMENT(drive) = (flags & MCI_ARG) ? arg : 0;
 219
 220         /* Construct MCI_COMMAND & enable CPSM */
 221         MCI_COMMAND(drive) =
 222            /*b0:5*/  cmd
 223            /* b6 */| ((flags & (MCI_RESP|MCI_LONG_RESP)) ? MCI_COMMAND_RESPONSE : 0)
 224            /* b7 */| ((flags & MCI_LONG_RESP) ? MCI_COMMAND_LONG_RESPONSE : 0)
 225            /* b8   | MCI_COMMAND_INTERRUPT */
 226            /* b9   | MCI_COMMAND_PENDING */  /*Only used with stream data transfer*/
 227            /* b10*/| MCI_COMMAND_ENABLE;     /* Enables CPSM */
 228
 229         /* Wait while cmd completes then disable CPSM */
 230         while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);
 231         MCI_COMMAND(drive) = 0;
 232
 233         status = MCI_STATUS(drive);
 234
 235         /*  Handle command responses */
 236         if(flags & MCI_RESP)                /* CMD expects response */
 237         {
 238             response[0] = MCI_RESP0(drive); /* Always prepare short response */
 239
 240             if(status & MCI_RESPONSE_ERROR) /* timeout or crc failure */
 241                 continue;
 242
 243             if(status & MCI_CMD_RESP_END)   /* Response passed CRC check */
 244             {
 245                 if(flags & MCI_LONG_RESP)
 246                 {   /* response[0] has already been read */
 247                     response[1] = MCI_RESP1(drive);
 248                     response[2] = MCI_RESP2(drive);
 249                     response[3] = MCI_RESP3(drive);
 250                 }
 251                 return true;
 252             }
 253         }
 254         else if(status & MCI_CMD_SENT)  /* CMD sent, no response required */
 255             return true;
 256     }
 257
 258     return false;
 259 }
 260
 261 #define MCI_FULLSPEED     (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS)     /* MCLK   */
 262 #define MCI_HALFSPEED     (MCI_CLOCK_ENABLE)                        /* MCLK/2 */
 263 #define MCI_QUARTERSPEED  (MCI_CLOCK_ENABLE | 1)                    /* MCLK/4 */
 264 #define MCI_IDENTSPEED    (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV)  /* IDENT  */
 265
 266 static int sd_init_card(const int drive)
 267 {
 268     unsigned long response;
 269     long init_timeout;
 270     bool sd_v2 = false;
 271
 272     /* MCLCK on and set to 400kHz ident frequency  */
 273     MCI_CLOCK(drive) = MCI_IDENTSPEED;
 274
 275     /* 100 - 400kHz clock required for Identification Mode  */
 276     /*  Start of Card Identification Mode ************************************/
 277
 278     /* CMD0 Go Idle  */
 279     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_FLAGS, NULL))
 280         return -1;
 281     mci_delay();
 282
 283     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 284       Non v2 cards will not respond to this command*/
 285     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP|MCI_ARG, &response))
 286         if((response & 0xFFF) == 0x1AA)
 287             sd_v2 = true;
 288
 289     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 290     init_timeout = current_tick + HZ;
 291
 292     do {
 293         /* this timeout is the only valid error for this loop*/
 294         if(TIME_AFTER(current_tick, init_timeout))
 295             return -2;
 296
 297         /* app_cmd */
 298         send_cmd(drive, SD_APP_CMD, 0, MCI_RESP|MCI_ARG, &response);
 299
 300         /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 301         send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 302                         MCI_RESP|MCI_ARG, &card_info[drive].ocr);
 303
 304     } while(!(card_info[drive].ocr & (1<<31)));
 305
 306     /* CMD2 send CID */
 307     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP|MCI_ARG,
 308                             card_info[drive].cid))
 309         return -3;
 310
 311     /* CMD3 send RCA */
 312     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP|MCI_ARG,
 313                 &card_info[drive].rca))
 314         return -4;
 315
 316     /*  End of Card Identification Mode   ************************************/
 317
 318 #ifdef HAVE_MULTIDRIVE        /*  The internal SDs are v1 */
 319
 320     /* Try to switch V2 cards to HS timings, non HS seem to ignore this */
 321     if(sd_v2)
 322     {
 323         /*  CMD7 w/rca: Select card to put it in TRAN state */
 324         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
 325             return -5;
 326         mci_delay();
 327
 328         if(sd_wait_for_tran_state(drive))
 329             return -6;
 330         /* CMD6 */
 331         if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_ARG, NULL))
 332             return -7;
 333         mci_delay();
 334
 335         /*  go back to STBY state so we can read csd */
 336         /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 337         if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_ARG, NULL))
 338             return -8;
 339         mci_delay();
 340     }
 341 #endif /*  HAVE_MULTIDRIVE  */
 342
 343     /* CMD9 send CSD */
 344     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 345                  MCI_RESP|MCI_LONG_RESP|MCI_ARG, card_info[drive].csd))
 346         return -9;
 347
 348     sd_parse_csd(&card_info[drive]);
 349
 350 #if defined(HAVE_MULTIDRIVE)
 351     hs_card = (card_info[drive].speed == 50000000);
 352 #endif
 353
 354     /* Boost MCICLK to operating speed */
 355     if(drive == INTERNAL_AS3525)
 356         MCI_CLOCK(drive) = MCI_HALFSPEED;  /* MCICLK = IDE_CLK/2 = 25 MHz  */
 357 #if defined(HAVE_MULTIDRIVE)
 358     else
 359         /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
 360         MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
 361 #endif
 362
 363     /*  CMD7 w/rca: Select card to put it in TRAN state */
 364     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
 365         return -10;
 366     mci_delay();
 367
 368     /*
 369      * enable bank switching
 370      * without issuing this command, we only have access to 1/4 of the blocks
 371      * of the first bank (0x1E9E00 blocks, which is the size reported in the
 372      * CSD register)
 373      */
 374     if(drive == INTERNAL_AS3525)
 375     {
 376         const int ret = sd_select_bank(-1);
 377         if(ret < 0)
 378             return ret -16;
 379
 380         /*  CMD7 w/rca = 0: Select card to put it in STBY state */
 381         if(!send_cmd(drive, SD_SELECT_CARD, 0, MCI_ARG, NULL))
 382             return -17;
 383         mci_delay();
 384
 385         /* CMD9 send CSD again, so we got the correct number of blocks */
 386         if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 387                      MCI_RESP|MCI_LONG_RESP|MCI_ARG, card_info[drive].csd))
 388             return -18;
 389
 390         sd_parse_csd(&card_info[drive]);
 391         /* The OF is stored in the first blocks */
 392         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
 393
 394         /*  CMD7 w/rca: Select card to put it in TRAN state */
 395         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
 396             return -19;
 397         mci_delay();
 398     }
 399
 400     card_info[drive].initialized = 1;
 401
 402     return 0;
 403 }
 404
 405 static void sd_thread(void) __attribute__((noreturn));
 406 static void sd_thread(void)
 407 {
 408     struct queue_event ev;
 409     bool idle_notified = false;
 410
 411     while (1)
 412     {
 413         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 414
 415         switch ( ev.id )
 416         {
 417 #ifdef HAVE_HOTSWAP
 418         case SYS_HOTSWAP_INSERTED:
 419         case SYS_HOTSWAP_EXTRACTED:
 420         {
 421             int microsd_init = 1;
 422             fat_lock();          /* lock-out FAT activity first -
 423                                     prevent deadlocking via disk_mount that
 424                                     would cause a reverse-order attempt with
 425                                     another thread */
 426             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 427                                     into driver that bypass the fat cache */
 428
 429             /* We now have exclusive control of fat cache and ata */
 430
 431             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 432                                     descriptors aren't leaked and any busy
 433                                     ones are invalid if mounting */
 434
 435             /* Force card init for new card, re-init for re-inserted one or
 436              * clear if the last attempt to init failed with an error. */
 437             card_info[SD_SLOT_AS3525].initialized = 0;
 438
 439             if (ev.id == SYS_HOTSWAP_INSERTED)
 440             {
 441                 sd_enable(true);
 442                 init_pl180_controller(SD_SLOT_AS3525);
 443                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 444                 if (microsd_init < 0) /* initialisation failed */
 445                     panicf("microSD init failed : %d", microsd_init);
 446
 447                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 448             }
 449
 450             /*
 451              * Mount succeeded, or this was an EXTRACTED event,
 452              * in both cases notify the system about the changed filesystems
 453              */
 454             if (microsd_init)
 455                 queue_broadcast(SYS_FS_CHANGED, 0);
 456
 457             /* Access is now safe */
 458             mutex_unlock(&sd_mtx);
 459             fat_unlock();
 460             sd_enable(false);
 461         }
 462             break;
 463 #endif
 464         case SYS_TIMEOUT:
 465             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 466             {
 467                 idle_notified = false;
 468             }
 469             else
 470             {
 471                 /* never let a timer wrap confuse us */
 472                 next_yield = current_tick;
 473
 474                 if (!idle_notified)
 475                 {
 476                     call_storage_idle_notifys(false);
 477                     idle_notified = true;
 478                 }
 479             }
 480             break;
 481
 482         case SYS_USB_CONNECTED:
 483             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 484             /* Wait until the USB cable is extracted again */
 485             usb_wait_for_disconnect(&sd_queue);
 486
 487             break;
 488         case SYS_USB_DISCONNECTED:
 489             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 490             break;
 491         }
 492     }
 493 }
 494
 495 static void init_pl180_controller(const int drive)
 496 {
 497     MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;
 498     MCI_CLEAR(drive) = 0x7ff;
 499
 500     MCI_MASK0(drive) = MCI_DATA_ERROR | MCI_DATA_END;
 501     MCI_MASK1(drive) = 0;
 502 #ifdef HAVE_MULTIDRIVE
 503     VIC_INT_ENABLE =
 504         (drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
 505     /* clear previous irq */
 506     GPIOA_IC = EXT_SD_BITS;
 507     /* enable edge detecting */
 508     GPIOA_IS &= ~EXT_SD_BITS;
 509     /* detect both raising and falling edges */
 510     GPIOA_IBE |= EXT_SD_BITS;
 511
 512 #else
 513     VIC_INT_ENABLE = INTERRUPT_NAND;
 514 #endif
 515
 516     MCI_POWER(drive) = MCI_POWER_UP | (MCI_VDD_3_0);  /*  OF Setting  */
 517     mci_delay();
 518
 519     MCI_POWER(drive) |= MCI_POWER_ON;
 520     mci_delay();
 521
 522     MCI_SELECT(drive) = 0;
 523
 524     /* Pl180 clocks get turned on at start of card init */
 525 }
 526
 527 int sd_init(void)
 528 {
 529     int ret;
 530     CGU_IDE =   (1<<6)                  /*  enable non AHB interface*/
 531             |   (AS3525_IDE_DIV << 2)
 532             |    AS3525_CLK_PLLA;       /* clock source = PLLA */
 533
 534     CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
 535 #ifdef HAVE_MULTIDRIVE
 536     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 537     CCU_IO &= ~(1<<3);           /* bits 3:2 = 01, xpd is SD interface */
 538     CCU_IO |= (1<<2);
 539 #endif
 540
 541     wakeup_init(&transfer_completion_signal);
 542
 543     init_pl180_controller(INTERNAL_AS3525);
 544     ret = sd_init_card(INTERNAL_AS3525);
 545     if(ret < 0)
 546         return ret;
 547 #ifdef HAVE_MULTIDRIVE
 548     init_pl180_controller(SD_SLOT_AS3525);
 549 #endif
 550
 551     /* init mutex */
 552     mutex_init(&sd_mtx);
 553
 554     queue_init(&sd_queue, true);
 555     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 556             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 557
 558 #ifndef BOOTLOADER
 559     sd_enabled = true;
 560     sd_enable(false);
 561 #endif
 562     return 0;
 563 }
 564
 565 #ifdef HAVE_HOTSWAP
 566 bool sd_removable(IF_MD_NONVOID(int drive))
 567 {
 568     return (drive==1);
 569 }
 570
 571 bool sd_present(IF_MD_NONVOID(int drive))
 572 {
 573     return (drive == 0) ? true : card_detect_target();
 574 }
 575 #endif /* HAVE_HOTSWAP */
 576
 577 static int sd_wait_for_tran_state(const int drive)
 578 {
 579     unsigned long response = 0;
 580     unsigned int timeout = current_tick + 5 * HZ;
 581
 582     while (1)
 583     {
 584         if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca,
 585                     MCI_RESP|MCI_ARG, &response))
 586             return -1;
 587
 588         if (((response >> 9) & 0xf) == SD_TRAN)
 589             return 0;
 590
 591         if(TIME_AFTER(current_tick, timeout))
 592             return -2;
 593
 594         if (TIME_AFTER(current_tick, next_yield))
 595         {
 596             yield();
 597             next_yield = current_tick + MIN_YIELD_PERIOD;
 598         }
 599     }
 600 }
 601
 602 static int sd_select_bank(signed char bank)
 603 {
 604     int ret;
 605     unsigned loops = 0;
 606
 607     memset(uncached_buffer, 0, 512);
 608     if(bank == -1)
 609     {   /* enable bank switching */
 610         uncached_buffer[0] = 16;
 611         uncached_buffer[1] = 1;
 612         uncached_buffer[2] = 10;
 613     }
 614     else
 615         uncached_buffer[0] = bank;
 616
 617     do {
 618         if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 619             panicf("SD bank %d error : 0x%x", bank,
 620                     transfer_error[INTERNAL_AS3525]);
 621
 622         ret = sd_wait_for_tran_state(INTERNAL_AS3525);
 623         if (ret < 0)
 624             return ret - 2;
 625
 626         if(!send_cmd(INTERNAL_AS3525, SD_SWITCH_FUNC, 0x80ffffef, MCI_ARG, NULL))
 627             return -1;
 628
 629         mci_delay();
 630
 631         if(!send_cmd(INTERNAL_AS3525, 35, 0, MCI_NO_FLAGS, NULL))
 632             return -2;
 633
 634         mci_delay();
 635
 636         dma_retain();
 637         /* we don't use the uncached buffer here, because we need the
 638          * physical memory address for DMA transfers */
 639         dma_enable_channel(0, aligned_buffer, MCI_FIFO(INTERNAL_AS3525),
 640             DMA_PERI_SD, DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8,
 641             NULL);
 642
 643         MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT;
 644         MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
 645         MCI_DATA_CTRL(INTERNAL_AS3525) =  (1<<0) /* enable */   |
 646                                 (0<<1) /* transfer direction */ |
 647                                 (1<<3) /* DMA */                |
 648                                 (9<<4) /* 2^9 = 512 */ ;
 649
 650         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 651         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 652
 653         /*  Wait for FIFO to empty, card may still be in PRG state  */
 654         while(MCI_STATUS(INTERNAL_AS3525) & MCI_TX_ACTIVE );
 655
 656         dma_release();
 657
 658     } while(transfer_error[INTERNAL_AS3525]);
 659
 660     card_info[INTERNAL_AS3525].current_bank = (bank == -1) ? 0 : bank;
 661
 662     return 0;
 663 }
 664
 665 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 666                                int count, void* buf, const bool write)
 667 {
 668 #ifndef HAVE_MULTIDRIVE
 669     const int drive = 0;
 670 #endif
 671     int ret = 0;
 672     unsigned loops = 0;
 673
 674     mutex_lock(&sd_mtx);
 675 #ifndef BOOTLOADER
 676     sd_enable(true);
 677     led(true);
 678 #endif
 679
 680     if (card_info[drive].initialized <= 0)
 681     {
 682         ret = sd_init_card(drive);
 683         if (!(card_info[drive].initialized))
 684             goto sd_transfer_error;
 685     }
 686
 687     if(count < 0) /* XXX: why is it signed ? */
 688     {
 689         ret = -20;
 690         goto sd_transfer_error;
 691     }
 692     if((start+count) > card_info[drive].numblocks)
 693     {
 694         ret = -21;
 695         goto sd_transfer_error;
 696     }
 697
 698     /* skip SanDisk OF */
 699     if (drive == INTERNAL_AS3525)
 700         start += AMS_OF_SIZE;
 701
 702     last_disk_activity = current_tick;
 703
 704     dma_retain();
 705
 706     while(count)
 707     {
 708         /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
 709          * register, so we have to transfer maximum 127 sectors at a time. */
 710         unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
 711         void *dma_buf;
 712         const int cmd =
 713             write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 714         unsigned long bank_start = start;
 715
 716         /* Only switch banks for internal storage */
 717         if(drive == INTERNAL_AS3525)
 718         {
 719             unsigned int bank = 0;
 720             while(bank_start >= BLOCKS_PER_BANK)
 721             {
 722                 bank_start -= BLOCKS_PER_BANK;
 723                 bank++;
 724             }
 725
 726             /* Switch bank if needed */
 727             if(card_info[INTERNAL_AS3525].current_bank != bank)
 728             {
 729                 ret = sd_select_bank(bank);
 730                 if (ret < 0)
 731                 {
 732                     ret -= 20;
 733                     goto sd_transfer_error;
 734                 }
 735             }
 736
 737             /* Do not cross a bank boundary in a single transfer loop */
 738             if((transfer + bank_start) > BLOCKS_PER_BANK)
 739                 transfer = BLOCKS_PER_BANK - bank_start;
 740         }
 741
 742         /* Set bank_start to the correct unit (blocks or bytes) */
 743         if(!(card_info[drive].ocr & (1<<30)))   /* not SDHC */
 744             bank_start *= SD_BLOCK_SIZE;
 745
 746         dma_buf = aligned_buffer;
 747         if(transfer > UNALIGNED_NUM_SECTORS)
 748             transfer = UNALIGNED_NUM_SECTORS;
 749
 750         if(write)
 751             memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 752
 753         ret = sd_wait_for_tran_state(drive);
 754         if (ret < 0)
 755         {
 756             ret -= 2*20;
 757             goto sd_transfer_error;
 758         }
 759
 760         if(!send_cmd(drive, cmd, bank_start, MCI_ARG, NULL))
 761         {
 762             ret -= 3*20;
 763             goto sd_transfer_error;
 764         }
 765
 766         if(write)
 767         {
 768             dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
 769                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 770                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 771
 772             /*Small delay for writes prevents data crc failures at lower freqs*/
 773 #ifdef HAVE_MULTIDRIVE
 774             if((drive == SD_SLOT_AS3525) && !hs_card)
 775             {
 776                 int write_delay = 125;
 777                 while(write_delay--);
 778             }
 779 #endif
 780         }
 781         else
 782             dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
 783                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 784                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 785
 786         MCI_DATA_TIMER(drive) = write ?
 787                 SD_MAX_WRITE_TIMEOUT : SD_MAX_READ_TIMEOUT;
 788         MCI_DATA_LENGTH(drive) = transfer * SD_BLOCK_SIZE;
 789         MCI_DATA_CTRL(drive) =  (1<<0) /* enable */                     |
 790                                 (!write<<1) /* transfer direction */    |
 791                                 (1<<3) /* DMA */                        |
 792                                 (9<<4) /* 2^9 = 512 */ ;
 793
 794         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 795         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 796
 797         /*  Wait for FIFO to empty, card may still be in PRG state for writes */
 798         while(MCI_STATUS(drive) & MCI_TX_ACTIVE);
 799
 800         last_disk_activity = current_tick;
 801
 802         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_FLAGS, NULL))
 803         {
 804             ret = -4*20;
 805             goto sd_transfer_error;
 806         }
 807
 808         if(!transfer_error[drive])
 809         {
 810             if(!write)
 811                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 812             buf += transfer * SD_BLOCK_SIZE;
 813             start += transfer;
 814             count -= transfer;
 815             loops = 0;  /* reset errors counter */
 816         }
 817         else if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 818                 panicf("SD Xfer %s err:0x%x Disk%d", (write? "write": "read"),
 819                                                   transfer_error[drive], drive);
 820     }
 821
 822 sd_transfer_error:
 823
 824     dma_release();
 825
 826 #ifndef BOOTLOADER
 827     led(false);
 828     sd_enable(false);
 829 #endif
 830
 831     if (ret)    /* error */
 832         card_info[drive].initialized = 0;
 833
 834     mutex_unlock(&sd_mtx);
 835     return ret;
 836 }
 837
 838 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 839                      void* buf)
 840 {
 841     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 842 }
 843
 844 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 845                      const void* buf)
 846 {
 847
 848 #ifdef BOOTLOADER /* we don't need write support in bootloader */
 849 #ifdef HAVE_MULTIDRIVE
 850     (void) drive;
 851 #endif
 852     (void) start;
 853     (void) count;
 854     (void) buf;
 855     return -1;
 856 #else
 857     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 858 #endif
 859 }
 860
 861 #ifndef BOOTLOADER
 862 long sd_last_disk_activity(void)
 863 {
 864     return last_disk_activity;
 865 }
 866
 867 void sd_enable(bool on)
 868 {
 869 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 870     extern int buttonlight_is_on;
 871 #endif
 872
 873 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 874     static bool cpu_boosted = false;
 875 #endif
 876
 877     if (sd_enabled == on)
 878         return; /* nothing to do */
 879
 880     sd_enabled = on;
 881
 882     if(on)
 883     {
 884 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 885         /* buttonlight AMSes need a bit of special handling for the buttonlight
 886          * here due to the dual mapping of GPIOD and XPD */
 887         CCU_IO |= (1<<2);              /* XPD is SD-MCI interface (b3:2 = 01) */
 888         if (buttonlight_is_on)
 889             GPIOD_DIR &= ~(1<<7);
 890         else
 891             _buttonlight_off();
 892 #endif
 893
 894 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 895         if(card_detect_target())  /* If SD card present Boost cpu for voltage */
 896         {
 897             cpu_boosted = true;
 898             cpu_boost(true);
 899         }
 900 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 901     }
 902     else
 903     {
 904 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 905         if(cpu_boosted)
 906         {
 907             cpu_boost(false);
 908             cpu_boosted = false;
 909         }
 910 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 911
 912 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 913         CCU_IO &= ~(1<<2);           /* XPD is general purpose IO (b3:2 = 00) */
 914         if (buttonlight_is_on)
 915             _buttonlight_on();
 916 #endif
 917     }
 918 }
 919
 920 tCardInfo *card_get_info_target(int card_no)
 921 {
 922     return &card_info[card_no];
 923 }
 924
 925 #ifdef HAVE_HOTSWAP
 926 void card_enable_monitoring_target(bool on)
 927 {
 928     if (on) /* enable interrupt */
 929         GPIOA_IE |= EXT_SD_BITS;
 930     else    /* disable interrupt */
 931         GPIOA_IE &= ~EXT_SD_BITS;
 932 }
 933 #endif /* HAVE_HOTSWAP */
 934
 935 #endif /* !BOOTLOADER */
 936
 937 #ifdef CONFIG_STORAGE_MULTI
 938 int sd_num_drives(int first_drive)
 939 {
 940     /* We don't care which logical drive number(s) we have been assigned */
 941     (void)first_drive;
 942
 943     return NUM_DRIVES;
 944 }
 945 #endif /* CONFIG_STORAGE_MULTI */