firmware/target/coldfire/iriver/system-iriver.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 by Linus Nielsen Feltzing
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "config.h"
  22 #include "cpu.h"
  23 #include "kernel.h"
  24 #include "system.h"
  25 #include "power.h"
  26 #include "timer.h"
  27 #include "pcf50606.h"
  28
  29 /* Settings for all possible clock frequencies (with properly working timers)
  30  * NOTE: Some 5249 chips don't like having PLLDIV set to 0. We must avoid that!
  31  *
  32  *                        xxx_REFRESH_TIMER below
  33  * system.h, CPUFREQ_xxx_MULT        |
  34  *              |                    |
  35  *              V                    V
  36  *                   PLLCR &    Refreshtim.                         IDECONFIG1/IDECONFIG2
  37  * CPUCLK/Hz  MULT ~0x70400000  16MB  32MB  CSCR0   CSCR1   CSCR3   CS2Pre CS2Post CS2Wait
  38  * ---------------------------------------------------------------------------------------
  39  *  11289600    1   0x00800200    4     1   0x0180  0x0180  0x0180     1      1       0
  40  *  22579200    2   0x0589e025   10     4   0x0180  0x0180  0x0180     1      1       0
  41  *  33868800    3   0x0388e025   15     7   0x0180  0x0180  0x0180     1      1       0
  42  *  45158400    4   0x0589e021   21    10   0x0580  0x0180  0x0580     1      1       0
  43  *  56448000    5   0x0289e025   26    12   0x0580  0x0580  0x0980     2      1       0
  44  *  67737600    6   0x0388e021   32    15   0x0980  0x0980  0x0d80     2      1       0
  45  *  79027200    7   0x038a6021   37    18   0x0980  0x0d80  0x1180     2      1       0
  46  *  90316800    8   0x038be021   43    21   0x0d80  0x0d80  0x1580     2      1       0
  47  * 101606400    9   0x01892025   48    23   0x0d80  0x1180  0x1980     2      1       0
  48  * 112896000   10   0x0189e025   54    26   0x1180  0x1580  0x1d80     3      1       0
  49  * 124185600   11   0x018ae025   59    29   0x1180  0x1580  0x2180     3      1       1
  50  */
  51
  52 #if MEM < 32
  53 #define MAX_REFRESH_TIMER     59
  54 #define NORMAL_REFRESH_TIMER  21
  55 #define DEFAULT_REFRESH_TIMER 4
  56 #else
  57 #define MAX_REFRESH_TIMER     29
  58 #define NORMAL_REFRESH_TIMER  10
  59 #define DEFAULT_REFRESH_TIMER 1
  60 #endif
  61
  62 #ifdef IRIVER_H300_SERIES
  63 #define RECALC_DELAYS(f) \
  64         pcf50606_i2c_recalc_delay(f)
  65 #else
  66 #define RECALC_DELAYS(f)
  67 #endif
  68
  69 #ifdef HAVE_SERIAL
  70 #define BAUD_RATE 57600
  71 #define BAUDRATE_DIV_DEFAULT (CPUFREQ_DEFAULT/(BAUD_RATE*32*2))
  72 #define BAUDRATE_DIV_NORMAL (CPUFREQ_NORMAL/(BAUD_RATE*32*2))
  73 #define BAUDRATE_DIV_MAX (CPUFREQ_MAX/(BAUD_RATE*32*2))
  74 #endif
  75
  76 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
  77 void set_cpu_frequency (long) __attribute__ ((section (".icode")));
  78 void set_cpu_frequency(long frequency)
  79 #else
  80 void cf_set_cpu_frequency (long) __attribute__ ((section (".icode")));
  81 void cf_set_cpu_frequency(long frequency)
  82 #endif
  83 {
  84     switch(frequency)
  85     {
  86     case CPUFREQ_MAX:
  87         DCR = (0x8200 | DEFAULT_REFRESH_TIMER);
  88               /* Refresh timer for bypass frequency */
  89         PLLCR &= ~1;  /* Bypass mode */
  90         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
  91         RECALC_DELAYS(CPUFREQ_MAX);
  92         PLLCR = 0x018ae025 | (PLLCR & 0x70400000);
  93         CSCR0 = 0x00001180; /* Flash: 4 wait states */
  94         CSCR1 = 0x00001580; /* LCD: 5 wait states */
  95 #if CONFIG_USBOTG == USBOTG_ISP1362
  96         CSCR3 = 0x00002180; /* USBOTG: 8 wait states */
  97 #endif
  98         while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
  99                                             This may take up to 10ms! */
 100         timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
 101         DCR = (0x8200 | MAX_REFRESH_TIMER);          /* Refresh timer */
 102         cpu_frequency = CPUFREQ_MAX;
 103         IDECONFIG1 = 0x10100000 | (1 << 13) | (3 << 10);
 104         /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
 105         IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
 106
 107 #ifdef HAVE_SERIAL
 108         UBG10 = BAUDRATE_DIV_MAX >> 8;
 109         UBG20 = BAUDRATE_DIV_MAX & 0xff;
 110 #endif
 111         break;
 112
 113     case CPUFREQ_NORMAL:
 114         DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
 115               /* Refresh timer for bypass frequency */
 116         PLLCR &= ~1;  /* Bypass mode */
 117         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
 118         RECALC_DELAYS(CPUFREQ_NORMAL);
 119         PLLCR = 0x0589e021 | (PLLCR & 0x70400000);
 120         CSCR0 = 0x00000580; /* Flash: 1 wait state */
 121         CSCR1 = 0x00000180; /* LCD: 0 wait states */
 122 #if CONFIG_USBOTG == USBOTG_ISP1362
 123         CSCR3 = 0x00000580; /* USBOTG: 1 wait state */
 124 #endif
 125         while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
 126                                             This may take up to 10ms! */
 127         timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
 128         DCR = (0x8000 | NORMAL_REFRESH_TIMER);       /* Refresh timer */
 129         cpu_frequency = CPUFREQ_NORMAL;
 130         IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10);
 131         /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
 132         IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
 133
 134 #ifdef HAVE_SERIAL
 135         UBG10 = BAUDRATE_DIV_NORMAL >> 8;
 136         UBG20 = BAUDRATE_DIV_NORMAL & 0xff;
 137 #endif
 138         break;
 139     default:
 140         DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
 141               /* Refresh timer for bypass frequency */
 142         PLLCR &= ~1;  /* Bypass mode */
 143         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
 144         RECALC_DELAYS(CPUFREQ_DEFAULT);
 145         /* Power down PLL, but keep CRSEL and CLSEL */
 146         PLLCR = 0x00800200 | (PLLCR & 0x70400000);
 147         CSCR0 = 0x00000180; /* Flash: 0 wait states */
 148         CSCR1 = 0x00000180; /* LCD: 0 wait states */
 149 #if CONFIG_USBOTG == USBOTG_ISP1362
 150         CSCR3 = 0x00000180; /* USBOTG: 0 wait states */
 151 #endif
 152         DCR = (0x8000 | DEFAULT_REFRESH_TIMER);       /* Refresh timer */
 153         cpu_frequency = CPUFREQ_DEFAULT;
 154         IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10);
 155         /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
 156         IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
 157
 158 #ifdef HAVE_SERIAL
 159         UBG10 = BAUDRATE_DIV_DEFAULT >> 8;
 160         UBG20 = BAUDRATE_DIV_DEFAULT & 0xff;
 161 #endif
 162         break;
 163     }
 164 }