firmware/export/pp5002.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2004 by Thom Johansen
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef __PP5002_H__
  22 #define __PP5002_H__
  23
  24 /* Much info gleaned and/or copied from the iPodLinux project. */
  25 #define DRAM_START       0x28000000
  26
  27 /* LCD bridge */
  28 #define LCD1_BASE        0xc0001000
  29
  30 #define LCD1_CONTROL     (*(volatile unsigned long *)(0xc0001000))
  31 #define LCD1_CMD         (*(volatile unsigned long *)(0xc0001008))
  32 #define LCD1_DATA        (*(volatile unsigned long *)(0xc0001010))
  33
  34 #define LCD1_BUSY_MASK   0x8000
  35
  36 /* I2S controller */
  37
  38 /* FIFO slot bits 7-0 are not implemented and so use of packed samples
  39  * appears to be impossible. */
  40 #define IISCONFIG        (*(volatile unsigned long *)(0xc0002500))
  41 #define IISFIFO_CFG      (*(volatile unsigned long *)(0xc000251c))
  42 #define IISFIFO_WR       (*(volatile unsigned long *)(0xc0002540))
  43 #define IISFIFO_RD       (*(volatile unsigned long *)(0xc0002580))
  44
  45 /**
  46  * IISCONFIG bits:
  47  * |   31   |   30   |   29   |   28   |   27   |   26   |   25   |   24   |
  48  * |        |        |        |        |        |        |        |        |
  49  * |   23   |   22   |   21   |   20   |   19   |   18   |   17   |   16   |
  50  * |        |        |        |        |        |        |        |        |
  51  * |   15   |   14   |   13   |   12   |   11   |   10   |    9   |    8   |
  52  * |        |        |        |        |        |        |        |        |
  53  * |    7   |    6   |    5   |    4   |    3   |    2   |    1   |    0   |
  54  * |   rw   |   rw   |   rw   |   MS   |   rw   |TXFENB# |   rw   |   ENB  |
  55  *
  56  * # No effect observed on iPod 3g
  57  */
  58 #define IIS_ENABLE        (1 << 0)
  59 #define IIS_TXFIFOEN      (1 << 2)
  60 #define IIS_MASTER        (1 << 4)
  61
  62 /**
  63  * IISFIFO_CFG bits:
  64  * |   31   |   30   |   29   |   28   |   27   |   26   |   25   |   24   |
  65  * |        |            RXFull[3:0]$           |       TXFree[3:1]        >
  66  * |   23   |   22   |   21   |   20   |   19   |   18   |   17   |   16   |
  67  * >TXFre[0]|        |        |        |        |        | RXCLR  | TXCLR  |
  68  * |   15   |   14   |   13   |   12   |   11   |   10   |    9   |    8   |
  69  * |   rw   |   rw   |   rw   |   rw   |   rw   |   rw   | IRQTX  |   rw   |
  70  * |    7*  |    6*  |    5*  |    4*  |    3   |    2   |    1   |    0   |
  71  * |RXEMPTY | RXSAFE | RXDNGR | RXFULL | TXFULL | TXSAFE | TXDNGR |TXEMPTY |
  72  *
  73  * $Could be RXFree
  74  * *Meaning isn't certain yet.
  75  * More concerted recording work will reveal.
  76  */
  77 #define IIS_IRQTX_REG     IISFIFO_CFG
  78 #define IIS_IRQRX_REG     IISFIFO_CFG
  79
  80 #define IIS_RX_FULL_MASK  (0xf << 27)
  81 #define IIS_RX_FULL_COUNT ((IISFIFO_CFG & IIS_RX_FULL_MASK) >> 27)
  82 #define IIS_TX_FREE_MASK  (0xf << 23) /* 0xf = 16 or 15 free */
  83 #define IIS_TX_FREE_COUNT ((IISFIFO_CFG & IIS_TX_FREE_MASK) >> 23)
  84 #define IIS_TX_IS_EMPTY   ((IISFIFO_CFG & IIS_TXEMPTY) != 0)
  85
  86 #define IIS_RXCLR         (1 << 17) /* Resets *could* be reversed */
  87 #define IIS_TXCLR         (1 << 16)
  88 #define IIS_IRQTX         (1 <<  9)
  89 #define IIS_TXFULL        (1 <<  3) /* All slots occupied */
  90 #define IIS_TXSAFE        (1 <<  2) /* FIFO >= 3/4 full */
  91 #define IIS_TXDANGER      (1 <<  1) /* FIFO <= 1/4 full */
  92 #define IIS_TXEMPTY       (1 <<  0) /* No samples in FIFO */
  93
  94 #define IIS_RXEMPTY       (1 <<  4) /* FIFO is empty */
  95
  96 #define IDE_BASE         0xc0003000
  97
  98 #define IDE_CFG_STATUS   (*(volatile unsigned long *)(0xc0003024))
  99
 100 #define USB_BASE         0xc0005000
 101
 102 #define I2C_BASE         0xc0008000
 103
 104 /* Processor ID */
 105 #define PROCESSOR_ID     (*(volatile unsigned long *)(0xc4000000))
 106
 107 #define PROC_ID_CPU      0x55
 108 #define PROC_ID_COP      0xaa
 109
 110 #define GPIOA_ENABLE     (*(volatile unsigned char *)(0xcf000000))
 111 #define GPIOB_ENABLE     (*(volatile unsigned char *)(0xcf000004))
 112 #define GPIOC_ENABLE     (*(volatile unsigned char *)(0xcf000008))
 113 #define GPIOD_ENABLE     (*(volatile unsigned char *)(0xcf00000c))
 114 #define GPIOA_OUTPUT_EN  (*(volatile unsigned char *)(0xcf000010))
 115 #define GPIOB_OUTPUT_EN  (*(volatile unsigned char *)(0xcf000014))
 116 #define GPIOC_OUTPUT_EN  (*(volatile unsigned char *)(0xcf000018))
 117 #define GPIOD_OUTPUT_EN  (*(volatile unsigned char *)(0xcf00001c))
 118 #define GPIOA_OUTPUT_VAL (*(volatile unsigned char *)(0xcf000020))
 119 #define GPIOB_OUTPUT_VAL (*(volatile unsigned char *)(0xcf000024))
 120 #define GPIOC_OUTPUT_VAL (*(volatile unsigned char *)(0xcf000028))
 121 #define GPIOD_OUTPUT_VAL (*(volatile unsigned char *)(0xcf00002c))
 122 #define GPIOA_INPUT_VAL  (*(volatile unsigned char *)(0xcf000030))
 123 #define GPIOB_INPUT_VAL  (*(volatile unsigned char *)(0xcf000034))
 124 #define GPIOC_INPUT_VAL  (*(volatile unsigned char *)(0xcf000038))
 125 #define GPIOD_INPUT_VAL  (*(volatile unsigned char *)(0xcf00003c))
 126 #define GPIOA_INT_STAT   (*(volatile unsigned char *)(0xcf000040))
 127 #define GPIOB_INT_STAT   (*(volatile unsigned char *)(0xcf000044))
 128 #define GPIOC_INT_STAT   (*(volatile unsigned char *)(0xcf000048))
 129 #define GPIOD_INT_STAT   (*(volatile unsigned char *)(0xcf00004c))
 130 #define GPIOA_INT_EN     (*(volatile unsigned char *)(0xcf000050))
 131 #define GPIOB_INT_EN     (*(volatile unsigned char *)(0xcf000054))
 132 #define GPIOC_INT_EN     (*(volatile unsigned char *)(0xcf000058))
 133 #define GPIOD_INT_EN     (*(volatile unsigned char *)(0xcf00005c))
 134 #define GPIOA_INT_LEV    (*(volatile unsigned char *)(0xcf000060))
 135 #define GPIOB_INT_LEV    (*(volatile unsigned char *)(0xcf000064))
 136 #define GPIOC_INT_LEV    (*(volatile unsigned char *)(0xcf000068))
 137 #define GPIOD_INT_LEV    (*(volatile unsigned char *)(0xcf00006c))
 138 #define GPIOA_INT_CLR    (*(volatile unsigned char *)(0xcf000070))
 139 #define GPIOB_INT_CLR    (*(volatile unsigned char *)(0xcf000074))
 140 #define GPIOC_INT_CLR    (*(volatile unsigned char *)(0xcf000078))
 141 #define GPIOD_INT_CLR    (*(volatile unsigned char *)(0xcf00007c))
 142
 143 #define CPU_INT_STAT     (*(volatile unsigned long *)(0xcf001000))
 144 #define COP_INT_STAT     (*(volatile unsigned long *)(0xcf001004))
 145 #define CPU_FIQ_STAT     (*(volatile unsigned long *)(0xcf001008))
 146 #define COP_FIQ_STAT     (*(volatile unsigned long *)(0xcf00100c))
 147
 148 #define INT_STAT         (*(volatile unsigned long *)(0xcf001010))
 149 #define INT_FORCED_STAT  (*(volatile unsigned long *)(0xcf001014))
 150 #define INT_FORCED_SET   (*(volatile unsigned long *)(0xcf001018))
 151 #define INT_FORCED_CLR   (*(volatile unsigned long *)(0xcf00101c))
 152
 153 #define CPU_INT_EN_STAT  (*(volatile unsigned long *)(0xcf001020))
 154 #define CPU_INT_EN       (*(volatile unsigned long *)(0xcf001024))
 155 #define CPU_INT_DIS      (*(volatile unsigned long *)(0xcf001028))
 156 #define CPU_INT_PRIORITY (*(volatile unsigned long *)(0xcf00102c))
 157
 158 #define COP_INT_EN_STAT  (*(volatile unsigned long *)(0xcf001030))
 159 #define COP_INT_EN       (*(volatile unsigned long *)(0xcf001034))
 160 #define COP_INT_DIS      (*(volatile unsigned long *)(0xcf001038))
 161 #define COP_INT_PRIORITY (*(volatile unsigned long *)(0xcf00103c))
 162
 163 #define IDE_IRQ          1
 164 #define SER0_IRQ         4
 165 #define I2S_IRQ          5
 166 #define SER1_IRQ         7
 167 #define TIMER1_IRQ      11
 168 #define TIMER2_IRQ      12
 169 #define GPIO_IRQ        14
 170 #define DMA_OUT_IRQ     30
 171 #define DMA_IN_IRQ      31
 172
 173 #define IDE_MASK         (1 << IDE_IRQ)
 174 #define SER0_MASK        (1 << SER0_IRQ)
 175 #define I2S_MASK         (1 << I2S_IRQ)
 176 #define SER1_MASK        (1 << SER1_IRQ)
 177 #define TIMER1_MASK      (1 << TIMER1_IRQ)
 178 #define TIMER2_MASK      (1 << TIMER2_IRQ)
 179 #define GPIO_MASK        (1 << GPIO_IRQ)
 180 #define DMA_OUT_MASK     (1 << DMA_OUT_IRQ)
 181 #define DMA_IN_MASK      (1 << DMA_IN_IRQ)
 182
 183 /* Yes, there is I2S_MASK but this cleans up the pcm code */
 184 #define IIS_MASK         DMA_OUT_MASK
 185
 186 #define TIMER1_CFG       (*(volatile unsigned long *)(0xcf001100))
 187 #define TIMER1_VAL       (*(volatile unsigned long *)(0xcf001104))
 188 #define TIMER2_CFG       (*(volatile unsigned long *)(0xcf001108))
 189 #define TIMER2_VAL       (*(volatile unsigned long *)(0xcf00110c))
 190
 191 #define USEC_TIMER       (*(volatile unsigned long *)(0xcf001110))
 192
 193 #define TIMING1_CTL      (*(volatile unsigned long *)(0xcf004000))
 194 #define TIMING2_CTL      (*(volatile unsigned long *)(0xcf004008))
 195
 196 #define PP_VER1          (*(volatile unsigned long *)(0xcf004030))
 197 #define PP_VER2          (*(volatile unsigned long *)(0xcf004034))
 198 #define PP_VER3          (*(volatile unsigned long *)(0xcf004038))
 199 #define PP_VER4          (*(volatile unsigned long *)(0xcf00403c))
 200
 201 /* Processors Control */
 202 #define PROC_STAT        (*(volatile unsigned long *)(0xcf004050))
 203 #define CPU_CTL          (*(volatile unsigned char *)(0xcf004054))
 204 #define COP_CTL          (*(volatile unsigned char *)(0xcf004058))
 205
 206 #define CPU_SLEEPING     0x8000
 207 #define COP_SLEEPING     0x4000
 208 #define PROC_SLEEPING(core) (0x8000 >> (core))
 209
 210 #define PROC_CTL(core)   ((&CPU_CTL)[(core)*4])
 211
 212 #define PROC_SLEEP       0xca
 213 #define PROC_WAKE        0xce
 214
 215 /* Cache Control */
 216 #define CACHE_CTL        (*(volatile unsigned long *)(0xcf004024))
 217 #define CACHE_RUN        0x1
 218 #define CACHE_INIT       0x2
 219
 220 #define CACHE_MASK       (*(volatile unsigned long *)(0xf000f020))
 221 #define CACHE_OPERATION  (*(volatile unsigned long *)(0xf000f024))
 222 #define CACHE_FLUSH_BASE (*(volatile unsigned long *)(0xf000c000))
 223 #define CACHE_INVALIDATE_BASE (*(volatile unsigned long *)(0xf0004000))
 224 #define CACHE_SIZE       0x2000  /* PP5002 has 8KB cache */
 225
 226 #define CACHE_OP_UNKNOWN1 (1<<11) /* 0x800 */
 227
 228 #define DEV_EN           (*(volatile unsigned long *)(0xcf005000))
 229 #define DEV_RS           (*(volatile unsigned long *)(0xcf005030))
 230
 231 #define DEV_I2C          (1<<8)
 232 #define DEV_I2S          (1<<7)
 233 #define DEV_USB          0x400000
 234
 235 #define CLOCK_ENABLE     (*(volatile unsigned long *)(0xcf005008))
 236 #define CLOCK_SOURCE     (*(volatile unsigned long *)(0xcf00500c))
 237 #define PLL_CONTROL      (*(volatile unsigned long *)(0xcf005010))
 238 #define PLL_DIV          (*(volatile unsigned long *)(0xcf005018))
 239 #define PLL_MULT         (*(volatile unsigned long *)(0xcf00501c))
 240 #define PLL_UNLOCK       (*(volatile unsigned long *)(0xcf005038))
 241
 242 #define MMAP0_LOGICAL    (*(volatile unsigned long *)(0xf000f000))
 243 #define MMAP0_PHYSICAL   (*(volatile unsigned long *)(0xf000f004))
 244 #define MMAP1_LOGICAL    (*(volatile unsigned long *)(0xf000f008))
 245 #define MMAP1_PHYSICAL   (*(volatile unsigned long *)(0xf000f00c))
 246 #define MMAP2_LOGICAL    (*(volatile unsigned long *)(0xf000f010))
 247 #define MMAP2_PHYSICAL   (*(volatile unsigned long *)(0xf000f014))
 248 #define MMAP3_LOGICAL    (*(volatile unsigned long *)(0xf000f018))
 249 #define MMAP3_PHYSICAL   (*(volatile unsigned long *)(0xf000f01c))
 250
 251 /* Timer frequency */
 252 /* Portalplayer chips use a microsecond timer. */
 253 #define TIMER_FREQ 1000000
 254
 255 #endif