firmware/target/arm/as3525/system-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by Rob Purchase
  11  * Copyright © 2008 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h"
  24 #include "kernel.h"
  25 #include "system.h"
  26 #include "panic.h"
  27 #include "ascodec-target.h"
  28 #include "adc.h"
  29 #include "dma-target.h"
  30 #include "clock-target.h"
  31 #include "fmradio_i2c.h"
  32 #include "button-target.h"
  33 #ifndef BOOTLOADER
  34 #include "mmu-arm.h"
  35 #endif
  36 #include "backlight-target.h"
  37
  38 #define default_interrupt(name) \
  39   extern __attribute__((weak,alias("UIRQ"))) void name (void)
  40
  41 void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
  42 void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
  43
  44 default_interrupt(INT_WATCHDOG);
  45 default_interrupt(INT_TIMER1);
  46 default_interrupt(INT_TIMER2);
  47 default_interrupt(INT_USB);
  48 default_interrupt(INT_DMAC);
  49 default_interrupt(INT_NAND);
  50 default_interrupt(INT_IDE);
  51 default_interrupt(INT_MCI0);
  52 default_interrupt(INT_MCI1);
  53 default_interrupt(INT_AUDIO);
  54 default_interrupt(INT_SSP);
  55 default_interrupt(INT_I2C_MS);
  56 default_interrupt(INT_I2C_AUDIO);
  57 default_interrupt(INT_I2SIN);
  58 default_interrupt(INT_I2SOUT);
  59 default_interrupt(INT_UART);
  60 default_interrupt(INT_GPIOD);
  61 default_interrupt(RESERVED1); /* Interrupt 17 : unused */
  62 default_interrupt(INT_CGU);
  63 default_interrupt(INT_MEMORY_STICK);
  64 default_interrupt(INT_DBOP);
  65 default_interrupt(RESERVED2); /* Interrupt 21 : unused */
  66 default_interrupt(RESERVED3); /* Interrupt 22 : unused */
  67 default_interrupt(RESERVED4); /* Interrupt 23 : unused */
  68 default_interrupt(RESERVED5); /* Interrupt 24 : unused */
  69 default_interrupt(RESERVED6); /* Interrupt 25 : unused */
  70 default_interrupt(RESERVED7); /* Interrupt 26 : unused */
  71 default_interrupt(RESERVED8); /* Interrupt 27 : unused */
  72 default_interrupt(RESERVED9); /* Interrupt 28 : unused */
  73 default_interrupt(INT_GPIOA);
  74 default_interrupt(INT_GPIOB);
  75 default_interrupt(INT_GPIOC);
  76
  77 static const char * const irqname[] =
  78 {
  79     "INT_WATCHDOG", "INT_TIMER1", "INT_TIMER2", "INT_USB", "INT_DMAC", "INT_NAND",
  80     "INT_IDE", "INT_MCI0", "INT_MCI1", "INT_AUDIO", "INT_SSP", "INT_I2C_MS",
  81     "INT_I2C_AUDIO", "INT_I2SIN", "INT_I2SOUT", "INT_UART", "INT_GPIOD", "RESERVED1",
  82     "INT_CGU", "INT_MEMORY_STICK", "INT_DBOP", "RESERVED2", "RESERVED3", "RESERVED4",
  83     "RESERVED5", "RESERVED6", "RESERVED7", "RESERVED8", "RESERVED9", "INT_GPIOA",
  84     "INT_GPIOB", "INT_GPIOC"
  85 };
  86
  87 static void UIRQ(void)
  88 {
  89     unsigned int irq_no = 0;
  90     int status = VIC_IRQ_STATUS;
  91
  92     if(status == 0)
  93         panicf("Unhandled IRQ (source unknown!)");
  94
  95     while((status >>= 1))
  96         irq_no++;
  97
  98     panicf("Unhandled IRQ %02X: %s", irq_no, irqname[irq_no]);
  99 }
 100
 101 struct vec_int_src
 102 {
 103     int source;
 104     void (*isr) (void);
 105 };
 106
 107 /* Vectored interrupts (16 available) */
 108 struct vec_int_src vec_int_srcs[] =
 109 {
 110     { INT_SRC_TIMER1, INT_TIMER1 },
 111     { INT_SRC_TIMER2, INT_TIMER2 },
 112     { INT_SRC_DMAC, INT_DMAC },
 113     { INT_SRC_NAND, INT_NAND },
 114     { INT_SRC_I2C_AUDIO, INT_I2C_AUDIO },
 115     { INT_SRC_AUDIO, INT_AUDIO },
 116 #if (defined HAVE_MULTIDRIVE  && CONFIG_CPU == AS3525)
 117     { INT_SRC_MCI0, INT_MCI0 },
 118 #endif
 119 #ifdef HAVE_HOTSWAP
 120     { INT_SRC_GPIOA, INT_GPIOA, },
 121 #endif
 122 #ifdef HAVE_RECORDING
 123     { INT_SRC_I2SIN, INT_I2SIN, },
 124 #endif
 125 };
 126
 127 static void setup_vic(void)
 128 {
 129     volatile unsigned long *vic_vect_addrs = VIC_VECT_ADDRS;
 130     volatile unsigned long *vic_vect_cntls = VIC_VECT_CNTLS;
 131     const unsigned int n = sizeof(vec_int_srcs)/sizeof(vec_int_srcs[0]);
 132     unsigned int i;
 133
 134     CGU_PERI |= CGU_VIC_CLOCK_ENABLE; /* enable VIC */
 135     VIC_INT_EN_CLEAR = 0xffffffff; /* disable all interrupt lines */
 136     VIC_INT_SELECT = 0; /* only IRQ, no FIQ */
 137
 138     VIC_DEF_VECT_ADDR = (unsigned long)UIRQ;
 139
 140     for(i = 0; i < n; i++)
 141     {
 142         vic_vect_addrs[i] = (unsigned long)vec_int_srcs[i].isr;
 143         vic_vect_cntls[i] = (1<<5) | vec_int_srcs[i].source;
 144     }
 145 }
 146
 147 void irq_handler(void)
 148 {
 149     asm volatile(   "stmfd  sp!, {r0-r5,ip,lr}      \n" /* Store context */
 150                     "ldr    r5, =0xC6010030         \n" /* VIC_VECT_ADDR */
 151                     "mov    lr, pc                  \n" /* Return from ISR */
 152                     "ldr    pc, [r5]                \n" /* execute ISR */
 153                     "str    r0, [r5]                \n" /* Ack interrupt */
 154                     "ldmfd  sp!, {r0-r5,ip,lr}      \n" /* Restore context */
 155                     "subs   pc, lr, #4              \n" /* Return from IRQ */
 156             );
 157 }
 158
 159 void fiq_handler(void)
 160 {
 161     asm volatile (
 162         "subs   pc, lr, #4   \r\n"
 163     );
 164 }
 165
 166 #if defined(SANSA_C200V2)
 167 #include "dbop-as3525.h"
 168
 169 int c200v2_variant = 0;
 170
 171 static void check_model_variant(void)
 172 {
 173     unsigned int i;
 174     unsigned int saved_dir = GPIOA_DIR;
 175
 176     /* Make A7 input */
 177     GPIOA_DIR &= ~(1<<7);
 178     /* wait a little to allow the pullup/pulldown resistor
 179      * to charge the input capacitance */
 180     for (i=0; i<1000; i++) asm volatile ("nop\n");
 181     /* read the pullup/pulldown value on A7 to determine the variant */
 182     if (GPIOA_PIN(7) == 0) {
 183         /*
 184          * Backlight on A7.
 185          */
 186         c200v2_variant = 1;
 187     } else {
 188         /*
 189          * Backlight on A5.
 190          */
 191         c200v2_variant = 0;
 192     }
 193     GPIOA_DIR = saved_dir;
 194 }
 195 #else
 196 static inline void check_model_variant(void)
 197 {
 198 }
 199 #endif /* SANSA_C200V2*/
 200
 201 #if defined(BOOTLOADER)
 202 static void sdram_delay(void)
 203 {
 204     int delay = 1024; /* arbitrary */
 205     while (delay--) ;
 206 }
 207
 208 /* Use the same initialization than OF */
 209 static void sdram_init(void)
 210 {
 211     CGU_PERI |= (CGU_EXTMEM_CLOCK_ENABLE|CGU_EXTMEMIF_CLOCK_ENABLE);
 212
 213     MPMC_CONTROL = 0x1; /* enable MPMC */
 214
 215     MPMC_DYNAMIC_CONTROL = 0x183; /* SDRAM NOP, all clocks high */
 216     sdram_delay();
 217
 218     MPMC_DYNAMIC_CONTROL = 0x103; /* SDRAM PALL, all clocks high */
 219     sdram_delay();
 220
 221     MPMC_DYNAMIC_REFRESH = 0x138; /* 0x138 * 16 HCLK ticks between SDRAM refresh cycles */
 222
 223     MPMC_CONFIG = 0; /* little endian, HCLK:MPMCCLKOUT[3:0] ratio = 1:1 */
 224
 225     if(MPMC_PERIPH_ID2 & 0xf0)
 226         MPMC_DYNAMIC_READ_CONFIG = 0x1; /* command delayed, clock out not delayed */
 227
 228     /* timings */
 229     MPMC_DYNAMIC_tRP    = 2;
 230     MPMC_DYNAMIC_tRAS   = 4;
 231     MPMC_DYNAMIC_tSREX  = 5;
 232     MPMC_DYNAMIC_tAPR   = 0;
 233     MPMC_DYNAMIC_tDAL   = 4;
 234     MPMC_DYNAMIC_tWR    = 2;
 235     MPMC_DYNAMIC_tRC    = 5;
 236     MPMC_DYNAMIC_tRFC   = 5;
 237     MPMC_DYNAMIC_tXSR   = 5;
 238     MPMC_DYNAMIC_tRRD   = 2;
 239     MPMC_DYNAMIC_tMRD   = 2;
 240
 241 #if defined(SANSA_CLIP) || defined(SANSA_M200V4) || defined(SANSA_C200V2)
 242 /* 16 bits external bus, low power SDRAM, 16 Mbits = 2 Mbytes */
 243 #define MEMORY_MODEL 0x21
 244
 245 #elif defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_CLIPV2) \
 246     || defined(SANSA_CLIPPLUS) || defined(SANSA_FUZEV2)
 247 /* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */
 248 #define MEMORY_MODEL 0x5
 249
 250 #else
 251 #error "The external memory in your player is unknown"
 252 #endif
 253
 254     MPMC_DYNAMIC_RASCAS_0 = (2<<8)|2; /* CAS & RAS latency = 2 clock cycles */
 255     MPMC_DYNAMIC_CONFIG_0 = (MEMORY_MODEL << 7);
 256
 257     MPMC_DYNAMIC_RASCAS_1 = MPMC_DYNAMIC_CONFIG_1 =
 258     MPMC_DYNAMIC_RASCAS_2 = MPMC_DYNAMIC_CONFIG_2 =
 259     MPMC_DYNAMIC_RASCAS_3 = MPMC_DYNAMIC_CONFIG_3 = 0;
 260
 261     MPMC_DYNAMIC_CONTROL = 0x82; /* SDRAM MODE, MPMCCLKOUT runs continuously */
 262
 263     /* program the SDRAM mode register */
 264     /* FIXME: details the exact settings of mode register */
 265     asm volatile(
 266         "ldr r4, [%0]\n"
 267         : : "p"(0x30000000+0x2300*MEM) : "r4");
 268
 269     MPMC_DYNAMIC_CONTROL = 0x2; /* SDRAM NORMAL, MPMCCLKOUT runs continuously */
 270
 271     MPMC_DYNAMIC_CONFIG_0 |= (1<<19); /* buffer enable */
 272 }
 273 #endif /* BOOTLOADER */
 274
 275 void system_init(void)
 276 {
 277 #if CONFIG_CPU == AS3525v2
 278     CCU_SRC = 0x57D7BF0;
 279 #else
 280     CCU_SRC = 0x1fffff0
 281         & ~CCU_SRC_IDE_EN; /* FIXME */
 282 #endif
 283
 284     unsigned int reset_loops = 640;
 285     while(reset_loops--)
 286         CCU_SRL = CCU_SRL_MAGIC_NUMBER;
 287     CCU_SRC = CCU_SRL = 0;
 288
 289     CCU_SCON = 1; /* AHB master's priority configuration :
 290                      TIC (Test Interface Controller) > DMA > USB > IDE > ARM */
 291
 292     CGU_PROC = 0;           /* fclk 24 MHz */
 293 #if CONFIG_CPU == AS3525v2
 294     /* pclk is always based on PLLA, since we don't know the current PLLA speed,
 295      * avoid having pclk too fast and hope it's not too low */
 296     CGU_PERI |= 0xf << 2;   /* pclk lowest */
 297 #else
 298     CGU_PERI &= ~0x7f;      /* pclk 24 MHz */
 299 #endif
 300
 301     /* bits 31:30 should be set to 0 in arm926-ejs */
 302     asm volatile(
 303         "mrc p15, 0, r0, c1, c0   \n"      /* control register */
 304         "bic r0, r0, #3<<30       \n"      /* clears bus bits : sets fastbus */
 305         "mcr p15, 0, r0, c1, c0   \n"
 306         : : : "r0" );
 307
 308     CGU_COUNTA = 0xff;
 309     CGU_PLLA = AS3525_PLLA_SETTING;
 310     CGU_PLLASUP = 0;        /* enable PLLA */
 311     while(!(CGU_INTCTRL & (1<<0)));           /* wait until PLLA is locked */
 312
 313 #if (AS3525_MCLK_SEL == AS3525_CLK_PLLB)
 314     CGU_COUNTB = 0xff;
 315     CGU_PLLB = AS3525_PLLB_SETTING;
 316     CGU_PLLBSUP = 0;        /* enable PLLB */
 317     while(!(CGU_INTCTRL & (1<<1)));           /* wait until PLLB is locked */
 318 #endif
 319
 320     /*  Set FCLK frequency */
 321     CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
 322                 (AS3525_FCLK_PREDIV  << 2) |
 323                  AS3525_FCLK_SEL);
 324
 325     /*  Set PCLK frequency */
 326     CGU_PERI = ((CGU_PERI & ~0x7F)  |       /* reset divider & clksel bits */
 327                  (AS3525_PCLK_DIV0 << 2) |
 328 #if CONFIG_CPU == AS3525
 329                  (AS3525_PCLK_DIV1 << 6) |
 330 #endif
 331                   AS3525_PCLK_SEL);
 332
 333 #ifdef BOOTLOADER
 334     sdram_init();
 335 #endif  /* BOOTLOADER */
 336
 337 #if 0 /* the GPIO clock is already enabled by the dualboot function */
 338     CGU_PERI |= CGU_GPIO_CLOCK_ENABLE;
 339 #endif
 340
 341     /* enable timer interface for TIMER1 & TIMER2 */
 342     CGU_PERI |= CGU_TIMERIF_CLOCK_ENABLE;
 343
 344     setup_vic();
 345
 346     dma_init();
 347
 348     ascodec_init();
 349
 350 #ifndef BOOTLOADER
 351     /*  Initialize power management settings */
 352     ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING);
 353 #if CONFIG_TUNER
 354     fmradio_i2c_init();
 355 #endif
 356 #endif /* !BOOTLOADER */
 357     check_model_variant();
 358 }
 359
 360 void system_reboot(void)
 361 {
 362     _backlight_off();
 363     /* use watchdog to reset */
 364     CGU_PERI |= (CGU_WDOCNT_CLOCK_ENABLE | CGU_WDOIF_CLOCK_ENABLE);
 365     WDT_LOAD = 1; /* set counter to 1 */
 366     WDT_CONTROL = 3; /* enable watchdog counter & reset */
 367     while(1);
 368 }
 369
 370 void system_exception_wait(void)
 371 {
 372     /* wait until button release (if a button is pressed) */
 373     while(button_read_device());
 374     /* then wait until next button press */
 375     while(!button_read_device());
 376 }
 377
 378 int system_memory_guard(int newmode)
 379 {
 380     (void)newmode;
 381     return 0;
 382 }
 383
 384 #ifndef BOOTLOADER
 385 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 386
 387 #if CONFIG_CPU == AS3525
 388 void set_cpu_frequency(long frequency)
 389 {
 390     if(frequency == CPUFREQ_MAX)
 391     {
 392 #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
 393         /* Increasing frequency so boost voltage before change */
 394         ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_20));
 395
 396         /* Some players run a bit low so use 1.175 volts instead of 1.20  */
 397         /* Wait for voltage to be at least 1.175v before making fclk > 200 MHz */
 398         while(adc_read(ADC_CVDD) < 470); /* 470 * .0025 = 1.175V */
 399 #endif  /*  HAVE_ADJUSTABLE_CPU_VOLTAGE */
 400
 401         asm volatile(
 402             "mrc p15, 0, r0, c1, c0  \n"
 403
 404 #ifdef ASYNCHRONOUS_BUS
 405             "orr r0, r0, #3<<30      \n"   /* asynchronous bus clocking */
 406 #else
 407             "bic r0, r0, #3<<30      \n"   /* clear bus bits */
 408             "orr r0, r0, #1<<30      \n"   /* synchronous bus clocking */
 409 #endif
 410
 411             "mcr p15, 0, r0, c1, c0  \n"
 412             : : : "r0" );
 413
 414         cpu_frequency = CPUFREQ_MAX;
 415     }
 416     else
 417     {
 418         asm volatile(
 419             "mrc p15, 0, r0, c1, c0  \n"
 420             "bic r0, r0, #3<<30      \n"     /* fastbus clocking */
 421             "mcr p15, 0, r0, c1, c0  \n"
 422             : : : "r0" );
 423
 424
 425 #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
 426         /* Decreasing frequency so reduce voltage after change */
 427         ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_10));
 428 #endif  /*  HAVE_ADJUSTABLE_CPU_VOLTAGE */
 429
 430         cpu_frequency = CPUFREQ_NORMAL;
 431     }
 432 }
 433 #else   /* as3525v2  */
 434 void set_cpu_frequency(long frequency)
 435 {
 436     int oldstatus = disable_irq_save();
 437     int delay;
 438
 439     if(frequency == CPUFREQ_MAX)
 440     {
 441         /* Change PCLK while FCLK is low, so it doesn't go too high */
 442         CGU_PERI = (CGU_PERI & ~(0x1F << 2)) | (AS3525_PCLK_DIV0 << 2);
 443
 444         delay = 40; while(delay--) asm("nop");
 445
 446         CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
 447                     (AS3525_FCLK_PREDIV  << 2) |
 448                     AS3525_FCLK_SEL);
 449
 450         delay = 40; while(delay--) asm("nop");
 451
 452     }
 453     else
 454     {
 455         frequency = CPUFREQ_NORMAL; /* We only have 2 settings */
 456
 457         CGU_PROC = ((AS3525_FCLK_POSTDIV_UNBOOSTED << 4) |
 458                     (AS3525_FCLK_PREDIV  << 2) |
 459                     AS3525_FCLK_SEL);
 460
 461         delay = 40; while(delay--) asm("nop");
 462
 463         /* Change PCLK after FCLK is low, so it doesn't go too high */
 464         CGU_PERI = (CGU_PERI & ~(0x1F << 2)) | (AS3525_PCLK_DIV0_UNBOOSTED << 2);
 465         delay = 40; while(delay--) asm("nop");
 466     }
 467
 468     cpu_frequency = frequency;
 469
 470     restore_irq(oldstatus);
 471 }
 472 #endif
 473
 474 #endif /* HAVE_ADJUSTABLE_CPU_FREQ */
 475 #endif /* !BOOTLOADER */