firmware/drivers/audio/wm8978.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2008 by Michael Sevakis
  11  *
  12  * Driver for WM8978 audio codec
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  20  * KIND, either express or implied.
  21  *
  22  ****************************************************************************/
  23 #include "config.h"
  24 #include "system.h"
  25 #include "audiohw.h"
  26 #include "wmcodec.h"
  27 #include "audio.h"
  28 /*#define LOGF_ENABLE*/
  29 #include "logf.h"
  30
  31 /* TODO: Define/refine an API for special hardware steps outside the
  32  * main codec driver such as special GPIO handling. */
  33 /* NOTE: Much of the volume code is very interdependent and calibrated for
  34  * the Gigabeat S. If you change anything for another device that uses this
  35  * file it may break things. */
  36 extern void audiohw_enable_headphone_jack(bool enable);
  37
  38 const struct sound_settings_info audiohw_settings[] =
  39 {
  40     [SOUND_VOLUME]             = {"dB", 0,   1, -90,   6, -25},
  41     [SOUND_BALANCE]            = {"%",  0,   1,-100, 100,   0},
  42     [SOUND_CHANNELS]           = {"",   0,   1,   0,   5,   0},
  43     [SOUND_STEREO_WIDTH]       = {"%",  0,   5,   0, 250, 100},
  44     [SOUND_EQ_BAND1_GAIN]      = {"dB", 0,   1, -12,  12,   0},
  45     [SOUND_EQ_BAND2_GAIN]      = {"dB", 0,   1, -12,  12,   0},
  46     [SOUND_EQ_BAND3_GAIN]      = {"dB", 0,   1, -12,  12,   0},
  47     [SOUND_EQ_BAND4_GAIN]      = {"dB", 0,   1, -12,  12,   0},
  48     [SOUND_EQ_BAND5_GAIN]      = {"dB", 0,   1, -12,  12,   0},
  49     [SOUND_EQ_BAND1_FREQUENCY] = {"",   0,   1,   0,   3,   0},
  50     [SOUND_EQ_BAND2_FREQUENCY] = {"",   0,   1,   0,   3,   0},
  51     [SOUND_EQ_BAND3_FREQUENCY] = {"",   0,   1,   0,   3,   0},
  52     [SOUND_EQ_BAND4_FREQUENCY] = {"",   0,   1,   0,   3,   0},
  53     [SOUND_EQ_BAND5_FREQUENCY] = {"",   0,   1,   0,   3,   0},
  54     [SOUND_EQ_BAND2_WIDTH]     = {"",   0,   1,   0,   1,   0},
  55     [SOUND_EQ_BAND3_WIDTH]     = {"",   0,   1,   0,   1,   0},
  56     [SOUND_EQ_BAND4_WIDTH]     = {"",   0,   1,   0,   1,   0},
  57     [SOUND_DEPTH_3D]           = {"%",  0,   1,   0,  15,   0},
  58 #ifdef HAVE_RECORDING
  59     /* Digital: -119.0dB to +8.0dB in 0.5dB increments
  60      * Analog:  Relegated to volume control
  61      * Circumstances unfortunately do not allow a great deal of positive
  62      * gain. */
  63     [SOUND_LEFT_GAIN]          = {"dB", 1,   1,-238,  16,   0},
  64     [SOUND_RIGHT_GAIN]         = {"dB", 1,   1,-238,  16,   0},
  65 #if 0
  66     [SOUND_MIC_GAIN]           = {"dB", 1,   1,-238,  16,   0},
  67 #endif
  68 #endif
  69 };
  70
  71 static uint16_t wmc_regs[WMC_NUM_REGISTERS] =
  72 {
  73     /* Initialized with post-reset default values - the 2-wire interface
  74      * cannot be read. Or-in additional bits desired for some registers. */
  75     [0 ... WMC_NUM_REGISTERS-1]   = 0x8000, /* To ID invalids in gaps */
  76     [WMC_SOFTWARE_RESET]          = 0x000,
  77     [WMC_POWER_MANAGEMENT1]       = 0x000,
  78     [WMC_POWER_MANAGEMENT2]       = 0x000,
  79     [WMC_POWER_MANAGEMENT3]       = 0x000,
  80     [WMC_AUDIO_INTERFACE]         = 0x050,
  81     [WMC_COMPANDING_CTRL]         = 0x000,
  82     [WMC_CLOCK_GEN_CTRL]          = 0x140,
  83     [WMC_ADDITIONAL_CTRL]         = 0x000,
  84     [WMC_GPIO]                    = 0x000,
  85     [WMC_JACK_DETECT_CONTROL1]    = 0x000,
  86     [WMC_DAC_CONTROL]             = 0x000,
  87     [WMC_LEFT_DAC_DIGITAL_VOL]    = 0x0ff, /* Latch left first */
  88     [WMC_RIGHT_DAC_DIGITAL_VOL]   = 0x0ff | WMC_VU,
  89     [WMC_JACK_DETECT_CONTROL2]    = 0x000,
  90     [WMC_ADC_CONTROL]             = 0x100,
  91     [WMC_LEFT_ADC_DIGITAL_VOL]    = 0x0ff, /* Latch left first */
  92     [WMC_RIGHT_ADC_DIGITAL_VOL]   = 0x0ff | WMC_VU,
  93     [WMC_EQ1_LOW_SHELF]           = 0x12c,
  94     [WMC_EQ2_PEAK1]               = 0x02c,
  95     [WMC_EQ3_PEAK2]               = 0x02c,
  96     [WMC_EQ4_PEAK3]               = 0x02c,
  97     [WMC_EQ5_HIGH_SHELF]          = 0x02c,
  98     [WMC_DAC_LIMITER1]            = 0x032,
  99     [WMC_DAC_LIMITER2]            = 0x000,
 100     [WMC_NOTCH_FILTER1]           = 0x000,
 101     [WMC_NOTCH_FILTER2]           = 0x000,
 102     [WMC_NOTCH_FILTER3]           = 0x000,
 103     [WMC_NOTCH_FILTER4]           = 0x000,
 104     [WMC_ALC_CONTROL1]            = 0x038,
 105     [WMC_ALC_CONTROL2]            = 0x00b,
 106     [WMC_ALC_CONTROL3]            = 0x032,
 107     [WMC_NOISE_GATE]              = 0x000,
 108     [WMC_PLL_N]                   = 0x008,
 109     [WMC_PLL_K1]                  = 0x00c,
 110     [WMC_PLL_K2]                  = 0x093,
 111     [WMC_PLL_K3]                  = 0x0e9,
 112     [WMC_3D_CONTROL]              = 0x000,
 113     [WMC_BEEP_CONTROL]            = 0x000,
 114     [WMC_INPUT_CTRL]              = 0x033,
 115     [WMC_LEFT_INP_PGA_GAIN_CTRL]  = 0x010 | WMC_ZC, /* Latch left first */
 116     [WMC_RIGHT_INP_PGA_GAIN_CTRL] = 0x010 | WMC_VU | WMC_ZC,
 117     [WMC_LEFT_ADC_BOOST_CTRL]     = 0x100,
 118     [WMC_RIGHT_ADC_BOOST_CTRL]    = 0x100,
 119     [WMC_OUTPUT_CTRL]             = 0x002,
 120     [WMC_LEFT_MIXER_CTRL]         = 0x001,
 121     [WMC_RIGHT_MIXER_CTRL]        = 0x001,
 122     [WMC_LOUT1_HP_VOLUME_CTRL]    = 0x039 | WMC_ZC, /* Latch left first */
 123     [WMC_ROUT1_HP_VOLUME_CTRL]    = 0x039 | WMC_VU | WMC_ZC,
 124     [WMC_LOUT2_SPK_VOLUME_CTRL]   = 0x039 | WMC_ZC, /* Latch left first */
 125     [WMC_ROUT2_SPK_VOLUME_CTRL]   = 0x039 | WMC_VU | WMC_ZC,
 126     [WMC_OUT3_MIXER_CTRL]         = 0x001,
 127     [WMC_OUT4_MONO_MIXER_CTRL]    = 0x001,
 128 };
 129
 130 struct
 131 {
 132     signed   char vol_l;
 133     signed   char vol_r;
 134     unsigned char dac_l;
 135     unsigned char dac_r;
 136     unsigned char ahw_mute;
 137     unsigned char prescaler;        /* Attenuation */
 138     unsigned char eq_on;            /* Enabled */
 139     signed   char band_gain[5];     /* Setting */
 140     unsigned char enh_3d_prescaler; /* Attenuation */
 141     unsigned char enh_3d_on;        /* Enabled */
 142     unsigned char enh_3d;           /* Setting */
 143 } wmc_vol =
 144 {
 145     .vol_l = 0,
 146     .vol_r = 0,
 147     .dac_l = 0,
 148     .dac_r = 0,
 149     .ahw_mute = false,
 150     .prescaler = 0,
 151     .eq_on = true,
 152     .band_gain = { 0, 0, 0, 0, 0 },
 153     .enh_3d_prescaler = 0,
 154     .enh_3d_on = true,
 155     .enh_3d   = 0,
 156 };
 157
 158 static void wmc_write(unsigned int reg, unsigned int val)
 159 {
 160     if (reg >= WMC_NUM_REGISTERS || (wmc_regs[reg] & 0x8000))
 161     {
 162         logf("wm8978 invalid register: %d", reg);
 163         return;
 164     }
 165
 166     wmc_regs[reg] = val & ~0x8000;
 167     wmcodec_write(reg, val);
 168 }
 169
 170 void wmc_set(unsigned int reg, unsigned int bits)
 171 {
 172     wmc_write(reg, wmc_regs[reg] | bits);
 173 }
 174
 175 void wmc_clear(unsigned int reg, unsigned int bits)
 176 {
 177     wmc_write(reg, wmc_regs[reg] & ~bits);
 178 }
 179
 180 static void wmc_write_masked(unsigned int reg, unsigned int bits,
 181                              unsigned int mask)
 182 {
 183     wmc_write(reg, (wmc_regs[reg] & ~mask) | (bits & mask));
 184 }
 185
 186 /* convert tenth of dB volume (-890..60) to master volume register value
 187  * (000000...111111) */
 188 int tenthdb2master(int db)
 189 {
 190     /* -90dB to +6dB 1dB steps (96 levels) 7bits */
 191     /* 1100000 ==  +6dB  (0x60,96)               */
 192     /* 1101010 ==   0dB  (0x5a,90)               */
 193     /* 1000001 == -57dB  (0x21,33,DAC)           */
 194     /* 0000001 == -89dB  (0x01,01)               */
 195     /* 0000000 == -90dB  (0x00,00,Mute)          */
 196     if (db <= VOLUME_MIN)
 197     {
 198         return 0x0;
 199     }
 200     else
 201     {
 202         return (db - VOLUME_MIN) / 10;
 203     }
 204 }
 205
 206 int sound_val2phys(int setting, int value)
 207 {
 208     int result;
 209
 210     switch (setting)
 211     {
 212 #ifdef HAVE_RECORDING
 213     case SOUND_LEFT_GAIN:
 214     case SOUND_RIGHT_GAIN:
 215     case SOUND_MIC_GAIN:
 216         result = value * 5;
 217         break;
 218 #endif
 219
 220     case SOUND_DEPTH_3D:
 221         result = (100 * value + 8) / 15;
 222         break;
 223
 224     default:
 225         result = value;
 226     }
 227
 228     return result;
 229 }
 230
 231 void audiohw_preinit(void)
 232 {
 233     /* 1. Turn on external power supplies. Wait for supply voltage to settle. */
 234
 235     /* Step 1 should be completed already. Reset and return all registers to
 236      * defaults */
 237     wmcodec_write(WMC_SOFTWARE_RESET, 0xff);
 238     sleep(HZ/10);
 239
 240     /* 2. Mute all analogue outputs */
 241     wmc_set(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
 242     wmc_set(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
 243     wmc_set(WMC_LOUT2_SPK_VOLUME_CTRL, WMC_MUTE);
 244     wmc_set(WMC_ROUT2_SPK_VOLUME_CTRL, WMC_MUTE);
 245     wmc_set(WMC_OUT3_MIXER_CTRL, WMC_MUTE);
 246     wmc_set(WMC_OUT4_MONO_MIXER_CTRL, WMC_MUTE);
 247
 248     /* 3. Set L/RMIXEN = 1 and DACENL/R = 1 in register R3. */
 249     wmc_write(WMC_POWER_MANAGEMENT3, WMC_RMIXEN | WMC_LMIXEN);
 250
 251     /* EQ and 3D applied to DAC (Set before DAC enable!) */
 252     wmc_set(WMC_EQ1_LOW_SHELF, WMC_EQ3DMODE);
 253
 254     wmc_set(WMC_POWER_MANAGEMENT3, WMC_DACENR | WMC_DACENL);
 255
 256     /* 4. Set BUFIOEN = 1 and VMIDSEL[1:0] to required value in register
 257      *    R1. Wait for VMID supply to settle */
 258     wmc_write(WMC_POWER_MANAGEMENT1, WMC_BUFIOEN | WMC_VMIDSEL_300K);
 259     sleep(HZ/10);
 260
 261     /* 5. Set BIASEN = 1 in register R1. */
 262     wmc_set(WMC_POWER_MANAGEMENT1, WMC_BIASEN);
 263
 264     /* 6. Set L/ROUTEN = 1 in register R2. */
 265     wmc_write(WMC_POWER_MANAGEMENT2, WMC_LOUT1EN | WMC_ROUT1EN);
 266 }
 267
 268 void audiohw_postinit(void)
 269 {
 270     sleep(5*HZ/4);
 271
 272     /* 7. Enable other mixers as required */
 273
 274     /* 8. Enable other outputs as required */
 275
 276     /* 9. Set remaining registers */
 277     wmc_write(WMC_AUDIO_INTERFACE, WMC_WL_16 | WMC_FMT_I2S);
 278     wmc_write(WMC_DAC_CONTROL, WMC_DACOSR_128 | WMC_AMUTE);
 279
 280     /* No ADC, no HP filter, no popping */
 281     wmc_clear(WMC_ADC_CONTROL, WMC_HPFEN);
 282
 283     wmc_clear(WMC_LEFT_ADC_BOOST_CTRL, WMC_PGABOOSTL);
 284     wmc_clear(WMC_RIGHT_ADC_BOOST_CTRL, WMC_PGABOOSTR);
 285
 286     /* Specific to HW clocking */
 287     wmc_write_masked(WMC_CLOCK_GEN_CTRL, WMC_BCLKDIV_4 | WMC_MS,
 288                      WMC_BCLKDIV | WMC_MS | WMC_CLKSEL);
 289     audiohw_set_frequency(HW_FREQ_DEFAULT);
 290
 291     audiohw_enable_headphone_jack(true);
 292 }
 293
 294 static void get_headphone_levels(int val, int *dac_p, int *hp_p,
 295                                  int *mix_p, int *boost_p)
 296 {
 297     int dac, hp, mix, boost;
 298
 299     if (val >= 33)
 300     {
 301         dac = 255;
 302         hp = val - 33;
 303         mix = 7;
 304         boost = 5;
 305     }
 306     else if (val >= 21)
 307     {
 308         dac = 189 + val / 3 * 6;
 309         hp = val % 3;
 310         mix = 7;
 311         boost = (val - 18) / 3;
 312     }
 313     else
 314     {
 315         dac = 189 + val / 3 * 6;
 316         hp = val % 3;
 317         mix = val / 3;
 318         boost = 1;
 319     }
 320
 321     *dac_p = dac;
 322     *hp_p = hp;
 323     *mix_p = mix;
 324     *boost_p = boost;
 325 }
 326
 327 static void sync_prescaler(void)
 328 {
 329     int prescaler = 0;
 330
 331     /* Combine all prescaling into a single DAC attenuation */
 332     if (wmc_vol.eq_on)
 333         prescaler = wmc_vol.prescaler * 2;
 334
 335     if (wmc_vol.enh_3d_on)
 336         prescaler += wmc_vol.enh_3d_prescaler;
 337
 338     wmc_write_masked(WMC_LEFT_DAC_DIGITAL_VOL, wmc_vol.dac_l - prescaler,
 339                      WMC_DVOL);
 340     wmc_write_masked(WMC_RIGHT_DAC_DIGITAL_VOL, wmc_vol.dac_r - prescaler,
 341                      WMC_DVOL);
 342 }
 343
 344 void audiohw_set_headphone_vol(int vol_l, int vol_r)
 345 {
 346     int prev_l = wmc_vol.vol_l;
 347     int prev_r = wmc_vol.vol_r;
 348     int dac_l, dac_r, hp_l, hp_r;
 349     int mix_l, mix_r, boost_l, boost_r;
 350
 351     wmc_vol.vol_l = vol_l;
 352     wmc_vol.vol_r = vol_r;
 353
 354     /* Mixers are synced to provide full volume range on both the analogue
 355      * and digital pathways */
 356     get_headphone_levels(vol_l, &dac_l, &hp_l, &mix_l, &boost_l);
 357     get_headphone_levels(vol_r, &dac_r, &hp_r, &mix_r, &boost_r);
 358
 359     wmc_vol.dac_l = dac_l;
 360     wmc_vol.dac_r = dac_r;
 361
 362     sync_prescaler();
 363
 364     wmc_write_masked(WMC_LEFT_MIXER_CTRL, mix_l << WMC_BYPLMIXVOL_POS,
 365                      WMC_BYPLMIXVOL);
 366     wmc_write_masked(WMC_LEFT_ADC_BOOST_CTRL,
 367                      boost_l << WMC_L2_2BOOSTVOL_POS, WMC_L2_2BOOSTVOL);
 368     wmc_write_masked(WMC_LOUT1_HP_VOLUME_CTRL, hp_l, WMC_AVOL);
 369
 370     wmc_write_masked(WMC_RIGHT_MIXER_CTRL, mix_r << WMC_BYPRMIXVOL_POS,
 371                      WMC_BYPRMIXVOL);
 372     wmc_write_masked(WMC_RIGHT_ADC_BOOST_CTRL,
 373                      boost_r << WMC_R2_2BOOSTVOL_POS, WMC_R2_2BOOSTVOL);
 374     wmc_write_masked(WMC_ROUT1_HP_VOLUME_CTRL, hp_r, WMC_AVOL);
 375
 376     if (vol_l > 0)
 377     {
 378         /* Not muted and going up from mute level? */
 379         if (prev_l <= 0 && !wmc_vol.ahw_mute)
 380             wmc_clear(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
 381     }
 382     else
 383     {
 384         /* Going to mute level? */
 385         if (prev_l > 0)
 386             wmc_set(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
 387     }
 388
 389     if (vol_r > 0)
 390     {
 391         /* Not muted and going up from mute level? */
 392         if (prev_r <= 0 && !wmc_vol.ahw_mute)
 393             wmc_clear(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
 394     }
 395     else
 396     {
 397         /* Going to mute level? */
 398         if (prev_r > 0)
 399             wmc_set(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
 400     }
 401 }
 402
 403 static void audiohw_mute(bool mute)
 404 {
 405     wmc_vol.ahw_mute = mute;
 406
 407     /* No DAC mute here, please - take care of each enabled output. */
 408     if (mute)
 409     {
 410         wmc_set(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
 411         wmc_set(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
 412     }
 413     else
 414     {
 415         /* Unmute outputs not at mute level */
 416         if (wmc_vol.vol_l > 0)
 417             wmc_clear(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
 418
 419         if (wmc_vol.vol_r > 0)
 420             wmc_clear(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
 421     }
 422 }
 423
 424 /* Equalizer - set the eq band level -12 to +12 dB. */
 425 void audiohw_set_eq_band_gain(unsigned int band, int val)
 426 {
 427     if (band > 4)
 428         return;
 429
 430     wmc_vol.band_gain[band] = val;
 431
 432     if (!wmc_vol.eq_on)
 433         val = 0;
 434
 435     wmc_write_masked(band + WMC_EQ1_LOW_SHELF, 12 - val, WMC_EQG);
 436 }
 437
 438 /* Equalizer - set the eq band frequency index. */
 439 void audiohw_set_eq_band_frequency(unsigned int band, int val)
 440 {
 441     if (band > 4)
 442         return;
 443
 444     wmc_write_masked(band + WMC_EQ1_LOW_SHELF,
 445                      val << WMC_EQC_POS, WMC_EQC);
 446 }
 447
 448 /* Equalizer - set bandwidth for peaking filters to wide (!= 0) or
 449  * narrow (0); only valid for peaking filter bands 1-3. */
 450 void audiohw_set_eq_band_width(unsigned int band, int val)
 451 {
 452     if (band < 1 || band > 3)
 453         return;
 454
 455     wmc_write_masked(band + WMC_EQ1_LOW_SHELF,
 456                      (val == 0) ? 0 : WMC_EQBW, WMC_EQBW);
 457 }
 458
 459 /* Set prescaler to prevent clipping the output amp when applying positive
 460  * gain to EQ bands. */
 461 void audiohw_set_prescaler(int val)
 462 {
 463     wmc_vol.prescaler = val;
 464     sync_prescaler();
 465 }
 466
 467 /* Set the depth of the 3D effect */
 468 void audiohw_set_depth_3d(int val)
 469 {
 470     wmc_vol.enh_3d_prescaler = 10*val / 15; /* -5 dB @ full setting */
 471     wmc_vol.enh_3d = val;
 472
 473     if (!wmc_vol.enh_3d_on)
 474         val = 0;
 475
 476     sync_prescaler();
 477     wmc_write_masked(WMC_3D_CONTROL, val, WMC_DEPTH3D);
 478 }
 479
 480 void audiohw_close(void)
 481 {
 482     /* 1. Mute all analogue outputs */
 483     audiohw_mute(true);
 484     audiohw_enable_headphone_jack(false);
 485
 486     /* 2. Disable power management register 1. R1 = 00 */
 487     wmc_write(WMC_POWER_MANAGEMENT1, 0x000);
 488
 489     /* 3. Disable power management register 2. R2 = 00 */
 490     wmc_write(WMC_POWER_MANAGEMENT2, 0x000);
 491
 492     /* 4. Disable power management register 3. R3 = 00 */
 493     wmc_write(WMC_POWER_MANAGEMENT3, 0x000);
 494
 495     /* 5. Remove external power supplies. */
 496 }
 497
 498 void audiohw_set_frequency(int fsel)
 499 {
 500     /* For 16.9344MHz MCLK, codec as master. */
 501     static const struct
 502     {
 503         uint32_t plln  : 8;
 504         uint32_t pllk1 : 6;
 505         uint32_t pllk2 : 9;
 506         uint32_t pllk3 : 9;
 507         unsigned char mclkdiv;
 508         unsigned char filter;
 509     } srctrl_table[HW_NUM_FREQ] =
 510     {
 511         [HW_FREQ_8] = /* PLL = 65.536MHz */
 512         {
 513             .plln    = 7 | WMC_PLL_PRESCALE,
 514             .pllk1   = 0x2f,            /* 12414886 */
 515             .pllk2   = 0x0b7,
 516             .pllk3   = 0x1a6,
 517             .mclkdiv = WMC_MCLKDIV_8,   /*  2.0480 MHz */
 518             .filter  = WMC_SR_8KHZ,
 519         },
 520         [HW_FREQ_11] = /* PLL = off */
 521         {
 522             .mclkdiv = WMC_MCLKDIV_6,   /*  2.8224 MHz */
 523             .filter  = WMC_SR_12KHZ,
 524         },
 525         [HW_FREQ_12] = /* PLL = 73.728 MHz */
 526         {
 527             .plln    = 8 | WMC_PLL_PRESCALE,
 528             .pllk1   = 0x2d,            /* 11869595 */
 529             .pllk2   = 0x08e,
 530             .pllk3   = 0x19b,
 531             .mclkdiv = WMC_MCLKDIV_6,   /*  3.0720 MHz */
 532             .filter  = WMC_SR_12KHZ,
 533         },
 534         [HW_FREQ_16] = /* PLL = 65.536MHz */
 535         {
 536             .plln    = 7 | WMC_PLL_PRESCALE,
 537             .pllk1   = 0x2f,            /* 12414886 */
 538             .pllk2   = 0x0b7,
 539             .pllk3   = 0x1a6,
 540             .mclkdiv = WMC_MCLKDIV_4,   /*  4.0960 MHz */
 541             .filter  = WMC_SR_16KHZ,
 542         },
 543         [HW_FREQ_22] = /* PLL = off */
 544         {
 545             .mclkdiv = WMC_MCLKDIV_3,   /*  5.6448 MHz */
 546             .filter  = WMC_SR_24KHZ,
 547         },
 548         [HW_FREQ_24] = /* PLL = 73.728 MHz */
 549         {
 550             .plln    = 8 | WMC_PLL_PRESCALE,
 551             .pllk1   = 0x2d,            /* 11869595 */
 552             .pllk2   = 0x08e,
 553             .pllk3   = 0x19b,
 554             .mclkdiv = WMC_MCLKDIV_3,   /*  6.1440 MHz */
 555             .filter  = WMC_SR_24KHZ,
 556         },
 557         [HW_FREQ_32] = /* PLL = 65.536MHz */
 558         {
 559             .plln    = 7 | WMC_PLL_PRESCALE,
 560             .pllk1   = 0x2f,            /* 12414886 */
 561             .pllk2   = 0x0b7,
 562             .pllk3   = 0x1a6,
 563             .mclkdiv = WMC_MCLKDIV_2,   /*  8.1920 MHz */
 564             .filter  = WMC_SR_32KHZ,
 565         },
 566         [HW_FREQ_44] = /* PLL = off */
 567         {
 568             .mclkdiv = WMC_MCLKDIV_1_5, /* 11.2896 MHz */
 569             .filter  = WMC_SR_48KHZ,
 570         },
 571         [HW_FREQ_48] = /* PLL = 73.728 MHz */
 572         {
 573             .plln    = 8 | WMC_PLL_PRESCALE,
 574             .pllk1   = 0x2d,            /* 11869595 */
 575             .pllk2   = 0x08e,
 576             .pllk3   = 0x19b,
 577             .mclkdiv = WMC_MCLKDIV_1_5, /* 12.2880 MHz */
 578             .filter  = WMC_SR_48KHZ,
 579         },
 580     };
 581
 582     unsigned int plln;
 583     unsigned int mclkdiv;
 584
 585     if ((unsigned)fsel >= HW_NUM_FREQ)
 586         fsel = HW_FREQ_DEFAULT;
 587
 588     /* Setup filters. */
 589     wmc_write(WMC_ADDITIONAL_CTRL, srctrl_table[fsel].filter);
 590
 591     plln = srctrl_table[fsel].plln;
 592     mclkdiv = srctrl_table[fsel].mclkdiv;
 593
 594     if (plln != 0)
 595     {
 596         /* Using PLL to generate SYSCLK */
 597
 598         /* Program PLL. */
 599         wmc_write(WMC_PLL_N, plln);
 600         wmc_write(WMC_PLL_K1, srctrl_table[fsel].pllk1);
 601         wmc_write(WMC_PLL_K2, srctrl_table[fsel].pllk2);
 602         wmc_write(WMC_PLL_K3, srctrl_table[fsel].pllk3);
 603
 604         /* Turn on PLL. */
 605         wmc_set(WMC_POWER_MANAGEMENT1, WMC_PLLEN);
 606
 607         /* Switch to PLL and set divider. */
 608         wmc_write_masked(WMC_CLOCK_GEN_CTRL, mclkdiv | WMC_CLKSEL,
 609                          WMC_MCLKDIV | WMC_CLKSEL);
 610     }
 611     else
 612     {
 613         /* Switch away from PLL and set MCLKDIV. */
 614         wmc_write_masked(WMC_CLOCK_GEN_CTRL, mclkdiv,
 615                          WMC_MCLKDIV | WMC_CLKSEL);
 616
 617         /* Turn off PLL. */
 618         wmc_clear(WMC_POWER_MANAGEMENT1, WMC_PLLEN);
 619     }
 620 }
 621
 622 void audiohw_enable_tone_controls(bool enable)
 623 {
 624     int i;
 625     wmc_vol.eq_on = enable;
 626     audiohw_set_prescaler(wmc_vol.prescaler);
 627
 628     for (i = 0; i < 5; i++)
 629         audiohw_set_eq_band_gain(i, wmc_vol.band_gain[i]);
 630 }
 631
 632 void audiohw_enable_depth_3d(bool enable)
 633 {
 634     wmc_vol.enh_3d_on = enable;
 635     audiohw_set_depth_3d(wmc_vol.enh_3d);
 636 }
 637
 638 #ifdef HAVE_RECORDING
 639 void audiohw_set_recsrc(int source, bool recording)
 640 {
 641     switch (source)
 642     {
 643     case AUDIO_SRC_PLAYBACK:
 644         /* Disable all audio paths but DAC */
 645         /* Disable ADCs */
 646         wmc_clear(WMC_ADC_CONTROL, WMC_HPFEN);
 647         wmc_clear(WMC_POWER_MANAGEMENT2, WMC_ADCENL | WMC_ADCENR);
 648         /* Disable bypass */
 649         wmc_clear(WMC_LEFT_MIXER_CTRL, WMC_BYPL2LMIX);
 650         wmc_clear(WMC_RIGHT_MIXER_CTRL, WMC_BYPR2RMIX);
 651         /* Disable IP BOOSTMIX and PGA */
 652         wmc_clear(WMC_POWER_MANAGEMENT2, WMC_INPPGAENL | WMC_INPPGAENR |
 653                   WMC_BOOSTENL | WMC_BOOSTENR);
 654         wmc_clear(WMC_INPUT_CTRL, WMC_L2_2INPPGA | WMC_R2_2INPPGA |
 655                                   WMC_LIP2INPPGA | WMC_RIP2INPPGA |
 656                                   WMC_LIN2INPPGA | WMC_RIN2INPPGA);
 657         wmc_clear(WMC_LEFT_ADC_BOOST_CTRL, WMC_PGABOOSTL);
 658         wmc_clear(WMC_RIGHT_ADC_BOOST_CTRL, WMC_PGABOOSTR);
 659         break;
 660
 661     case AUDIO_SRC_FMRADIO:
 662         if (recording)
 663         {
 664             /* Disable bypass */
 665             wmc_clear(WMC_LEFT_MIXER_CTRL, WMC_BYPL2LMIX);
 666             wmc_clear(WMC_RIGHT_MIXER_CTRL, WMC_BYPR2RMIX);
 667             /* Enable ADCs, IP BOOSTMIX and PGA, route L/R2 through PGA */
 668             wmc_set(WMC_POWER_MANAGEMENT2, WMC_ADCENL | WMC_ADCENR |
 669                     WMC_BOOSTENL | WMC_BOOSTENR | WMC_INPPGAENL |
 670                     WMC_INPPGAENR);
 671             wmc_set(WMC_ADC_CONTROL, WMC_ADCOSR | WMC_HPFEN);
 672             /* PGA at 0dB with +20dB boost */
 673             wmc_write_masked(WMC_LEFT_INP_PGA_GAIN_CTRL, 0x10, WMC_AVOL);
 674             wmc_write_masked(WMC_RIGHT_INP_PGA_GAIN_CTRL, 0x10, WMC_AVOL);
 675             wmc_set(WMC_LEFT_ADC_BOOST_CTRL, WMC_PGABOOSTL);
 676             wmc_set(WMC_RIGHT_ADC_BOOST_CTRL, WMC_PGABOOSTR);
 677             /* Connect L/R2 inputs to PGA */
 678             wmc_write_masked(WMC_INPUT_CTRL, WMC_L2_2INPPGA | WMC_R2_2INPPGA |
 679                                              WMC_LIN2INPPGA | WMC_RIN2INPPGA,
 680                                              WMC_L2_2INPPGA | WMC_R2_2INPPGA |
 681                                              WMC_LIP2INPPGA | WMC_RIP2INPPGA |
 682                                              WMC_LIN2INPPGA | WMC_RIN2INPPGA);
 683         }
 684         else
 685         {
 686             /* Disable PGA and ADC, enable IP BOOSTMIX, route L/R2 directly to
 687              * IP BOOSTMIX */
 688             wmc_clear(WMC_ADC_CONTROL, WMC_HPFEN);
 689             wmc_write_masked(WMC_POWER_MANAGEMENT2, WMC_BOOSTENL | WMC_BOOSTENR,
 690                 WMC_BOOSTENL | WMC_BOOSTENR | WMC_INPPGAENL |
 691                 WMC_INPPGAENR | WMC_ADCENL | WMC_ADCENR);
 692             wmc_clear(WMC_INPUT_CTRL, WMC_L2_2INPPGA | WMC_R2_2INPPGA |
 693                                       WMC_LIP2INPPGA | WMC_RIP2INPPGA |
 694                                       WMC_LIN2INPPGA | WMC_RIN2INPPGA);
 695             wmc_clear(WMC_LEFT_ADC_BOOST_CTRL, WMC_PGABOOSTL);
 696             wmc_clear(WMC_RIGHT_ADC_BOOST_CTRL, WMC_PGABOOSTR);
 697             /* Enable bypass to L/R mixers */
 698             wmc_set(WMC_LEFT_MIXER_CTRL, WMC_BYPL2LMIX);
 699             wmc_set(WMC_RIGHT_MIXER_CTRL, WMC_BYPR2RMIX);
 700         }
 701         break;
 702     }
 703 }
 704
 705 void audiohw_set_recvol(int left, int right, int type)
 706 {
 707     switch (type)
 708     {
 709     case AUDIO_GAIN_LINEIN:
 710         wmc_write_masked(WMC_LEFT_ADC_DIGITAL_VOL, left + 239, WMC_DVOL);
 711         wmc_write_masked(WMC_RIGHT_ADC_DIGITAL_VOL, right + 239, WMC_DVOL);
 712         return;
 713     }
 714 }
 715 #endif /* HAVE_RECORDING */