firmware/target/arm/imx31/mc13783-imx31.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (c) 2008 by Michael Sevakis
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "system.h"
  22 #include "cpu.h"
  23 #include "gpio-imx31.h"
  24 #include "mc13783.h"
  25 #include "mc13783-target.h"
  26 #include "debug.h"
  27 #include "kernel.h"
  28
  29 extern const struct mc13783_event mc13783_events[MC13783_NUM_EVENTS];
  30 extern struct spi_node mc13783_spi;
  31
  32 /* PMIC event service data */
  33 static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)];
  34 static const char *mc13783_thread_name = "pmic";
  35 static struct wakeup mc13783_svc_wake;
  36
  37 /* Synchronous thread communication objects */
  38 static struct mutex mc13783_spi_mutex;
  39 static struct wakeup mc13783_spi_wake;
  40
  41 /* Tracking for which interrupts are enabled */
  42 static uint32_t pmic_int_enabled[2] =
  43     { 0x00000000, 0x00000000 };
  44
  45 static const unsigned char pmic_intm_regs[2] =
  46     { MC13783_INTERRUPT_MASK0, MC13783_INTERRUPT_MASK1 };
  47
  48 static const unsigned char pmic_ints_regs[2] =
  49     { MC13783_INTERRUPT_STATUS0, MC13783_INTERRUPT_STATUS1 };
  50
  51 static volatile unsigned int mc13783_thread_id = 0;
  52
  53 static void mc13783_xfer_complete_cb(struct spi_transfer_desc *trans);
  54
  55 /* Transfer descriptor for synchronous reads and writes */
  56 static struct spi_transfer_desc mc13783_transfer =
  57 {
  58     .node = &mc13783_spi,
  59     .txbuf = NULL,
  60     .rxbuf = NULL,
  61     .count = 0,
  62     .callback = mc13783_xfer_complete_cb,
  63     .next = NULL,
  64 };
  65
  66 /* Called when a transfer is finished and data is ready/written */
  67 static void mc13783_xfer_complete_cb(struct spi_transfer_desc *xfer)
  68 {
  69     if (xfer->count != 0)
  70         return;
  71
  72     wakeup_signal(&mc13783_spi_wake);
  73 }
  74
  75 static inline bool wait_for_transfer_complete(void)
  76 {
  77     return wakeup_wait(&mc13783_spi_wake, HZ*2) == OBJ_WAIT_SUCCEEDED &&
  78            mc13783_transfer.count == 0;
  79 }
  80
  81 static void mc13783_interrupt_thread(void)
  82 {
  83     uint32_t pending[2];
  84
  85     /* Enable mc13783 GPIO event */
  86     gpio_enable_event(MC13783_EVENT_ID);
  87
  88     while (1)
  89     {
  90         const struct mc13783_event *event, *event_last;
  91
  92         wakeup_wait(&mc13783_svc_wake, TIMEOUT_BLOCK);
  93
  94         if (mc13783_thread_id == 0)
  95             break;
  96
  97         mc13783_read_regs(pmic_ints_regs, pending, 2);
  98
  99         /* Only clear interrupts being dispatched */
 100         pending[0] &= pmic_int_enabled[0];
 101         pending[1] &= pmic_int_enabled[1];
 102
 103         mc13783_write_regs(pmic_ints_regs, pending, 2);
 104
 105         /* Whatever is going to be serviced in this loop has been
 106          * acknowledged. Reenable interrupt and if anything was still
 107          * pending or became pending again, another signal will be
 108          * generated. */
 109         bitset32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
 110
 111         event = mc13783_events;
 112         event_last = event + MC13783_NUM_EVENTS;
 113
 114         /* .count is surely expected to be > 0 */
 115         do
 116         {
 117             enum mc13783_event_sets set = event->set;
 118             uint32_t pnd = pending[set];
 119             uint32_t mask = event->mask;
 120
 121             if (pnd & mask)
 122             {
 123                 event->callback();
 124                 pnd &= ~mask;
 125                 pending[set] = pnd;
 126             }
 127
 128             if ((pending[0] | pending[1]) == 0)
 129                 break; /* Terminate early if nothing more to service */
 130         }
 131         while (++event < event_last);
 132     }
 133
 134     gpio_disable_event(MC13783_EVENT_ID);
 135 }
 136
 137 /* GPIO interrupt handler for mc13783 */
 138 void mc13783_event(void)
 139 {
 140     /* Mask the interrupt (unmasked when PMIC thread services it). */
 141     bitclr32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
 142     MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
 143     wakeup_signal(&mc13783_svc_wake);
 144 }
 145
 146 void INIT_ATTR mc13783_init(void)
 147 {
 148     /* Serial interface must have been initialized first! */
 149     wakeup_init(&mc13783_svc_wake);
 150     mutex_init(&mc13783_spi_mutex);
 151
 152     wakeup_init(&mc13783_spi_wake);
 153
 154     /* Enable the PMIC SPI module */
 155     spi_enable_module(&mc13783_spi);
 156
 157     /* Mask any PMIC interrupts for now - modules will enable them as
 158      * required */
 159     mc13783_write(MC13783_INTERRUPT_MASK0, 0xffffff);
 160     mc13783_write(MC13783_INTERRUPT_MASK1, 0xffffff);
 161
 162     MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
 163
 164     mc13783_thread_id =
 165         create_thread(mc13783_interrupt_thread,
 166             mc13783_thread_stack, sizeof(mc13783_thread_stack), 0,
 167             mc13783_thread_name IF_PRIO(, PRIORITY_REALTIME) IF_COP(, CPU));
 168 }
 169
 170 void mc13783_close(void)
 171 {
 172     unsigned int thread_id = mc13783_thread_id;
 173
 174     if (thread_id == 0)
 175         return;
 176
 177     mc13783_thread_id = 0;
 178     wakeup_signal(&mc13783_svc_wake);
 179     thread_wait(thread_id);
 180     spi_disable_module(&mc13783_spi);
 181 }
 182
 183 bool mc13783_enable_event(enum mc13783_event_ids id)
 184 {
 185     const struct mc13783_event * const event = &mc13783_events[id];
 186     int set = event->set;
 187     uint32_t mask = event->mask;
 188
 189     mutex_lock(&mc13783_spi_mutex);
 190
 191     pmic_int_enabled[set] |= mask;
 192     mc13783_clear(pmic_intm_regs[set], mask);
 193
 194     mutex_unlock(&mc13783_spi_mutex);
 195
 196     return true;
 197 }
 198
 199 void mc13783_disable_event(enum mc13783_event_ids id)
 200 {
 201     const struct mc13783_event * const event = &mc13783_events[id];
 202     int set = event->set;
 203     uint32_t mask = event->mask;
 204
 205     mutex_lock(&mc13783_spi_mutex);
 206
 207     pmic_int_enabled[set] &= ~mask;
 208     mc13783_set(pmic_intm_regs[set], mask);
 209
 210     mutex_unlock(&mc13783_spi_mutex);
 211 }
 212
 213 uint32_t mc13783_set(unsigned address, uint32_t bits)
 214 {
 215     uint32_t data;
 216
 217     mutex_lock(&mc13783_spi_mutex);
 218
 219     data = mc13783_read(address);
 220
 221     if (data != MC13783_DATA_ERROR)
 222         mc13783_write(address, data | bits);
 223
 224     mutex_unlock(&mc13783_spi_mutex);
 225
 226     return data;
 227 }
 228
 229 uint32_t mc13783_clear(unsigned address, uint32_t bits)
 230 {
 231     uint32_t data;
 232
 233     mutex_lock(&mc13783_spi_mutex);
 234
 235     data = mc13783_read(address);
 236
 237     if (data != MC13783_DATA_ERROR)
 238         mc13783_write(address, data & ~bits);
 239
 240     mutex_unlock(&mc13783_spi_mutex);
 241
 242     return data;
 243 }
 244
 245 int mc13783_write(unsigned address, uint32_t data)
 246 {
 247     uint32_t packet;
 248     int i;
 249
 250     if (address >= MC13783_NUM_REGS)
 251         return -1;
 252
 253     packet = (1 << 31) | (address << 25) | (data & 0xffffff);
 254
 255     mutex_lock(&mc13783_spi_mutex);
 256
 257     mc13783_transfer.txbuf = &packet;
 258     mc13783_transfer.rxbuf = NULL;
 259     mc13783_transfer.count = 1;
 260
 261     i = -1;
 262
 263     if (spi_transfer(&mc13783_transfer) && wait_for_transfer_complete())
 264         i = 1 - mc13783_transfer.count;
 265
 266     mutex_unlock(&mc13783_spi_mutex);
 267
 268     return i;
 269 }
 270
 271 uint32_t mc13783_write_masked(unsigned address, uint32_t data, uint32_t mask)
 272 {
 273     uint32_t old;
 274
 275     mutex_lock(&mc13783_spi_mutex);
 276
 277     old = mc13783_read(address);
 278
 279     if (old != MC13783_DATA_ERROR)
 280     {
 281         data = (old & ~mask) | (data & mask);
 282
 283         if (mc13783_write(address, data) != 1)
 284             old = MC13783_DATA_ERROR;
 285     }
 286
 287     mutex_unlock(&mc13783_spi_mutex);
 288
 289     return old;
 290 }
 291
 292 uint32_t mc13783_read(unsigned address)
 293 {
 294     uint32_t packet;
 295
 296     if (address >= MC13783_NUM_REGS)
 297         return MC13783_DATA_ERROR;
 298
 299     packet = address << 25;
 300
 301     mutex_lock(&mc13783_spi_mutex);
 302
 303     mc13783_transfer.txbuf = &packet;
 304     mc13783_transfer.rxbuf = &packet;
 305     mc13783_transfer.count = 1;
 306
 307     if (!spi_transfer(&mc13783_transfer) || !wait_for_transfer_complete())
 308         packet = MC13783_DATA_ERROR;
 309
 310     mutex_unlock(&mc13783_spi_mutex);
 311
 312     return packet;
 313 }
 314
 315 int mc13783_read_regs(const unsigned char *regs, uint32_t *buffer,
 316                       int count)
 317 {
 318     int i;
 319
 320     for (i = 0; i < count; i++)
 321     {
 322         unsigned reg = regs[i];
 323
 324         if (reg >= MC13783_NUM_REGS)
 325             return -1;
 326
 327         buffer[i] = reg << 25;
 328     }
 329
 330     mutex_lock(&mc13783_spi_mutex);
 331
 332     mc13783_transfer.txbuf = buffer;
 333     mc13783_transfer.rxbuf = buffer;
 334     mc13783_transfer.count = count;
 335
 336     i = -1;
 337
 338     if (spi_transfer(&mc13783_transfer) && wait_for_transfer_complete())
 339         i = count - mc13783_transfer.count;
 340
 341     mutex_unlock(&mc13783_spi_mutex);
 342
 343     return i;
 344 }
 345
 346 int mc13783_write_regs(const unsigned char *regs, uint32_t *buffer,
 347                        int count)
 348 {
 349     int i;
 350
 351     for (i = 0; i < count; i++)
 352     {
 353         unsigned reg = regs[i];
 354
 355         if (reg >= MC13783_NUM_REGS)
 356             return -1;
 357
 358         buffer[i] = (1 << 31) | (reg << 25) | (buffer[i] & 0xffffff);
 359     }
 360
 361     mutex_lock(&mc13783_spi_mutex);
 362
 363     mc13783_transfer.txbuf = buffer;
 364     mc13783_transfer.rxbuf = NULL;
 365     mc13783_transfer.count = count;
 366
 367     i = -1;
 368
 369     if (spi_transfer(&mc13783_transfer) && wait_for_transfer_complete())
 370         i = count - mc13783_transfer.count;
 371
 372     mutex_unlock(&mc13783_spi_mutex);
 373
 374     return i;
 375 }
 376
 377 #if 0 /* Not needed right now */
 378 bool mc13783_read_async(struct spi_transfer_desc *xfer,
 379                         const unsigned char *regs, uint32_t *buffer,
 380                         int count, spi_transfer_cb_fn_type callback)
 381 {
 382     int i;
 383
 384     for (i = 0; i < count; i++)
 385     {
 386         unsigned reg = regs[i];
 387
 388         if (reg >= MC13783_NUM_REGS)
 389             return false;
 390
 391         buffer[i] = reg << 25;
 392     }
 393
 394     xfer->node  = &mc13783_spi;
 395     xfer->txbuf = buffer;
 396     xfer->rxbuf = buffer;
 397     xfer->count = count;
 398     xfer->callback = callback;
 399     xfer->next = NULL;
 400
 401     return spi_transfer(xfer);
 402 }
 403 #endif
 404
 405 bool mc13783_write_async(struct spi_transfer_desc *xfer,
 406                          const unsigned char *regs, uint32_t *buffer,
 407                          int count, spi_transfer_cb_fn_type callback)
 408 {
 409     int i;
 410
 411     for (i = 0; i < count; i++)
 412     {
 413         unsigned reg = regs[i];
 414
 415         if (reg >= MC13783_NUM_REGS)
 416             return false;
 417
 418         buffer[i] = (1 << 31) | (reg << 25) | (buffer[i] & 0xffffff);
 419     }
 420
 421     xfer->node  = &mc13783_spi;
 422     xfer->txbuf = buffer;
 423     xfer->rxbuf = NULL;
 424     xfer->count = count;
 425     xfer->callback = callback;
 426     xfer->next = NULL;
 427
 428     return spi_transfer(xfer);
 429 }