1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (c) 2008 by Michael Sevakis
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
23 #include "gpio-imx31.h"
28 extern const struct mc13783_event_list mc13783_event_list
;
29 extern struct spi_node mc13783_spi
;
31 /* PMIC event service data */
32 static int mc13783_thread_stack
[DEFAULT_STACK_SIZE
/sizeof(int)];
33 static const char *mc13783_thread_name
= "pmic";
34 static struct wakeup mc13783_svc_wake
;
36 /* Synchronous thread communication objects */
37 static struct mutex mc13783_spi_mutex
;
38 static struct wakeup mc13783_spi_wake
;
40 /* Tracking for which interrupts are enabled */
41 static uint32_t pmic_int_enabled
[2] =
42 { 0x00000000, 0x00000000 };
44 static const unsigned char pmic_intm_regs
[2] =
45 { MC13783_INTERRUPT_MASK0
, MC13783_INTERRUPT_MASK1
};
47 static const unsigned char pmic_ints_regs
[2] =
48 { MC13783_INTERRUPT_STATUS0
, MC13783_INTERRUPT_STATUS1
};
50 static volatile unsigned int mc13783_thread_id
= 0;
52 static void mc13783_xfer_complete_cb(struct spi_transfer_desc
*trans
);
54 /* Transfer descriptor for synchronous reads and writes */
55 static struct spi_transfer_desc mc13783_transfer
=
61 .callback
= mc13783_xfer_complete_cb
,
65 /* Called when a transfer is finished and data is ready/written */
66 static void mc13783_xfer_complete_cb(struct spi_transfer_desc
*xfer
)
71 wakeup_signal(&mc13783_spi_wake
);
74 static inline bool wait_for_transfer_complete(void)
76 return wakeup_wait(&mc13783_spi_wake
, HZ
*2) == OBJ_WAIT_SUCCEEDED
&&
77 mc13783_transfer
.count
== 0;
80 static void mc13783_interrupt_thread(void)
84 /* Enable mc13783 GPIO event */
85 gpio_enable_event(MC13783_EVENT_ID
);
89 const struct mc13783_event
*event
, *event_last
;
91 wakeup_wait(&mc13783_svc_wake
, TIMEOUT_BLOCK
);
93 if (mc13783_thread_id
== 0)
96 mc13783_read_regs(pmic_ints_regs
, pending
, 2);
98 /* Only clear interrupts being dispatched */
99 pending
[0] &= pmic_int_enabled
[0];
100 pending
[1] &= pmic_int_enabled
[1];
102 mc13783_write_regs(pmic_ints_regs
, pending
, 2);
104 /* Whatever is going to be serviced in this loop has been
105 * acknowledged. Reenable interrupt and if anything was still
106 * pending or became pending again, another signal will be
108 imx31_regset32(&MC13783_GPIO_IMR
, 1ul << MC13783_GPIO_LINE
);
110 event
= mc13783_event_list
.events
;
111 event_last
= event
+ mc13783_event_list
.count
;
113 /* .count is surely expected to be > 0 */
116 enum mc13783_event_sets set
= event
->set
;
117 uint32_t pnd
= pending
[set
];
118 uint32_t mask
= event
->mask
;
127 if ((pending
[0] | pending
[1]) == 0)
128 break; /* Terminate early if nothing more to service */
130 while (++event
< event_last
);
133 gpio_disable_event(MC13783_EVENT_ID
);
136 /* GPIO interrupt handler for mc13783 */
137 void mc13783_event(void)
139 /* Mask the interrupt (unmasked when PMIC thread services it). */
140 imx31_regclr32(&MC13783_GPIO_IMR
, 1ul << MC13783_GPIO_LINE
);
141 MC13783_GPIO_ISR
= (1ul << MC13783_GPIO_LINE
);
142 wakeup_signal(&mc13783_svc_wake
);
145 void mc13783_init(void)
147 /* Serial interface must have been initialized first! */
148 wakeup_init(&mc13783_svc_wake
);
149 mutex_init(&mc13783_spi_mutex
);
151 wakeup_init(&mc13783_spi_wake
);
153 /* Enable the PMIC SPI module */
154 spi_enable_module(&mc13783_spi
);
156 /* Mask any PMIC interrupts for now - modules will enable them as
158 mc13783_write(MC13783_INTERRUPT_MASK0
, 0xffffff);
159 mc13783_write(MC13783_INTERRUPT_MASK1
, 0xffffff);
161 MC13783_GPIO_ISR
= (1ul << MC13783_GPIO_LINE
);
164 create_thread(mc13783_interrupt_thread
,
165 mc13783_thread_stack
, sizeof(mc13783_thread_stack
), 0,
166 mc13783_thread_name
IF_PRIO(, PRIORITY_REALTIME
) IF_COP(, CPU
));
169 void mc13783_close(void)
171 unsigned int thread_id
= mc13783_thread_id
;
176 mc13783_thread_id
= 0;
177 wakeup_signal(&mc13783_svc_wake
);
178 thread_wait(thread_id
);
179 spi_disable_module(&mc13783_spi
);
182 bool mc13783_enable_event(enum mc13783_event_ids id
)
184 const struct mc13783_event
* const event
=
185 &mc13783_event_list
.events
[id
];
186 int set
= event
->set
;
187 uint32_t mask
= event
->mask
;
189 mutex_lock(&mc13783_spi_mutex
);
191 pmic_int_enabled
[set
] |= mask
;
192 mc13783_clear(pmic_intm_regs
[set
], mask
);
194 mutex_unlock(&mc13783_spi_mutex
);
199 void mc13783_disable_event(enum mc13783_event_ids id
)
201 const struct mc13783_event
* const event
=
202 &mc13783_event_list
.events
[id
];
203 int set
= event
->set
;
204 uint32_t mask
= event
->mask
;
206 mutex_lock(&mc13783_spi_mutex
);
208 pmic_int_enabled
[set
] &= ~mask
;
209 mc13783_set(pmic_intm_regs
[set
], mask
);
211 mutex_unlock(&mc13783_spi_mutex
);
214 uint32_t mc13783_set(unsigned address
, uint32_t bits
)
218 mutex_lock(&mc13783_spi_mutex
);
220 data
= mc13783_read(address
);
222 if (data
!= MC13783_DATA_ERROR
)
223 mc13783_write(address
, data
| bits
);
225 mutex_unlock(&mc13783_spi_mutex
);
230 uint32_t mc13783_clear(unsigned address
, uint32_t bits
)
234 mutex_lock(&mc13783_spi_mutex
);
236 data
= mc13783_read(address
);
238 if (data
!= MC13783_DATA_ERROR
)
239 mc13783_write(address
, data
& ~bits
);
241 mutex_unlock(&mc13783_spi_mutex
);
246 int mc13783_write(unsigned address
, uint32_t data
)
251 if (address
>= MC13783_NUM_REGS
)
254 packet
= (1 << 31) | (address
<< 25) | (data
& 0xffffff);
256 mutex_lock(&mc13783_spi_mutex
);
258 mc13783_transfer
.txbuf
= &packet
;
259 mc13783_transfer
.rxbuf
= NULL
;
260 mc13783_transfer
.count
= 1;
264 if (spi_transfer(&mc13783_transfer
) && wait_for_transfer_complete())
265 i
= 1 - mc13783_transfer
.count
;
267 mutex_unlock(&mc13783_spi_mutex
);
272 uint32_t mc13783_write_masked(unsigned address
, uint32_t data
, uint32_t mask
)
276 mutex_lock(&mc13783_spi_mutex
);
278 old
= mc13783_read(address
);
280 if (old
!= MC13783_DATA_ERROR
)
282 data
= (old
& ~mask
) | (data
& mask
);
284 if (mc13783_write(address
, data
) != 1)
285 old
= MC13783_DATA_ERROR
;
288 mutex_unlock(&mc13783_spi_mutex
);
293 uint32_t mc13783_read(unsigned address
)
297 if (address
>= MC13783_NUM_REGS
)
298 return MC13783_DATA_ERROR
;
300 packet
= address
<< 25;
302 mutex_lock(&mc13783_spi_mutex
);
304 mc13783_transfer
.txbuf
= &packet
;
305 mc13783_transfer
.rxbuf
= &packet
;
306 mc13783_transfer
.count
= 1;
308 if (!spi_transfer(&mc13783_transfer
) || !wait_for_transfer_complete())
309 packet
= MC13783_DATA_ERROR
;
311 mutex_unlock(&mc13783_spi_mutex
);
316 int mc13783_read_regs(const unsigned char *regs
, uint32_t *buffer
,
321 for (i
= 0; i
< count
; i
++)
323 unsigned reg
= regs
[i
];
325 if (reg
>= MC13783_NUM_REGS
)
328 buffer
[i
] = reg
<< 25;
331 mutex_lock(&mc13783_spi_mutex
);
333 mc13783_transfer
.txbuf
= buffer
;
334 mc13783_transfer
.rxbuf
= buffer
;
335 mc13783_transfer
.count
= count
;
339 if (spi_transfer(&mc13783_transfer
) && wait_for_transfer_complete())
340 i
= count
- mc13783_transfer
.count
;
342 mutex_unlock(&mc13783_spi_mutex
);
347 int mc13783_write_regs(const unsigned char *regs
, uint32_t *buffer
,
352 for (i
= 0; i
< count
; i
++)
354 unsigned reg
= regs
[i
];
356 if (reg
>= MC13783_NUM_REGS
)
359 buffer
[i
] = (1 << 31) | (reg
<< 25) | (buffer
[i
] & 0xffffff);
362 mutex_lock(&mc13783_spi_mutex
);
364 mc13783_transfer
.txbuf
= buffer
;
365 mc13783_transfer
.rxbuf
= NULL
;
366 mc13783_transfer
.count
= count
;
370 if (spi_transfer(&mc13783_transfer
) && wait_for_transfer_complete())
371 i
= count
- mc13783_transfer
.count
;
373 mutex_unlock(&mc13783_spi_mutex
);
378 #if 0 /* Not needed right now */
379 bool mc13783_read_async(struct spi_transfer_desc
*xfer
,
380 const unsigned char *regs
, uint32_t *buffer
,
381 int count
, spi_transfer_cb_fn_type callback
)
385 for (i
= 0; i
< count
; i
++)
387 unsigned reg
= regs
[i
];
389 if (reg
>= MC13783_NUM_REGS
)
392 buffer
[i
] = reg
<< 25;
395 xfer
->node
= &mc13783_spi
;
396 xfer
->txbuf
= buffer
;
397 xfer
->rxbuf
= buffer
;
399 xfer
->callback
= callback
;
401 return spi_transfer(xfer
);
405 bool mc13783_write_async(struct spi_transfer_desc
*xfer
,
406 const unsigned char *regs
, uint32_t *buffer
,
407 int count
, spi_transfer_cb_fn_type callback
)
411 for (i
= 0; i
< count
; i
++)
413 unsigned reg
= regs
[i
];
415 if (reg
>= MC13783_NUM_REGS
)
418 buffer
[i
] = (1 << 31) | (reg
<< 25) | (buffer
[i
] & 0xffffff);
421 xfer
->node
= &mc13783_spi
;
422 xfer
->txbuf
= buffer
;
425 xfer
->callback
= callback
;
427 return spi_transfer(xfer
);