firmware/target/arm/thread-arm.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2005 by Thom Johansen
  11  *
  12  * Generic ARM threading support
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  20  * KIND, either express or implied.
  21  *
  22  ****************************************************************************/
  23
  24 /*---------------------------------------------------------------------------
  25  * Start the thread running and terminate it if it returns
  26  *---------------------------------------------------------------------------
  27  */
  28 static void __attribute__((naked,used)) start_thread(void)
  29 {
  30     /* r0 = context */
  31     asm volatile (
  32         "ldr    sp, [r0, #32]            \n" /* Load initial sp */
  33         "ldr    r4, [r0, #40]            \n" /* start in r4 since it's non-volatile */
  34         "mov    r1, #0                   \n" /* Mark thread as running */
  35         "str    r1, [r0, #40]            \n"
  36 #if NUM_CORES > 1
  37         "ldr    r0, =cpucache_invalidate \n" /* Invalidate this core's cache. */
  38         "mov    lr, pc                   \n" /* This could be the first entry into */
  39         "bx     r0                       \n" /* plugin or codec code for this core. */
  40 #endif
  41         "mov    lr, pc                   \n" /* Call thread function */
  42         "bx     r4                       \n"
  43     ); /* No clobber list - new thread doesn't care */
  44     thread_exit();
  45 #if 0
  46     asm volatile (".ltorg"); /* Dump constant pool */
  47 #endif
  48 }
  49
  50 /* For startup, place context pointer in r4 slot, start_thread pointer in r5
  51  * slot, and thread function pointer in context.start. See load_context for
  52  * what happens when thread is initially going to run. */
  53 #define THREAD_STARTUP_INIT(core, thread, function) \
  54     ({ (thread)->context.r[0] = (uint32_t)&(thread)->context,  \
  55        (thread)->context.r[1] = (uint32_t)start_thread, \
  56        (thread)->context.start = (uint32_t)function; })
  57
  58
  59 /*---------------------------------------------------------------------------
  60  * Store non-volatile context.
  61  *---------------------------------------------------------------------------
  62  */
  63 static inline void store_context(void* addr)
  64 {
  65     asm volatile(
  66         "stmia  %0, { r4-r11, sp, lr } \n"
  67         : : "r" (addr)
  68     );
  69 }
  70
  71 /*---------------------------------------------------------------------------
  72  * Load non-volatile context.
  73  *---------------------------------------------------------------------------
  74  */
  75 static inline void load_context(const void* addr)
  76 {
  77     asm volatile(
  78         "ldr     r0, [%0, #40]          \n" /* Load start pointer */
  79         "cmp     r0, #0                 \n" /* Check for NULL */
  80
  81         /* If not already running, jump to start */
  82 #if ARM_ARCH == 4 && defined(USE_THUMB)
  83         "ldmneia %0, { r0, r12 }        \n"
  84         "bxne    r12                    \n"
  85 #else
  86         "ldmneia %0, { r0, pc }         \n"
  87 #endif
  88
  89         "ldmia   %0, { r4-r11, sp, lr } \n" /* Load regs r4 to r14 from context */
  90         : : "r" (addr) : "r0" /* only! */
  91     );
  92 }
  93
  94 #if defined(CPU_TCC780X) || defined(CPU_TCC77X) /* Single core only for now */ \
  95 || CONFIG_CPU == IMX31L || CONFIG_CPU == DM320 || CONFIG_CPU == AS3525 \
  96 || CONFIG_CPU == S3C2440 || CONFIG_CPU == S5L8701 || CONFIG_CPU == AS3525v2
  97 /* Use the generic ARMv4/v5/v6 wait for IRQ */
  98 static inline void core_sleep(void)
  99 {
 100     asm volatile (
 101         "mcr p15, 0, %0, c7, c0, 4 \n" /* Wait for interrupt */
 102 #if CONFIG_CPU == IMX31L
 103         "nop\n nop\n nop\n nop\n nop\n" /* Clean out the pipes */
 104 #endif
 105         : : "r"(0)
 106     );
 107     enable_irq();
 108 }
 109 #else
 110 /* Skip this if special code is required and implemented */
 111 #ifndef CPU_PP
 112 static inline void core_sleep(void)
 113 {
 114     #warning core_sleep not implemented, battery life will be decreased
 115     enable_irq();
 116 }
 117 #endif /* CPU_PP */
 118 #endif
 119
 120