firmware/target/arm/imx31/sdma_struct.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2009 by Michael Sevakis
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 /* Largely taken from sdmaStruct.h from the Linux BSP provided by Freescale.
  23  * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved.
  24  */
  25
  26 /* Other information gleaned from RE-ing the BSP and SDMA code */
  27
  28 #ifndef SDMA_STRUCT_H
  29 #define SDMA_STRUCT_H
  30
  31 /**
  32  * Number of channels
  33  */
  34 #define CH_NUM  32
  35
  36 /**
  37  * Ownership
  38  */
  39 #define CH_OWNSHP_EVT (1 << 0)
  40 #define CH_OWNSHP_MCU (1 << 1)
  41 #if 0
  42 #define CH_OWNSHP_DSP (1 << 2)
  43 #endif
  44
  45 /**
  46  * Channel contexts management
  47  */
  48
  49 /* Contexts for each channel begin here within SDMA core */
  50 #define CHANNEL_CONTEXT_BASE_ADDR 0x800
  51 /* Compute SDMA address where context for a channel is stored */
  52 #define CHANNEL_CONTEXT_ADDR(channel) \
  53     (CHANNEL_CONTEXT_BASE_ADDR+sizeof(struct context_data)/4*(channel))
  54
  55 /**
  56  * Error bit set in the CCB status field by the SDMA,
  57  * in setbd routine, in case of a transfer error
  58  */
  59 #define DATA_ERROR  (1 << 28) /* BD_RROR set on last buffer descriptor */
  60 #define DATA_FAULT  (1 << 29) /* A source or destination fault occured */
  61
  62 /**
  63  * Buffer descriptor status values.
  64  */
  65 #define BD_DONE  0x01 /* Set by host, cleared when SDMA has finished with
  66                          this BD */
  67 #define BD_WRAP  0x02 /* If set in last descriptor, allows circular buffer
  68                        * structure. curr_bd_ptr will be reset to base_bd_ptr
  69                        */
  70 #define BD_CONT  0x04 /* If set, more descriptors follow (multi-buffer) */
  71 #define BD_INTR  0x08 /* Interrupt when transfer complete */
  72 #define BD_RROR  0x10 /* Error during BD processing (set by SDMA) */
  73 #define BD_LAST  0x20 /* Set by SDMA ap_2_bp and bp_2_ap scripts.
  74                          TODO: determine function */
  75 #define BD_EXTD  0x80 /* Use extended buffer address (indicates BD is 12
  76                          bytes instead of 8) */
  77
  78 /**
  79  * Buffer descriptor channel 0 commands.
  80  */
  81 #define C0_SETCTX 0x07 /* Write context for a channel (ch# = BD command [7:3]) */
  82 #define C0_GETCTX 0x03 /* Read context for a channel (ch# = BD command [7:3]) */
  83 #define C0_SETDM  0x01 /* Write 32-bit words to SDMA memory */
  84 #define C0_GETDM  0x02 /* Read 32-bit words from SDMA memory */
  85 #define C0_SETPM  0x04 /* Write 16-bit halfwords to SDMA memory */
  86 #define C0_GETPM  0x08 /* Read 16-bit halfwords from SDMA memory */
  87
  88 /* Treated the same as those above */
  89 #define C0_ADDR   0x01
  90 #define C0_LOAD   0x02
  91 #define C0_DUMP   0x03
  92
  93 /**
  94  * Transfer sizes, encoded in the BD command field (when not a C0_ command).
  95  */
  96 #define TRANSFER_32BIT 0x00
  97 #define TRANSFER_8BIT  0x01
  98 #define TRANSFER_16BIT 0x02
  99 #define TRANSFER_24BIT 0x03
 100
 101 /**
 102  * Change endianness indicator in the BD command field
 103  */
 104 #define CHANGE_ENDIANNESS   0x80
 105
 106 /**
 107  * Size in bytes of struct buffer_descriptor
 108  */
 109 #define SDMA_BD_SIZE           8
 110 #define SDMA_EXTENDED_BD_SIZE 12
 111 #define BD_NUMBER              4
 112
 113 /**
 114  * Channel interrupt policy
 115  */
 116 #define DEFAULT_POLL 0
 117 #define CALLBACK_ISR 1
 118 /**
 119  * Channel status
 120  */
 121 #define UNINITIALIZED 0
 122 #define INITIALIZED 1
 123
 124 /**
 125  * IoCtl particular values
 126  */
 127 #define SET_BIT_ALL     0xFFFFFFFF
 128 #define BD_NUM_OFFSET   16
 129 #define BD_NUM_MASK     0xFFFF0000
 130
 131 /**
 132  * Maximum values for IoCtl calls, used in high or middle level calls
 133  */
 134 #define MAX_BD_NUM         256
 135 #define MAX_BD_SIZE        65536
 136 #define MAX_BLOCKING       2
 137 #define MAX_SYNCH          2
 138 #define MAX_OWNERSHIP      8
 139 #define MAX_CH_PRIORITY    8
 140 #define MAX_TRUST          2
 141 #define MAX_WML            256
 142
 143
 144 /**
 145  * Default values for channel descriptor - nobody owns the channel
 146  */
 147 #define CD_DEFAULT_OWNERSHIP  7
 148
 149 #if 0 /* IPC not used */
 150 /**
 151  * Data Node descriptor status values.
 152  */
 153 #define DND_END_OF_FRAME  0x80
 154 #define DND_END_OF_XFER   0x40
 155 #define DND_DONE          0x20
 156 #define DND_UNUSED        0x01
 157
 158 /**
 159  * IPCV2 descriptor status values.
 160  */
 161 #define BD_IPCV2_END_OF_FRAME  0x40
 162
 163 #define IPCV2_MAX_NODES        50
 164
 165 /**
 166  * User Type Section
 167  */
 168
 169 /**
 170  * Command/Mode/Count of buffer descriptors
 171  */
 172 struct mode_count_ipcv2
 173 {
 174     unsigned long count    : 16; /* size of the buffer pointed by this BD */
 175     unsigned long reserved :  8; /* reserved */
 176     unsigned long status   :  8; /* L, E, D bits stored here */
 177 };
 178
 179 /**
 180  * Data Node descriptor - IPCv2
 181  * (differentiated between evolutions of SDMA)
 182  */
 183 struct data_node_descriptor
 184 {
 185     struct mode_count_ipcv2 mode; /* command, status and count */
 186     void* buffer_addr;            /* address of the buffer described */
 187 };
 188
 189 struct mode_count_ipcv1_v2
 190 {
 191     unsigned long count      : 16; /* size of the buffer pointed by this BD */
 192     unsigned long status     :  8; /* E,R,I,C,W,D status bits stored here */
 193     unsigned long reserved   :  7;
 194     unsigned long endianness :  1;
 195 };
 196
 197 /**
 198  * Buffer descriptor
 199  * (differentiated between evolutions of SDMA)
 200  */
 201 struct buffer_descriptor_ipcv1_v2
 202 {
 203     struct mode_count_ipcv1_v2 mode; /* command, status and count */
 204     void *buffer_addr;               /* address of the buffer described */
 205     void *ext_buffer_addr;           /* extended buffer address */
 206 };
 207 #endif /* No IPC */
 208
 209 /**
 210  * Mode/Count of data node descriptors - IPCv2
 211  */
 212 struct mode_count
 213 {
 214     unsigned long count   : 16; /* size of the buffer pointed by this BD */
 215     unsigned long status  :  8; /* E,R,I,C,W,D status bits stored here:
 216                                  * SDMA r/w */
 217     unsigned long command :  8; /* channel 0 command or transfer size */
 218 };
 219
 220
 221 /**
 222  * Buffer descriptor - describes each buffer in a DMA transfer.
 223  * (differentiated between evolutions of SDMA)
 224  */
 225 /* (mode.status & BD_EXTD) == 0 (8 bytes) */
 226 struct buffer_descriptor
 227 {
 228     volatile struct mode_count mode; /* command, status and count: SDMA r/w */
 229     void *buf_addr;     /* address of the buffer described: SDMA r */
 230 };
 231
 232 /* (mode.status & BD_EXTD) != 0 (12 bytes) */
 233 struct buffer_descriptor_extd
 234 {
 235     struct buffer_descriptor bd;
 236     void *buf_addr_ext; /* extended buffer address described (r6): SDMA r */
 237 };
 238
 239 #if 0 /* A different one is defined for Rockbox use - this has too much.
 240        * See below. */
 241 struct channel_control_block;
 242 struct channel_descriptor;
 243 /**
 244  * Channel Descriptor
 245  */
 246 struct channel_descriptor
 247 {
 248     unsigned char  channel_number;       /* stores the channel number */
 249     unsigned char  buffer_desc_count;    /* number of BD's allocated
 250                                             for this channel */
 251     unsigned short buffer_per_desc_size; /* size (in bytes) of buffer
 252                                             descriptors' data buffers */
 253     unsigned long  blocking        :  3; /* polling/ callback method
 254                                             selection */
 255     unsigned long  callback_synch  :  1; /* (iapi) blocking / non blocking
 256                                             feature selection */
 257     unsigned long  ownership       :  3; /* ownership of the channel
 258                                             (host+dedicated+event) */
 259     unsigned long  priority        :  3; /* reflects the SDMA channel
 260                                             priority register */
 261     unsigned long  trust           :  1; /* trusted buffers or kernel
 262                                             allocated */
 263     unsigned long  use_data_size   :  1; /* (iapi) indicates if the dataSize
 264                                             field is meaningfull */
 265     unsigned long  data_size       :  2; /* (iapi->BD) data transfer
 266                                             size - 8,16,24 or 32 bits*/
 267     unsigned long  force_close     :  1; /* If TRUE, close channel even
 268                                             with BD owned by SDMA*/
 269     unsigned long  script_id       :  7; /* number of the script */
 270     unsigned long  watermark_level : 10; /* (greg) Watermark level for the
 271                                             peripheral access */
 272     unsigned long  event_mask1;          /* (greg) First Event mask */
 273     unsigned long  event_mask2;          /* (greg) Second  Event mask */
 274     unsigned long  shp_addr;             /* (greg) Address of the peripheral
 275                                              or its fifo when needed */
 276     void (* callback)(struct channel_descriptor *); /* pointer to the
 277                                              callback function (or NULL) */
 278     struct channel_control_block *ccb_ptr; /* pointer to the channel control
 279                                               block associated to this
 280                                               channel */
 281 };
 282 #endif
 283
 284 /* Only what we need, members sorted by size, no code-bloating bitfields */
 285 struct channel_descriptor
 286 {
 287     unsigned int bd_count;                 /* number of BD's allocated
 288                                               for this channel */
 289     struct channel_control_block *ccb_ptr; /* pointer to the channel control
 290                                               block associated to this
 291                                               channel */
 292     void (* callback)(void);               /* pointer to the
 293                                               callback function (or NULL) */
 294     unsigned long shp_addr;                /* (greg) Address of the peripheral
 295                                               or its fifo when needed */
 296     unsigned short wml;                    /* (greg) Watermark level for the
 297                                               peripheral access */
 298     unsigned char per_type;                /* Peripheral type */
 299     unsigned char tran_type;               /* Transfer type */
 300     unsigned char event_id1;               /* DMA request ID */
 301     unsigned char event_id2;               /* DMA request ID 2 */
 302     unsigned char is_setup;                /* Channel setup has been done */
 303 };
 304
 305 /**
 306  * Channel Status
 307  */
 308 struct channel_status
 309 {
 310     unsigned long unused          : 28;
 311     unsigned long error           :  1; /* Last BD triggered an error:
 312                                            SDMA r/w */
 313     unsigned long opened_init     :  1; /* Channel is initialized:
 314                                            SDMA r/w */
 315     unsigned long state_direction :  1; /* SDMA is reading/writing (as seen
 316                                            from channel owner core) */
 317     unsigned long execute         :  1; /* Channel is being processed
 318                                            (started) or not */
 319 };
 320
 321 /**
 322  * Channel control Block
 323  * SDMA ROM code expects these are 16-bytes each in an array
 324  * (MC0PTR + 16*CCR)
 325  */
 326 struct channel_control_block
 327 {
 328     /* current buffer descriptor processed: SDMA r/w */
 329     struct buffer_descriptor * volatile curr_bd_ptr;
 330     /* first element of buffer descriptor array: SDMA r */
 331     struct buffer_descriptor  *base_bd_ptr;
 332     /* pointer to the channel descriptor: SDMA ignored */
 333     struct channel_descriptor *channel_desc;
 334     /* open/close ; started/stopped ; read/write: SDMA r/w */
 335     volatile struct channel_status status;
 336 };
 337
 338 /**
 339  * Channel context structure.
 340  */
 341
 342 /* Channel state bits on SDMA core side */
 343 struct state_registers
 344 {
 345     /* Offset 0 */
 346     unsigned long pc      : 14; /* program counter */
 347     unsigned long unused0 :  1;
 348     unsigned long t       :  1; /* test bit: status of arithmetic & test
 349                                    instruction */
 350     unsigned long rpc     : 14; /* return program counter */
 351     unsigned long unused1 :  1;
 352     unsigned long sf      :  1; /* source fault while loading data */
 353     /* Offset 1 */
 354     unsigned long spc     : 14; /* loop start program counter */
 355     unsigned long unused2 :  1;
 356     unsigned long df      :  1; /* destination falut while storing data */
 357     unsigned long epc     : 14; /* loop end program counter */
 358     unsigned long lm      :  2; /* loop mode */
 359 };
 360
 361 /* Context data saved for every channel on the SDMA core. This is 32 words
 362  * long which is specified in the SDMA initialization on the AP side. The
 363  * SDMA scripts utilize the scratch space. */
 364 struct context_data
 365 {
 366     struct state_registers channel_state; /* channel state bits */
 367     union
 368     {
 369         unsigned long r[8];            /* general registers (r0-r7) */
 370         struct                         /* script usage of said when
 371                                           setting contexts */
 372         {
 373             unsigned long event_mask2; /* 08h */
 374             unsigned long event_mask1; /* 0Ch */
 375             unsigned long r2;          /* 10h */
 376             unsigned long r3;          /* 14h */
 377             unsigned long r4;          /* 18h */
 378             unsigned long r5;          /* 1Ch */
 379             unsigned long shp_addr;    /* 20h */
 380             unsigned long wml;         /* 24h */
 381         };
 382     };
 383     unsigned long mda; /* burst dma destination address register */
 384     unsigned long msa; /* burst dma source address register */
 385     unsigned long ms;  /* burst dma status register */
 386     unsigned long md;  /* burst dma data register */
 387     unsigned long pda; /* peripheral dma destination address register */
 388     unsigned long psa; /* peripheral dma source address register */
 389     unsigned long ps;  /* peripheral dma status register */
 390     unsigned long pd;  /* peripheral dma data register */
 391     unsigned long ca;  /* CRC polynomial register */
 392     unsigned long cs;  /* CRC accumulator register */
 393     unsigned long dda; /* dedicated core destination address register */
 394     unsigned long dsa; /* dedicated core source address register */
 395     unsigned long ds;  /* dedicated core status register */
 396     unsigned long dd;  /* dedicated core data register */
 397     unsigned long scratch[8]; /* channel context scratch RAM */
 398 };
 399
 400 /**
 401  * This structure holds the necessary data for the assignment in the
 402  * dynamic channel-script association
 403  */
 404 struct script_data
 405 {
 406     unsigned long load_address; /* start address of the script */
 407     unsigned long wml;              /* parameters for the channel descriptor */
 408     unsigned long shp_addr;     /* shared peripheral base address */
 409     unsigned long event_mask1;  /* first event mask */
 410     unsigned long event_mask2;  /* second event mask */
 411 };
 412
 413 /**
 414  * This structure holds the the useful bits of the CONFIG register
 415  */
 416 struct configs_data
 417 {
 418   unsigned long dspdma : 1; /* indicates if the DSPDMA is used */
 419   unsigned long rtdobs : 1; /* indicates if Real-Time Debug pins are
 420                                enabled */
 421   unsigned long acr    : 1; /* indicates if AHB freq /core freq = 2 or 1 */
 422   unsigned long csm    : 2; /* indicates which context switch mode is
 423                                selected */
 424 };
 425
 426 #endif /* SDMA_STRUCT_H */