firmware/target/arm/imx31/mc13783-imx31.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (c) 2008 by Michael Sevakis
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "system.h"
  22 #include "cpu.h"
  23 #include "gpio-imx31.h"
  24 #include "mc13783.h"
  25 #include "debug.h"
  26 #include "kernel.h"
  27
  28 extern const struct mc13783_event_list mc13783_event_list;
  29 extern struct spi_node mc13783_spi;
  30
  31 /* PMIC event service data */
  32 static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)];
  33 static const char *mc13783_thread_name = "pmic";
  34 static struct wakeup mc13783_svc_wake;
  35
  36 /* Synchronous thread communication objects */
  37 static struct mutex mc13783_spi_mutex;
  38 static struct wakeup mc13783_spi_wake;
  39
  40 /* Tracking for which interrupts are enabled */
  41 static uint32_t pmic_int_enabled[2] =
  42     { 0x00000000, 0x00000000 };
  43
  44 static const unsigned char pmic_intm_regs[2] =
  45     { MC13783_INTERRUPT_MASK0, MC13783_INTERRUPT_MASK1 };
  46
  47 static const unsigned char pmic_ints_regs[2] =
  48     { MC13783_INTERRUPT_STATUS0, MC13783_INTERRUPT_STATUS1 };
  49
  50 static volatile unsigned int mc13783_thread_id = 0;
  51
  52 static void mc13783_xfer_complete_cb(struct spi_transfer_desc *trans);
  53
  54 /* Transfer descriptor for synchronous reads and writes */
  55 static struct spi_transfer_desc mc13783_transfer =
  56 {
  57     .node = &mc13783_spi,
  58     .txbuf = NULL,
  59     .rxbuf = NULL,
  60     .count = 0,
  61     .callback = mc13783_xfer_complete_cb,
  62     .next = NULL,
  63 };
  64
  65 /* Called when a transfer is finished and data is ready/written */
  66 static void mc13783_xfer_complete_cb(struct spi_transfer_desc *xfer)
  67 {
  68     if (xfer->count != 0)
  69         return;
  70
  71     wakeup_signal(&mc13783_spi_wake);
  72 }
  73
  74 static inline bool wait_for_transfer_complete(void)
  75 {
  76     return wakeup_wait(&mc13783_spi_wake, HZ*2) == OBJ_WAIT_SUCCEEDED &&
  77            mc13783_transfer.count == 0;
  78 }
  79
  80 static void mc13783_interrupt_thread(void)
  81 {
  82     uint32_t pending[2];
  83
  84     /* Enable mc13783 GPIO event */
  85     gpio_enable_event(MC13783_EVENT_ID);
  86
  87     while (1)
  88     {
  89         const struct mc13783_event *event, *event_last;
  90
  91         wakeup_wait(&mc13783_svc_wake, TIMEOUT_BLOCK);
  92
  93         if (mc13783_thread_id == 0)
  94             break;
  95
  96         mc13783_read_regs(pmic_ints_regs, pending, 2);
  97
  98         /* Only clear interrupts being dispatched */
  99         pending[0] &= pmic_int_enabled[0];
 100         pending[1] &= pmic_int_enabled[1];
 101
 102         mc13783_write_regs(pmic_ints_regs, pending, 2);
 103
 104         /* Whatever is going to be serviced in this loop has been
 105          * acknowledged. Reenable interrupt and if anything was still
 106          * pending or became pending again, another signal will be
 107          * generated. */
 108         imx31_regset32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
 109
 110         event = mc13783_event_list.events;
 111         event_last = event + mc13783_event_list.count;
 112
 113         /* .count is surely expected to be > 0 */
 114         do
 115         {
 116             enum mc13783_event_sets set = event->set;
 117             uint32_t pnd = pending[set];
 118             uint32_t mask = event->mask;
 119
 120             if (pnd & mask)
 121             {
 122                 event->callback();
 123                 pnd &= ~mask;
 124                 pending[set] = pnd;
 125             }
 126
 127             if ((pending[0] | pending[1]) == 0)
 128                 break; /* Terminate early if nothing more to service */
 129         }
 130         while (++event < event_last);
 131     }
 132
 133     gpio_disable_event(MC13783_EVENT_ID);
 134 }
 135
 136 /* GPIO interrupt handler for mc13783 */
 137 void mc13783_event(void)
 138 {
 139     /* Mask the interrupt (unmasked when PMIC thread services it). */
 140     imx31_regclr32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
 141     MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
 142     wakeup_signal(&mc13783_svc_wake);
 143 }
 144
 145 void mc13783_init(void)
 146 {
 147     /* Serial interface must have been initialized first! */
 148     wakeup_init(&mc13783_svc_wake);
 149     mutex_init(&mc13783_spi_mutex);
 150
 151     wakeup_init(&mc13783_spi_wake);
 152
 153     /* Enable the PMIC SPI module */
 154     spi_enable_module(&mc13783_spi);
 155
 156     /* Mask any PMIC interrupts for now - modules will enable them as
 157      * required */
 158     mc13783_write(MC13783_INTERRUPT_MASK0, 0xffffff);
 159     mc13783_write(MC13783_INTERRUPT_MASK1, 0xffffff);
 160
 161     MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
 162
 163     mc13783_thread_id =
 164         create_thread(mc13783_interrupt_thread,
 165             mc13783_thread_stack, sizeof(mc13783_thread_stack), 0,
 166             mc13783_thread_name IF_PRIO(, PRIORITY_REALTIME) IF_COP(, CPU));
 167 }
 168
 169 void mc13783_close(void)
 170 {
 171     unsigned int thread_id = mc13783_thread_id;
 172
 173     if (thread_id == 0)
 174         return;
 175
 176     mc13783_thread_id = 0;
 177     wakeup_signal(&mc13783_svc_wake);
 178     thread_wait(thread_id);
 179     spi_disable_module(&mc13783_spi);
 180 }
 181
 182 bool mc13783_enable_event(enum mc13783_event_ids id)
 183 {
 184     const struct mc13783_event * const event =
 185         &mc13783_event_list.events[id];
 186     int set = event->set;
 187     uint32_t mask = event->mask;
 188
 189     mutex_lock(&mc13783_spi_mutex);
 190
 191     pmic_int_enabled[set] |= mask;
 192     mc13783_clear(pmic_intm_regs[set], mask);
 193
 194     mutex_unlock(&mc13783_spi_mutex);
 195
 196     return true;
 197 }
 198
 199 void mc13783_disable_event(enum mc13783_event_ids id)
 200 {
 201     const struct mc13783_event * const event =
 202         &mc13783_event_list.events[id];
 203     int set = event->set;
 204     uint32_t mask = event->mask;
 205
 206     mutex_lock(&mc13783_spi_mutex);
 207
 208     pmic_int_enabled[set] &= ~mask;
 209     mc13783_set(pmic_intm_regs[set], mask);
 210
 211     mutex_unlock(&mc13783_spi_mutex);
 212 }
 213
 214 uint32_t mc13783_set(unsigned address, uint32_t bits)
 215 {
 216     uint32_t data;
 217
 218     mutex_lock(&mc13783_spi_mutex);
 219
 220     data = mc13783_read(address);
 221
 222     if (data != MC13783_DATA_ERROR)
 223         mc13783_write(address, data | bits);
 224
 225     mutex_unlock(&mc13783_spi_mutex);
 226
 227     return data;
 228 }
 229
 230 uint32_t mc13783_clear(unsigned address, uint32_t bits)
 231 {
 232     uint32_t data;
 233
 234     mutex_lock(&mc13783_spi_mutex);
 235
 236     data = mc13783_read(address);
 237
 238     if (data != MC13783_DATA_ERROR)
 239         mc13783_write(address, data & ~bits);
 240
 241     mutex_unlock(&mc13783_spi_mutex);
 242
 243     return data;
 244 }
 245
 246 int mc13783_write(unsigned address, uint32_t data)
 247 {
 248     uint32_t packet;
 249     int i;
 250
 251     if (address >= MC13783_NUM_REGS)
 252         return -1;
 253
 254     packet = (1 << 31) | (address << 25) | (data & 0xffffff);
 255
 256     mutex_lock(&mc13783_spi_mutex);
 257
 258     mc13783_transfer.txbuf = &packet;
 259     mc13783_transfer.rxbuf = NULL;
 260     mc13783_transfer.count = 1;
 261
 262     i = -1;
 263
 264     if (spi_transfer(&mc13783_transfer) && wait_for_transfer_complete())
 265         i = 1 - mc13783_transfer.count;
 266
 267     mutex_unlock(&mc13783_spi_mutex);
 268
 269     return i;
 270 }
 271
 272 uint32_t mc13783_write_masked(unsigned address, uint32_t data, uint32_t mask)
 273 {
 274     uint32_t old;
 275
 276     mutex_lock(&mc13783_spi_mutex);
 277
 278     old = mc13783_read(address);
 279
 280     if (old != MC13783_DATA_ERROR)
 281     {
 282         data = (old & ~mask) | (data & mask);
 283
 284         if (mc13783_write(address, data) != 1)
 285             old = MC13783_DATA_ERROR;
 286     }
 287
 288     mutex_unlock(&mc13783_spi_mutex);
 289
 290     return old;
 291 }
 292
 293 uint32_t mc13783_read(unsigned address)
 294 {
 295     uint32_t packet;
 296
 297     if (address >= MC13783_NUM_REGS)
 298         return MC13783_DATA_ERROR;
 299
 300     packet = address << 25;
 301
 302     mutex_lock(&mc13783_spi_mutex);
 303
 304     mc13783_transfer.txbuf = &packet;
 305     mc13783_transfer.rxbuf = &packet;
 306     mc13783_transfer.count = 1;
 307
 308     if (!spi_transfer(&mc13783_transfer) || !wait_for_transfer_complete())
 309         packet = MC13783_DATA_ERROR;
 310
 311     mutex_unlock(&mc13783_spi_mutex);
 312
 313     return packet;
 314 }
 315
 316 int mc13783_read_regs(const unsigned char *regs, uint32_t *buffer,
 317                       int count)
 318 {
 319     int i;
 320
 321     for (i = 0; i < count; i++)
 322     {
 323         unsigned reg = regs[i];
 324
 325         if (reg >= MC13783_NUM_REGS)
 326             return -1;
 327
 328         buffer[i] = reg << 25;
 329     }
 330
 331     mutex_lock(&mc13783_spi_mutex);
 332
 333     mc13783_transfer.txbuf = buffer;
 334     mc13783_transfer.rxbuf = buffer;
 335     mc13783_transfer.count = count;
 336
 337     i = -1;
 338
 339     if (spi_transfer(&mc13783_transfer) && wait_for_transfer_complete())
 340         i = count - mc13783_transfer.count;
 341
 342     mutex_unlock(&mc13783_spi_mutex);
 343
 344     return i;
 345 }
 346
 347 int mc13783_write_regs(const unsigned char *regs, uint32_t *buffer,
 348                        int count)
 349 {
 350     int i;
 351
 352     for (i = 0; i < count; i++)
 353     {
 354         unsigned reg = regs[i];
 355
 356         if (reg >= MC13783_NUM_REGS)
 357             return -1;
 358
 359         buffer[i] = (1 << 31) | (reg << 25) | (buffer[i] & 0xffffff);
 360     }
 361
 362     mutex_lock(&mc13783_spi_mutex);
 363
 364     mc13783_transfer.txbuf = buffer;
 365     mc13783_transfer.rxbuf = NULL;
 366     mc13783_transfer.count = count;
 367
 368     i = -1;
 369
 370     if (spi_transfer(&mc13783_transfer) && wait_for_transfer_complete())
 371         i = count - mc13783_transfer.count;
 372
 373     mutex_unlock(&mc13783_spi_mutex);
 374
 375     return i;
 376 }
 377
 378 #if 0 /* Not needed right now */
 379 bool mc13783_read_async(struct spi_transfer_desc *xfer,
 380                         const unsigned char *regs, uint32_t *buffer,
 381                         int count, spi_transfer_cb_fn_type callback)
 382 {
 383     int i;
 384
 385     for (i = 0; i < count; i++)
 386     {
 387         unsigned reg = regs[i];
 388
 389         if (reg >= MC13783_NUM_REGS)
 390             return false;
 391
 392         buffer[i] = reg << 25;
 393     }
 394
 395     xfer->node  = &mc13783_spi;
 396     xfer->txbuf = buffer;
 397     xfer->rxbuf = buffer;
 398     xfer->count = count;
 399     xfer->callback = callback;
 400
 401     return spi_transfer(xfer);
 402 }
 403 #endif
 404
 405 bool mc13783_write_async(struct spi_transfer_desc *xfer,
 406                          const unsigned char *regs, uint32_t *buffer,
 407                          int count, spi_transfer_cb_fn_type callback)
 408 {
 409     int i;
 410
 411     for (i = 0; i < count; i++)
 412     {
 413         unsigned reg = regs[i];
 414
 415         if (reg >= MC13783_NUM_REGS)
 416             return false;
 417
 418         buffer[i] = (1 << 31) | (reg << 25) | (buffer[i] & 0xffffff);
 419     }
 420
 421     xfer->node  = &mc13783_spi;
 422     xfer->txbuf = buffer;
 423     xfer->rxbuf = NULL;
 424     xfer->count = count;
 425     xfer->callback = callback;
 426
 427     return spi_transfer(xfer);
 428 }