firmware/target/arm/as3525/sd-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 /* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
  24
  25 /* TODO: Find the real capacity of >2GB models (will be useful for USB) */
  26
  27 #include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
  28 #include "fat.h"
  29 #include "thread.h"
  30 #include "led.h"
  31 #include "hotswap.h"
  32 #include "system.h"
  33 #include "cpu.h"
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include "as3525.h"
  38 #include "pl180.h"  /* SD controller */
  39 #include "pl081.h"  /* DMA controller */
  40 #include "dma-target.h" /* DMA request lines */
  41 #include "clock-target.h"
  42 #include "panic.h"
  43 #ifdef HAVE_BUTTON_LIGHT
  44 #include "backlight-target.h"
  45 #endif
  46 #include "stdbool.h"
  47 #include "ata_idle_notify.h"
  48 #include "sd.h"
  49 #include "usb.h"
  50
  51 #ifdef HAVE_HOTSWAP
  52 #include "disk.h"
  53 #endif
  54
  55 /* command flags */
  56 #define MCI_NO_FLAGS    (0<<0)
  57 #define MCI_RESP        (1<<0)
  58 #define MCI_LONG_RESP   (1<<1)
  59 #define MCI_ARG         (1<<2)
  60
  61 /* ARM PL180 registers */
  62 #define MCI_POWER(i)       (*(volatile unsigned char *) (pl180_base[i]+0x00))
  63 #define MCI_CLOCK(i)       (*(volatile unsigned long *) (pl180_base[i]+0x04))
  64 #define MCI_ARGUMENT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x08))
  65 #define MCI_COMMAND(i)     (*(volatile unsigned long *) (pl180_base[i]+0x0C))
  66 #define MCI_RESPCMD(i)     (*(volatile unsigned long *) (pl180_base[i]+0x10))
  67 #define MCI_RESP0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x14))
  68 #define MCI_RESP1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x18))
  69 #define MCI_RESP2(i)       (*(volatile unsigned long *) (pl180_base[i]+0x1C))
  70 #define MCI_RESP3(i)       (*(volatile unsigned long *) (pl180_base[i]+0x20))
  71 #define MCI_DATA_TIMER(i)  (*(volatile unsigned long *) (pl180_base[i]+0x24))
  72 #define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
  73 #define MCI_DATA_CTRL(i)   (*(volatile unsigned char *) (pl180_base[i]+0x2C))
  74 #define MCI_DATA_CNT(i)    (*(volatile unsigned short*) (pl180_base[i]+0x30))
  75 #define MCI_STATUS(i)      (*(volatile unsigned long *) (pl180_base[i]+0x34))
  76 #define MCI_CLEAR(i)       (*(volatile unsigned long *) (pl180_base[i]+0x38))
  77 #define MCI_MASK0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x3C))
  78 #define MCI_MASK1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x40))
  79 #define MCI_SELECT(i)      (*(volatile unsigned long *) (pl180_base[i]+0x44))
  80 #define MCI_FIFO_CNT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x48))
  81
  82 #define MCI_DATA_ERROR    \
  83     ( MCI_DATA_CRC_FAIL   \
  84     | MCI_DATA_TIMEOUT    \
  85     | MCI_TX_UNDERRUN     \
  86     | MCI_RX_OVERRUN      \
  87     | MCI_START_BIT_ERR)
  88
  89 #define MCI_RESPONSE_ERROR    \
  90     ( MCI_CMD_TIMEOUT         \
  91     | MCI_CMD_CRC_FAIL)
  92
  93 #define MCI_FIFO(i)        ((unsigned long *) (pl180_base[i]+0x80))
  94 /* volumes */
  95 #define     INTERNAL_AS3525 0   /* embedded SD card */
  96 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  97
  98 static const int pl180_base[NUM_DRIVES] = {
  99             NAND_FLASH_BASE
 100 #ifdef HAVE_MULTIDRIVE
 101             , SD_MCI_BASE
 102 #endif
 103 };
 104
 105 static int sd_wait_for_state(const int drive, unsigned int state);
 106 static int sd_select_bank(signed char bank);
 107 static int sd_init_card(const int drive);
 108 static void init_pl180_controller(const int drive);
 109
 110 #define BLOCKS_PER_BANK 0x7a7800
 111
 112 static tCardInfo card_info[NUM_DRIVES];
 113
 114 /* maximum timeouts recommanded in the SD Specification v2.00 */
 115 #define SD_MAX_READ_TIMEOUT     ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
 116 #define SD_MAX_WRITE_TIMEOUT    ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
 117
 118 /* for compatibility */
 119 static long last_disk_activity = -1;
 120
 121 #define MIN_YIELD_PERIOD 5  /* ticks */
 122 static long next_yield = 0;
 123
 124 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 125 static const char         sd_thread_name[] = "ata/sd";
 126 static struct mutex       sd_mtx;
 127 static struct event_queue sd_queue;
 128 #ifndef BOOTLOADER
 129 bool sd_enabled = false;
 130 #endif
 131
 132 #if defined(HAVE_MULTIDRIVE)
 133 static bool hs_card = false;
 134 #define EXT_SD_BITS (1<<2)
 135 #endif
 136
 137 static struct wakeup transfer_completion_signal;
 138 static volatile unsigned int transfer_error[NUM_VOLUMES];
 139 #define PL180_MAX_TRANSFER_ERRORS 10
 140
 141 #define UNALIGNED_NUM_SECTORS 10
 142 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 143 static unsigned char *uncached_buffer = UNCACHED_ADDR(&aligned_buffer[0]);
 144
 145
 146 static inline void mci_delay(void) { udelay(1000) ; }
 147
 148
 149 static inline bool card_detect_target(void)
 150 {
 151 #if defined(HAVE_MULTIDRIVE)
 152     return !(GPIOA_PIN(2));
 153 #else
 154     return false;
 155 #endif
 156 }
 157
 158
 159 #ifdef HAVE_HOTSWAP
 160 static int sd1_oneshot_callback(struct timeout *tmo)
 161 {
 162     (void)tmo;
 163
 164     /* This is called only if the state was stable for 300ms - check state
 165      * and post appropriate event. */
 166     if (card_detect_target())
 167     {
 168         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 169     }
 170     else
 171         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 172
 173     return 0;
 174 }
 175
 176 void sd_gpioa_isr(void)
 177 {
 178     static struct timeout sd1_oneshot;
 179     if (GPIOA_MIS & EXT_SD_BITS)
 180         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 181     /* acknowledge interrupt */
 182     GPIOA_IC = EXT_SD_BITS;
 183 }
 184 #endif  /* HAVE_HOTSWAP */
 185
 186 void INT_NAND(void)
 187 {
 188     const int status = MCI_STATUS(INTERNAL_AS3525);
 189
 190     transfer_error[INTERNAL_AS3525] = status & MCI_DATA_ERROR;
 191
 192     wakeup_signal(&transfer_completion_signal);
 193     MCI_CLEAR(INTERNAL_AS3525) = status;
 194 }
 195
 196 #ifdef HAVE_MULTIDRIVE
 197 void INT_MCI0(void)
 198 {
 199     const int status = MCI_STATUS(SD_SLOT_AS3525);
 200
 201     transfer_error[SD_SLOT_AS3525] = status & MCI_DATA_ERROR;
 202
 203     wakeup_signal(&transfer_completion_signal);
 204     MCI_CLEAR(SD_SLOT_AS3525) = status;
 205 }
 206 #endif
 207
 208 static bool send_cmd(const int drive, const int cmd, const int arg,
 209                      const int flags, long *response)
 210 {
 211     int status;
 212
 213     /* Clear old status flags */
 214     MCI_CLEAR(drive) = 0x7ff;
 215
 216     /* Load command argument or clear if none */
 217     MCI_ARGUMENT(drive) = (flags & MCI_ARG) ? arg : 0;
 218
 219     /* Construct MCI_COMMAND & enable CPSM */
 220     MCI_COMMAND(drive) =
 221        /*b0:5*/  cmd
 222        /* b6 */| ((flags & (MCI_RESP|MCI_LONG_RESP)) ? MCI_COMMAND_RESPONSE : 0)
 223        /* b7 */| ((flags & MCI_LONG_RESP) ? MCI_COMMAND_LONG_RESPONSE : 0)
 224        /* b8   | MCI_COMMAND_INTERRUPT */
 225        /* b9   | MCI_COMMAND_PENDING */  /*Only used with stream data transfer*/
 226        /* b10*/| MCI_COMMAND_ENABLE;     /* Enables CPSM */
 227
 228     /* Wait while cmd completes then disable CPSM */
 229     while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);
 230     MCI_COMMAND(drive) = 0;
 231
 232     status = MCI_STATUS(drive);
 233
 234     /*  Handle command responses */
 235     if(flags & MCI_RESP)                   /*  CMD expects response  */
 236     {
 237         response[0] = MCI_RESP0(drive);    /*  Always prepare short response  */
 238
 239         if(status & MCI_RESPONSE_ERROR)    /* timeout or crc failure */
 240             return false;
 241
 242         if(status & MCI_CMD_RESP_END)      /* Response passed CRC check */
 243         {
 244             if(flags & MCI_LONG_RESP)
 245             {   /* response[0] has already been read */
 246                 response[1] = MCI_RESP1(drive);
 247                 response[2] = MCI_RESP2(drive);
 248                 response[3] = MCI_RESP3(drive);
 249             }
 250             return true;
 251         }
 252     }
 253     else if(status & MCI_CMD_SENT)          /* CMD sent, no response required */
 254         return true;
 255
 256     return false;
 257 }
 258
 259 #define MCI_FULLSPEED     (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS)     /* MCLK   */
 260 #define MCI_HALFSPEED     (MCI_CLOCK_ENABLE)                        /* MCLK/2 */
 261 #define MCI_QUARTERSPEED  (MCI_CLOCK_ENABLE | 1)                    /* MCLK/4 */
 262 #define MCI_IDENTSPEED    (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV)  /* IDENT  */
 263
 264 static int sd_init_card(const int drive)
 265 {
 266     unsigned long response;
 267     long init_timeout;
 268     bool sd_v2 = false;
 269
 270     /* MCLCK on and set to 400kHz ident frequency  */
 271     MCI_CLOCK(drive) = MCI_IDENTSPEED;
 272
 273     /* 100 - 400kHz clock required for Identification Mode  */
 274     /*  Start of Card Identification Mode ************************************/
 275
 276     /* CMD0 Go Idle  */
 277     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_FLAGS, NULL))
 278         return -1;
 279     mci_delay();
 280
 281     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 282       Non v2 cards will not respond to this command*/
 283     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP|MCI_ARG, &response))
 284         if((response & 0xFFF) == 0x1AA)
 285             sd_v2 = true;
 286
 287     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 288     init_timeout = current_tick + HZ;
 289
 290     do {
 291         /* this timeout is the only valid error for this loop*/
 292         if(TIME_AFTER(current_tick, init_timeout))
 293             return -2;
 294
 295         /* app_cmd */
 296         send_cmd(drive, SD_APP_CMD, 0, MCI_RESP|MCI_ARG, &response);
 297
 298         /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 299         send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 300                         MCI_RESP|MCI_ARG, &card_info[drive].ocr);
 301
 302     } while(!(card_info[drive].ocr & (1<<31)));
 303
 304     /* CMD2 send CID */
 305     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP|MCI_ARG,
 306                             card_info[drive].cid))
 307         return -3;
 308
 309     /* CMD3 send RCA */
 310     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP|MCI_ARG,
 311                 &card_info[drive].rca))
 312         return -4;
 313
 314     /*  End of Card Identification Mode   ************************************/
 315
 316 #ifdef HAVE_MULTIDRIVE        /*  The internal SDs are v1 */
 317
 318     /* Try to switch V2 cards to HS timings, non HS seem to ignore this */
 319     if(sd_v2)
 320     {
 321         /*  CMD7 w/rca: Select card to put it in TRAN state */
 322         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
 323             return -5;
 324         mci_delay();
 325
 326         if(sd_wait_for_state(drive, SD_TRAN))
 327             return -6;
 328         /* CMD6 */
 329         if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_ARG, NULL))
 330             return -7;
 331         mci_delay();
 332
 333         /*  go back to STBY state so we can read csd */
 334         /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 335         if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_ARG, NULL))
 336             return -8;
 337         mci_delay();
 338     }
 339 #endif /*  HAVE_MULTIDRIVE  */
 340
 341     /* CMD9 send CSD */
 342     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 343                  MCI_RESP|MCI_LONG_RESP|MCI_ARG, card_info[drive].csd))
 344         return -9;
 345
 346     sd_parse_csd(&card_info[drive]);
 347
 348 #if defined(HAVE_MULTIDRIVE)
 349     hs_card = (card_info[drive].speed == 50000000);
 350 #endif
 351
 352     /* Boost MCICLK to operating speed */
 353     if(drive == INTERNAL_AS3525)
 354         MCI_CLOCK(drive) = MCI_HALFSPEED;  /* MCICLK = IDE_CLK/2 = 25 MHz  */
 355 #if defined(HAVE_MULTIDRIVE)
 356     else
 357         /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
 358         MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
 359 #endif
 360
 361     /*  CMD7 w/rca: Select card to put it in TRAN state */
 362     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
 363         return -10;
 364     mci_delay();
 365
 366     /*
 367      * enable bank switching
 368      * without issuing this command, we only have access to 1/4 of the blocks
 369      * of the first bank (0x1E9E00 blocks, which is the size reported in the
 370      * CSD register)
 371      */
 372     if(drive == INTERNAL_AS3525)
 373     {
 374         const int ret = sd_select_bank(-1);
 375         if(ret < 0)
 376             return ret -16;
 377
 378         /*  CMD7 w/rca = 0: Select card to put it in STBY state */
 379         if(!send_cmd(drive, SD_SELECT_CARD, 0, MCI_ARG, NULL))
 380             return -17;
 381         mci_delay();
 382
 383         /* CMD9 send CSD again, so we got the correct number of blocks */
 384         if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 385                      MCI_RESP|MCI_LONG_RESP|MCI_ARG, card_info[drive].csd))
 386             return -18;
 387
 388         sd_parse_csd(&card_info[drive]);
 389         /* The OF is stored in the first blocks */
 390         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
 391
 392         /*  CMD7 w/rca: Select card to put it in TRAN state */
 393         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
 394             return -19;
 395         mci_delay();
 396     }
 397
 398     card_info[drive].initialized = 1;
 399
 400     return 0;
 401 }
 402
 403 static void sd_thread(void) __attribute__((noreturn));
 404 static void sd_thread(void)
 405 {
 406     struct queue_event ev;
 407     bool idle_notified = false;
 408
 409     while (1)
 410     {
 411         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 412
 413         switch ( ev.id )
 414         {
 415 #ifdef HAVE_HOTSWAP
 416         case SYS_HOTSWAP_INSERTED:
 417         case SYS_HOTSWAP_EXTRACTED:
 418         {
 419             int microsd_init = 1;
 420             fat_lock();          /* lock-out FAT activity first -
 421                                     prevent deadlocking via disk_mount that
 422                                     would cause a reverse-order attempt with
 423                                     another thread */
 424             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 425                                     into driver that bypass the fat cache */
 426
 427             /* We now have exclusive control of fat cache and ata */
 428
 429             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 430                                     descriptors aren't leaked and any busy
 431                                     ones are invalid if mounting */
 432
 433             /* Force card init for new card, re-init for re-inserted one or
 434              * clear if the last attempt to init failed with an error. */
 435             card_info[SD_SLOT_AS3525].initialized = 0;
 436
 437             if (ev.id == SYS_HOTSWAP_INSERTED)
 438             {
 439                 sd_enable(true);
 440                 init_pl180_controller(SD_SLOT_AS3525);
 441                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 442                 if (microsd_init < 0) /* initialisation failed */
 443                     panicf("microSD init failed : %d", microsd_init);
 444
 445                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 446             }
 447
 448             /*
 449              * Mount succeeded, or this was an EXTRACTED event,
 450              * in both cases notify the system about the changed filesystems
 451              */
 452             if (microsd_init)
 453                 queue_broadcast(SYS_FS_CHANGED, 0);
 454
 455             /* Access is now safe */
 456             mutex_unlock(&sd_mtx);
 457             fat_unlock();
 458             sd_enable(false);
 459         }
 460             break;
 461 #endif
 462         case SYS_TIMEOUT:
 463             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 464             {
 465                 idle_notified = false;
 466             }
 467             else
 468             {
 469                 /* never let a timer wrap confuse us */
 470                 next_yield = current_tick;
 471
 472                 if (!idle_notified)
 473                 {
 474                     call_storage_idle_notifys(false);
 475                     idle_notified = true;
 476                 }
 477             }
 478             break;
 479
 480         case SYS_USB_CONNECTED:
 481             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 482             /* Wait until the USB cable is extracted again */
 483             usb_wait_for_disconnect(&sd_queue);
 484
 485             break;
 486         case SYS_USB_DISCONNECTED:
 487             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 488             break;
 489         }
 490     }
 491 }
 492
 493 static void init_pl180_controller(const int drive)
 494 {
 495     MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;
 496     MCI_CLEAR(drive) = 0x7ff;
 497
 498     MCI_MASK0(drive) = MCI_DATA_ERROR | MCI_DATA_END;
 499     MCI_MASK1(drive) = 0;
 500 #ifdef HAVE_MULTIDRIVE
 501     VIC_INT_ENABLE =
 502         (drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
 503     /* clear previous irq */
 504     GPIOA_IC = EXT_SD_BITS;
 505     /* enable edge detecting */
 506     GPIOA_IS &= ~EXT_SD_BITS;
 507     /* detect both raising and falling edges */
 508     GPIOA_IBE |= EXT_SD_BITS;
 509
 510 #else
 511     VIC_INT_ENABLE = INTERRUPT_NAND;
 512 #endif
 513
 514     MCI_POWER(drive) = MCI_POWER_UP | (MCI_VDD_3_0);  /*  OF Setting  */
 515     mci_delay();
 516
 517     MCI_POWER(drive) |= MCI_POWER_ON;
 518     mci_delay();
 519
 520     MCI_SELECT(drive) = 0;
 521
 522     /* Pl180 clocks get turned on at start of card init */
 523 }
 524
 525 int sd_init(void)
 526 {
 527     int ret;
 528     CGU_IDE =   (1<<6)                  /*  enable non AHB interface*/
 529             |   (AS3525_IDE_DIV << 2)
 530             |    AS3525_CLK_PLLA;       /* clock source = PLLA */
 531
 532     CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
 533 #ifdef HAVE_MULTIDRIVE
 534     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 535     CCU_IO &= ~(1<<3);           /* bits 3:2 = 01, xpd is SD interface */
 536     CCU_IO |= (1<<2);
 537 #endif
 538
 539     wakeup_init(&transfer_completion_signal);
 540
 541     init_pl180_controller(INTERNAL_AS3525);
 542     ret = sd_init_card(INTERNAL_AS3525);
 543     if(ret < 0)
 544         return ret;
 545 #ifdef HAVE_MULTIDRIVE
 546     init_pl180_controller(SD_SLOT_AS3525);
 547 #endif
 548
 549     /* init mutex */
 550     mutex_init(&sd_mtx);
 551
 552     queue_init(&sd_queue, true);
 553     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 554             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 555
 556 #ifndef BOOTLOADER
 557     sd_enabled = true;
 558     sd_enable(false);
 559 #endif
 560     return 0;
 561 }
 562
 563 #ifdef HAVE_HOTSWAP
 564 bool sd_removable(IF_MD_NONVOID(int drive))
 565 {
 566     return (drive==1);
 567 }
 568
 569 bool sd_present(IF_MD_NONVOID(int drive))
 570 {
 571     return (drive == 0) ? true : card_detect_target();
 572 }
 573 #endif /* HAVE_HOTSWAP */
 574
 575 static int sd_wait_for_state(const int drive, unsigned int state)
 576 {
 577     unsigned long response = 0;
 578     unsigned int timeout = current_tick + 100; /* 100 ticks timeout */
 579
 580     while (1)
 581     {
 582         if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca,
 583                     MCI_RESP|MCI_ARG, &response))
 584             return -1;
 585
 586         if (((response >> 9) & 0xf) == state)
 587             return 0;
 588
 589         if(TIME_AFTER(current_tick, timeout))
 590             return -2;
 591
 592         if (TIME_AFTER(current_tick, next_yield))
 593         {
 594             yield();
 595             next_yield = current_tick + MIN_YIELD_PERIOD;
 596         }
 597     }
 598 }
 599
 600 static int sd_select_bank(signed char bank)
 601 {
 602     int ret;
 603     unsigned loops = 0;
 604
 605     do {
 606         if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 607             panicf("SD bank %d error : 0x%x", bank,
 608                     transfer_error[INTERNAL_AS3525]);
 609
 610         ret = sd_wait_for_state(INTERNAL_AS3525, SD_TRAN);
 611         if (ret < 0)
 612             return ret - 2;
 613
 614         if(!send_cmd(INTERNAL_AS3525, SD_SWITCH_FUNC, 0x80ffffef, MCI_ARG, NULL))
 615             return -1;
 616
 617         mci_delay();
 618
 619         if(!send_cmd(INTERNAL_AS3525, 35, 0, MCI_NO_FLAGS, NULL))
 620             return -2;
 621
 622         mci_delay();
 623
 624         memset(uncached_buffer, 0, 512);
 625         if(bank == -1)
 626         {   /* enable bank switching */
 627             uncached_buffer[0] = 16;
 628             uncached_buffer[1] = 1;
 629             uncached_buffer[2] = 10;
 630         }
 631         else
 632             uncached_buffer[0] = bank;
 633
 634         dma_retain();
 635         /* we don't use the uncached buffer here, because we need the
 636          * physical memory address for DMA transfers */
 637         dma_enable_channel(0, aligned_buffer, MCI_FIFO(INTERNAL_AS3525),
 638             DMA_PERI_SD, DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8,
 639             NULL);
 640
 641         MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT;
 642         MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
 643         MCI_DATA_CTRL(INTERNAL_AS3525) =  (1<<0) /* enable */   |
 644                                 (0<<1) /* transfer direction */ |
 645                                 (1<<3) /* DMA */                |
 646                                 (9<<4) /* 2^9 = 512 */ ;
 647
 648         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 649         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 650
 651         /*  Wait for FIFO to empty, card may still be in PRG state  */
 652         while(MCI_STATUS(INTERNAL_AS3525) & MCI_TX_ACTIVE );
 653
 654         dma_release();
 655
 656     } while(transfer_error[INTERNAL_AS3525]);
 657
 658     card_info[INTERNAL_AS3525].current_bank = (bank == -1) ? 0 : bank;
 659
 660     return 0;
 661 }
 662
 663 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 664                                int count, void* buf, const bool write)
 665 {
 666 #ifndef HAVE_MULTIDRIVE
 667     const int drive = 0;
 668 #endif
 669     int ret = 0;
 670     unsigned loops = 0;
 671
 672     mutex_lock(&sd_mtx);
 673 #ifndef BOOTLOADER
 674     sd_enable(true);
 675     led(true);
 676 #endif
 677
 678     if (card_info[drive].initialized <= 0)
 679     {
 680         ret = sd_init_card(drive);
 681         if (!(card_info[drive].initialized))
 682             goto sd_transfer_error;
 683     }
 684
 685     if((start+count) > card_info[drive].numblocks)
 686     {
 687         ret = -20;
 688         goto sd_transfer_error;
 689     }
 690
 691     /* skip SanDisk OF */
 692     if (drive == INTERNAL_AS3525)
 693         start += AMS_OF_SIZE;
 694
 695     last_disk_activity = current_tick;
 696
 697     dma_retain();
 698
 699     while(count)
 700     {
 701         /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
 702          * register, so we have to transfer maximum 127 sectors at a time. */
 703         unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
 704         void *dma_buf;
 705         const int cmd =
 706             write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 707         unsigned long bank_start = start;
 708
 709         /* Only switch banks for internal storage */
 710         if(drive == INTERNAL_AS3525)
 711         {
 712             unsigned int bank = start / BLOCKS_PER_BANK; /* Current bank */
 713
 714             /* Switch bank if needed */
 715             if(card_info[INTERNAL_AS3525].current_bank != bank)
 716             {
 717                 ret = sd_select_bank(bank);
 718                 if (ret < 0)
 719                 {
 720                     ret -= 20;
 721                     goto sd_transfer_error;
 722                 }
 723             }
 724
 725             /* Adjust start block in current bank */
 726             bank_start -= bank * BLOCKS_PER_BANK;
 727
 728             /* Do not cross a bank boundary in a single transfer loop */
 729             if((transfer + bank_start) > BLOCKS_PER_BANK)
 730                 transfer = BLOCKS_PER_BANK - bank_start;
 731         }
 732
 733         /* Set bank_start to the correct unit (blocks or bytes) */
 734         if(!(card_info[drive].ocr & (1<<30)))   /* not SDHC */
 735             bank_start *= SD_BLOCK_SIZE;
 736
 737         dma_buf = aligned_buffer;
 738         if(transfer > UNALIGNED_NUM_SECTORS)
 739             transfer = UNALIGNED_NUM_SECTORS;
 740
 741         if(write)
 742             memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 743
 744         ret = sd_wait_for_state(drive, SD_TRAN);
 745         if (ret < 0)
 746         {
 747             ret -= 2*20;
 748             goto sd_transfer_error;
 749         }
 750
 751         if(!send_cmd(drive, cmd, bank_start, MCI_ARG, NULL))
 752         {
 753             ret -= 3*20;
 754             goto sd_transfer_error;
 755         }
 756
 757         if(write)
 758         {
 759             dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
 760                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 761                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 762
 763             /*Small delay for writes prevents data crc failures at lower freqs*/
 764 #ifdef HAVE_MULTIDRIVE
 765             if((drive == SD_SLOT_AS3525) && !hs_card)
 766             {
 767                 int write_delay = 125;
 768                 while(write_delay--);
 769             }
 770 #endif
 771         }
 772         else
 773             dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
 774                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 775                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 776
 777         MCI_DATA_TIMER(drive) = write ?
 778                 SD_MAX_WRITE_TIMEOUT : SD_MAX_READ_TIMEOUT;
 779         MCI_DATA_LENGTH(drive) = transfer * SD_BLOCK_SIZE;
 780         MCI_DATA_CTRL(drive) =  (1<<0) /* enable */                     |
 781                                 (!write<<1) /* transfer direction */    |
 782                                 (1<<3) /* DMA */                        |
 783                                 (9<<4) /* 2^9 = 512 */ ;
 784
 785         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 786         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 787
 788         /*  Wait for FIFO to empty, card may still be in PRG state for writes */
 789         while(MCI_STATUS(drive) & MCI_TX_ACTIVE);
 790
 791         last_disk_activity = current_tick;
 792
 793         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_FLAGS, NULL))
 794         {
 795             ret = -4*20;
 796             goto sd_transfer_error;
 797         }
 798
 799         if(!transfer_error[drive])
 800         {
 801             if(!write)
 802                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 803             buf += transfer * SD_BLOCK_SIZE;
 804             start += transfer;
 805             count -= transfer;
 806             loops = 0;  /* reset errors counter */
 807         }
 808         else if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 809                 panicf("SD Xfer %s err:0x%x Disk%d", (write? "write": "read"),
 810                                                   transfer_error[drive], drive);
 811     }
 812
 813     ret = 0;    /* success */
 814
 815 sd_transfer_error:
 816
 817     dma_release();
 818
 819 #ifndef BOOTLOADER
 820     led(false);
 821     sd_enable(false);
 822 #endif
 823
 824     if (ret)    /* error */
 825         card_info[drive].initialized = 0;
 826
 827     mutex_unlock(&sd_mtx);
 828     return ret;
 829 }
 830
 831 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 832                      void* buf)
 833 {
 834     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 835 }
 836
 837 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 838                      const void* buf)
 839 {
 840
 841 #ifdef BOOTLOADER /* we don't need write support in bootloader */
 842 #ifdef HAVE_MULTIDRIVE
 843     (void) drive;
 844 #endif
 845     (void) start;
 846     (void) count;
 847     (void) buf;
 848     return -1;
 849 #else
 850     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 851 #endif
 852 }
 853
 854 #ifndef BOOTLOADER
 855 long sd_last_disk_activity(void)
 856 {
 857     return last_disk_activity;
 858 }
 859
 860 void sd_enable(bool on)
 861 {
 862 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 863     extern int buttonlight_is_on;
 864 #endif
 865
 866 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 867     static bool cpu_boosted = false;
 868 #endif
 869
 870     if (sd_enabled == on)
 871         return; /* nothing to do */
 872     if(on)
 873     {
 874         /*  Enable both NAF_CLOCK & IDE clk for internal SD */
 875         CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
 876         CGU_IDE  |= (1<<6);     /* enable non AHB interface*/
 877 #ifdef HAVE_MULTIDRIVE
 878         /* Enable MCI clk for uSD */
 879         CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 880 #ifdef HAVE_BUTTON_LIGHT
 881         /* buttonlight AMSes need a bit of special handling for the buttonlight
 882          * here due to the dual mapping of GPIOD and XPD */
 883         CCU_IO |= (1<<2);              /* XPD is SD-MCI interface (b3:2 = 01) */
 884         if (buttonlight_is_on)
 885             GPIOD_DIR &= ~(1<<7);
 886         else
 887             _buttonlight_off();
 888 #endif /* HAVE_BUTTON_LIGHT */
 889 #endif /* HAVE_MULTIDRIVE */
 890         sd_enabled = true;
 891
 892 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 893         if(card_detect_target())  /* If SD card present Boost cpu for voltage */
 894         {
 895             cpu_boosted = true;
 896             cpu_boost(true);
 897         }
 898 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 899     }
 900     else
 901     {
 902 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 903         if(cpu_boosted)
 904         {
 905             cpu_boost(false);
 906             cpu_boosted = false;
 907         }
 908 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 909
 910         sd_enabled = false;
 911
 912 #ifdef HAVE_MULTIDRIVE
 913 #ifdef HAVE_BUTTON_LIGHT
 914         CCU_IO &= ~(1<<2);           /* XPD is general purpose IO (b3:2 = 00) */
 915         if (buttonlight_is_on)
 916             _buttonlight_on();
 917 #endif /* HAVE_BUTTON_LIGHT */
 918         /* Disable MCI clk for uSD */
 919         CGU_PERI &= ~CGU_MCI_CLOCK_ENABLE;
 920 #endif /* HAVE_MULTIDRIVE */
 921
 922         /*  Disable both NAF_CLOCK & IDE clk for internal SD */
 923         CGU_PERI &= ~CGU_NAF_CLOCK_ENABLE;
 924         CGU_IDE &= ~(1<<6);       /* disable non AHB interface*/
 925     }
 926 }
 927
 928 tCardInfo *card_get_info_target(int card_no)
 929 {
 930     return &card_info[card_no];
 931 }
 932
 933 #ifdef HAVE_HOTSWAP
 934 void card_enable_monitoring_target(bool on)
 935 {
 936     if (on) /* enable interrupt */
 937         GPIOA_IE |= EXT_SD_BITS;
 938     else    /* disable interrupt */
 939         GPIOA_IE &= ~EXT_SD_BITS;
 940 }
 941 #endif /* HAVE_HOTSWAP */
 942
 943 #endif /* !BOOTLOADER */
 944
 945 #ifdef CONFIG_STORAGE_MULTI
 946 int sd_num_drives(int first_drive)
 947 {
 948     /* We don't care which logical drive number(s) we have been assigned */
 949     (void)first_drive;
 950
 951     return NUM_DRIVES;
 952 }
 953 #endif /* CONFIG_STORAGE_MULTI */