firmware/target/arm/imx31/avic-imx31.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by James Espinoza
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef AVIC_IMX31_H
  22 #define AVIC_IMX31_H
  23
  24 /* #define IRQ priorities for different modules (0-15) */
  25 #define INT_PRIO_DEFAULT    7
  26 #define INT_PRIO_DVFS       (INT_PRIO_DEFAULT+1)
  27 #define INT_PRIO_DPTC       (INT_PRIO_DEFAULT+1)
  28 #define INT_PRIO_SDMA       (INT_PRIO_DEFAULT+2)
  29
  30 enum INT_TYPE
  31 {
  32     INT_TYPE_IRQ = 0,
  33     INT_TYPE_FIQ
  34 };
  35
  36 enum IMX31_INT_LIST
  37 {
  38     __IMX31_INT_FIRST = -1,
  39    INT_RESERVED0, INT_RESERVED1,     INT_RESERVED2, INT_I2C3,
  40    INT_I2C2,      INT_MPEG4_ENCODER, INT_RTIC,      INT_FIR,
  41    INT_MMC_SDHC2, INT_MMC_SDHC1,     INT_I2C1,      INT_SSI2,
  42    INT_SSI1,      INT_CSPI2,         INT_CSPI1,     INT_ATA,
  43    INT_MBX,       INT_CSPI3,         INT_UART3,     INT_IIM,
  44    INT_SIM1,      INT_SIM2,          INT_RNGA,      INT_EVTMON,
  45    INT_KPP,       INT_RTC,           INT_PWN,       INT_EPIT2,
  46    INT_EPIT1,     INT_GPT,           INT_PWR_FAIL,  INT_CCM_DVFS,
  47    INT_UART2,     INT_NANDFC,        INT_SDMA,      INT_USB_HOST1,
  48    INT_USB_HOST2, INT_USB_OTG,       INT_RESERVED3, INT_MSHC1,
  49    INT_MSHC2,     INT_IPU_ERR,       INT_IPU,       INT_RESERVED4,
  50    INT_RESERVED5, INT_UART1,         INT_UART4,     INT_UART5,
  51    INT_ETC_IRQ,   INT_SCC_SCM,       INT_SCC_SMN,   INT_GPIO2,
  52    INT_GPIO1,     INT_CCM_CLK,       INT_PCMCIA,    INT_WDOG,
  53    INT_GPIO3,     INT_RESERVED6,     INT_EXT_PWMG,  INT_EXT_TEMP,
  54    INT_EXT_SENS1, INT_EXT_SENS2,     INT_EXT_WDOG,  INT_EXT_TV,
  55    INT_ALL
  56 };
  57
  58 void avic_init(void);
  59 void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype,
  60                      unsigned long ni_priority, void (*handler)(void));
  61 void avic_set_int_priority(enum IMX31_INT_LIST ints,
  62                            unsigned long ni_priority);
  63 void avic_disable_int(enum IMX31_INT_LIST ints);
  64 void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype);
  65
  66 #define AVIC_NIL_DISABLE 15
  67 #define AVIC_NIL_ENABLE  (-1)
  68 void avic_set_ni_level(int level);
  69
  70
  71 /* Call a service routine while allowing preemption by interrupts of higher
  72  * priority. Avoid using any app or other SVC stack by doing it with a mini
  73  * "stack on irq stack". Avoid actually enabling IRQ until the routine
  74  * decides to do so; epilogue code will always disable them again. */
  75 #define AVIC_NESTED_NI_CALL_PROLOGUE(prio, stacksize) \
  76 ({ asm volatile ( \
  77         "sub    lr, lr, #4               \n" /* prepare return address */ \
  78         "srsdb  #0x12!                   \n" /* save LR_irq and SPSR_irq */ \
  79         "stmfd  sp!, { r0-r3, r12 }      \n" /* preserve context */ \
  80         "mov    r0, #0x68000000          \n" /* AVIC_BASE_ADDR */ \
  81         "mov    r1, %0                   \n" /* load interrupt level */ \
  82         "ldr    r2, [r0, #0x04]          \n" /* save NIMASK */ \
  83         "str    r1, [r0, #0x04]          \n" /* set interrupt level */ \
  84         "mov    r0, sp                   \n" /* grab IRQ stack */ \
  85         "sub    sp, sp, %1               \n" /* allocate space for routine to SP_irq */ \
  86         "cps    #0x13                    \n" /* change to SVC mode */ \
  87         "mov    r1, sp                   \n" /* save SP_svc */ \
  88         "mov    sp, r0                   \n" /* switch to SP_irq *copy* */ \
  89         "stmfd  sp!, { r1, r2, lr }      \n" /* push SP_svc, NIMASK and LR_svc */ \
  90         : : "i"(prio), "i"(stacksize)); })
  91
  92 #define AVIC_NESTED_NI_CALL_EPILOGUE(stacksize) \
  93 ({ asm volatile ( \
  94         "cpsid  i                        \n" /* disable IRQ */ \
  95         "ldmfd  sp!, { r1, r2, lr }      \n" /* pop SP_svc, NIMASK and LR_svc */ \
  96         "mov    sp, r1                   \n" /* restore SP_svc */ \
  97         "cps    #0x12                    \n" /* return to IRQ mode */ \
  98         "add    sp, sp, %0               \n" /* deallocate routine space */ \
  99         "mov    r0, #0x68000000          \n" /* AVIC BASE ADDR */ \
 100         "str    r2, [r0, #0x04]          \n" /* restore NIMASK */ \
 101         "ldmfd  sp!, { r0-r3, r12 }      \n" /* reload context */ \
 102         "rfefd  sp!                      \n" /* move stacked SPSR to CPSR, return */ \
 103         : : "i"(stacksize)); })
 104
 105 #endif /* AVIC_IMX31_H */