apps/codecs/libspc/spc_emu.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006-2007 Adam Gashlin (hcs)
  11  * Copyright (C) 2004-2007 Shay Green (blargg)
  12  * Copyright (C) 2002 Brad Martin
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  20  * KIND, either express or implied.
  21  *
  22  ****************************************************************************/
  23 #include "codeclib.h"
  24 #include "spc_codec.h"
  25 #include "spc_profiler.h"
  26
  27 /* lovingly ripped off from Game_Music_Emu 0.5.2. http://www.slack.net/~ant/ */
  28 /* DSP Based on Brad Martin's OpenSPC DSP emulator */
  29 /* tag reading from sexyspc by John Brawn (John_Brawn@yahoo.com) and others */
  30
  31 struct cpu_ram_t ram IBSS_ATTR_SPC_LARGE_IRAM CACHEALIGN_ATTR;
  32
  33 /**************** Timers ****************/
  34
  35 void Timer_run_( struct Timer* t, long time )
  36 {
  37     /* when disabled, next_tick should always be in the future */
  38     assert( t->enabled );
  39
  40     int elapsed = ((time - t->next_tick) >> t->shift) + 1;
  41     t->next_tick += elapsed << t->shift;
  42
  43     elapsed += t->count;
  44     if ( elapsed >= t->period ) /* avoid unnecessary division */
  45     {
  46         int n = elapsed / t->period;
  47         elapsed -= n * t->period;
  48         t->counter = (t->counter + n) & 15;
  49     }
  50     t->count = elapsed;
  51 }
  52
  53 /**************** SPC emulator ****************/
  54 /* 1.024 MHz clock / 32000 samples per second */
  55
  56 static void SPC_enable_rom( THIS, int enable )
  57 {
  58     if ( this->rom_enabled != enable )
  59     {
  60         this->rom_enabled = enable;
  61         ci->memcpy( RAM + ROM_ADDR, (enable ? this->boot_rom : this->extra_ram), ROM_SIZE );
  62         /* TODO: ROM can still get overwritten when DSP writes to echo buffer */
  63     }
  64 }
  65
  66 void SPC_Init( THIS )
  67 {
  68     this->timer [0].shift = 4 + 3; /* 8 kHz */
  69     this->timer [1].shift = 4 + 3; /* 8 kHz */
  70     this->timer [2].shift = 4; /* 8 kHz */
  71
  72     /* Put STOP instruction around memory to catch PC underflow/overflow. */
  73     ci->memset( ram.padding1, 0xFF, sizeof ram.padding1 );
  74     ci->memset( ram.padding2, 0xFF, sizeof ram.padding2 );
  75
  76     /* A few tracks read from the last four bytes of IPL ROM */
  77     this->boot_rom [sizeof this->boot_rom - 2] = 0xC0;
  78     this->boot_rom [sizeof this->boot_rom - 1] = 0xFF;
  79     ci->memset( this->boot_rom, 0, sizeof this->boot_rom - 2 );
  80
  81     /* Have DSP in a defined state in case EMU is run and hasn't loaded
  82      * a program yet */
  83     DSP_reset(&this->dsp);
  84 }
  85
  86 static void SPC_load_state( THIS, struct cpu_regs_t const* cpu_state,
  87         const void* new_ram, const void* dsp_state )
  88 {
  89     ci->memcpy(&(this->r),cpu_state,sizeof this->r);
  90
  91     /* ram */
  92     ci->memcpy( RAM, new_ram, sizeof RAM );
  93     ci->memcpy( this->extra_ram, RAM + ROM_ADDR, sizeof this->extra_ram );
  94
  95     /* boot rom (have to force enable_rom() to update it) */
  96     this->rom_enabled = !(RAM [0xF1] & 0x80);
  97     SPC_enable_rom( this, !this->rom_enabled );
  98
  99     /* dsp */
 100     /* some SPCs rely on DSP immediately generating one sample */
 101     this->extra_cycles = 32;
 102     DSP_reset( &this->dsp );
 103     int i;
 104     for ( i = 0; i < REGISTER_COUNT; i++ )
 105         DSP_write( &this->dsp, i, ((uint8_t const*) dsp_state) [i] );
 106
 107     /* timers */
 108     for ( i = 0; i < TIMER_COUNT; i++ )
 109     {
 110         struct Timer* t = &this->timer [i];
 111
 112         t->next_tick = -EXTRA_CLOCKS;
 113         t->enabled = (RAM [0xF1] >> i) & 1;
 114         if ( !t->enabled )
 115             t->next_tick = TIMER_DISABLED_TIME;
 116         t->count = 0;
 117         t->counter = RAM [0xFD + i] & 15;
 118
 119         int p = RAM [0xFA + i];
 120         if ( !p )
 121             p = 0x100;
 122         t->period = p;
 123     }
 124
 125     /* Handle registers which already give 0 when read by
 126        setting RAM and not changing it.
 127        Put STOP instruction in registers which can be read,
 128        to catch attempted execution. */
 129     RAM [0xF0] = 0;
 130     RAM [0xF1] = 0;
 131     RAM [0xF3] = 0xFF;
 132     RAM [0xFA] = 0;
 133     RAM [0xFB] = 0;
 134     RAM [0xFC] = 0;
 135     RAM [0xFD] = 0xFF;
 136     RAM [0xFE] = 0xFF;
 137     RAM [0xFF] = 0xFF;
 138 }
 139
 140 static void clear_echo( THIS )
 141 {
 142     if ( !(DSP_read( &this->dsp, 0x6C ) & 0x20) )
 143     {
 144         unsigned addr = 0x100 * DSP_read( &this->dsp, 0x6D );
 145         size_t   size = 0x800 * DSP_read( &this->dsp, 0x7D );
 146         size_t max_size = sizeof RAM - addr;
 147         if ( size > max_size )
 148             size = sizeof RAM - addr;
 149         ci->memset( RAM + addr, 0xFF, size );
 150     }
 151 }
 152
 153 int SPC_load_spc( THIS, const void* data, long size )
 154 {
 155     struct spc_file_t const* spc = (struct spc_file_t const*) data;
 156     struct cpu_regs_t regs;
 157
 158     if ( size < SPC_FILE_SIZE )
 159         return -1;
 160
 161     if ( ci->memcmp( spc->signature, "SNES-SPC700 Sound File Data", 27 ) != 0 )
 162         return -1;
 163
 164     regs.pc     = spc->pc [1] * 0x100 + spc->pc [0];
 165     regs.a      = spc->a;
 166     regs.x      = spc->x;
 167     regs.y      = spc->y;
 168     regs.status = spc->status;
 169     regs.sp     = spc->sp;
 170
 171     if ( (unsigned long) size >= sizeof *spc )
 172         ci->memcpy( this->boot_rom, spc->ipl_rom, sizeof this->boot_rom );
 173
 174     SPC_load_state( this, &regs, spc->ram, spc->dsp );
 175
 176     clear_echo(this);
 177
 178     return 0;
 179 }
 180
 181 /**************** DSP interaction ****************/
 182 void SPC_run_dsp_( THIS, long time )
 183 {
 184     /* divide by CLOCKS_PER_SAMPLE */
 185     int count = ((time - this->next_dsp) >> 5) + 1;
 186     int32_t* buf = this->sample_buf;
 187     this->sample_buf = buf + count;
 188     this->next_dsp += count * CLOCKS_PER_SAMPLE;
 189     DSP_run( &this->dsp, count, buf );
 190 }
 191
 192 int SPC_read( THIS, unsigned addr, long const time )
 193 {
 194     int result = RAM [addr];
 195
 196     if ( ((unsigned) (addr - 0xF0)) < 0x10 )
 197     {
 198         assert( 0xF0 <= addr && addr <= 0xFF );
 199
 200         /* counters */
 201         int i = addr - 0xFD;
 202         if ( i >= 0 )
 203         {
 204             struct Timer* t = &this->timer [i];
 205             Timer_run( t, time );
 206             result = t->counter;
 207             t->counter = 0;
 208         }
 209         /* dsp */
 210         else if ( addr == 0xF3 )
 211         {
 212             SPC_run_dsp( this, time );
 213             result = DSP_read( &this->dsp, RAM [0xF2] & 0x7F );
 214         }
 215     }
 216     return result;
 217 }
 218
 219 void SPC_write( THIS, unsigned addr, int data, long const time )
 220 {
 221     /* first page is very common */
 222     if ( addr < 0xF0 )
 223     {
 224         RAM [addr] = (uint8_t) data;
 225     }
 226     else switch ( addr )
 227     {
 228         /* RAM */
 229         default:
 230             if ( addr < ROM_ADDR )
 231             {
 232                 RAM [addr] = (uint8_t) data;
 233             }
 234             else
 235             {
 236                 this->extra_ram [addr - ROM_ADDR] = (uint8_t) data;
 237                 if ( !this->rom_enabled )
 238                     RAM [addr] = (uint8_t) data;
 239             }
 240             break;
 241
 242         /* DSP */
 243         /*case 0xF2:*/ /* mapped to RAM */
 244         case 0xF3: {
 245             SPC_run_dsp( this, time );
 246             int reg = RAM [0xF2];
 247             if ( reg < REGISTER_COUNT ) {
 248                 DSP_write( &this->dsp, reg, data );
 249             }
 250             else {
 251                 /*dprintf( "DSP write to $%02X\n", (int) reg ); */
 252             }
 253             break;
 254         }
 255
 256         case 0xF0: /* Test register */
 257             /*dprintf( "Wrote $%02X to $F0\n", (int) data ); */
 258             break;
 259
 260         /* Config */
 261         case 0xF1:
 262         {
 263             int i;
 264             /* timers */
 265             for ( i = 0; i < TIMER_COUNT; i++ )
 266             {
 267                 struct Timer * t = this->timer+i;
 268                 if ( !(data & (1 << i)) )
 269                 {
 270                     t->enabled = 0;
 271                     t->next_tick = TIMER_DISABLED_TIME;
 272                 }
 273                 else if ( !t->enabled )
 274                 {
 275                     /* just enabled */
 276                     t->enabled = 1;
 277                     t->counter = 0;
 278                     t->count = 0;
 279                     t->next_tick = time;
 280                 }
 281             }
 282
 283             /* port clears */
 284             if ( data & 0x10 )
 285             {
 286                 RAM [0xF4] = 0;
 287                 RAM [0xF5] = 0;
 288             }
 289             if ( data & 0x20 )
 290             {
 291                 RAM [0xF6] = 0;
 292                 RAM [0xF7] = 0;
 293             }
 294
 295             SPC_enable_rom( this, (data & 0x80) != 0 );
 296             break;
 297         }
 298
 299         /* Ports */
 300         case 0xF4:
 301         case 0xF5:
 302         case 0xF6:
 303         case 0xF7:
 304             /* to do: handle output ports */
 305             break;
 306
 307         /* verified on SNES that these are read/write (RAM) */
 308         /*case 0xF8: */
 309         /*case 0xF9: */
 310
 311         /* Timers */
 312         case 0xFA:
 313         case 0xFB:
 314         case 0xFC: {
 315             int i = addr - 0xFA;
 316             struct Timer* t = &this->timer [i];
 317             if ( (t->period & 0xFF) != data )
 318             {
 319                 Timer_run( t, time );
 320                 this->timer[i].period = data ? data : 0x100;
 321             }
 322             break;
 323         }
 324
 325         /* Counters (cleared on write) */
 326         case 0xFD:
 327         case 0xFE:
 328         case 0xFF:
 329             /*dprintf( "Wrote to counter $%02X\n", (int) addr ); */
 330             this->timer [addr - 0xFD].counter = 0;
 331             break;
 332     }
 333 }
 334
 335 /**************** Sample generation ****************/
 336 int SPC_play( THIS, long count, int32_t* out )
 337 {
 338     int i;
 339     assert( count % 2 == 0 ); /* output is always in pairs of samples */
 340
 341     long start_time = -(count >> 1) * CLOCKS_PER_SAMPLE - EXTRA_CLOCKS;
 342
 343     /* DSP output is made on-the-fly when DSP registers are read or written */
 344     this->sample_buf = out;
 345     this->next_dsp = start_time + CLOCKS_PER_SAMPLE;
 346
 347     /* Localize timer next_tick times and run them to the present to prevent
 348        a running but ignored timer's next_tick from getting too far behind
 349        and overflowing. */
 350     for ( i = 0; i < TIMER_COUNT; i++ )
 351     {
 352         struct Timer* t = &this->timer [i];
 353         if ( t->enabled )
 354         {
 355             t->next_tick += start_time + EXTRA_CLOCKS;
 356             Timer_run( t, start_time );
 357         }
 358     }
 359
 360     /* Run from start_time to 0, pre-advancing by extra cycles from last run */
 361     this->extra_cycles = CPU_run( this, start_time + this->extra_cycles ) +
 362                          EXTRA_CLOCKS;
 363     if ( this->extra_cycles < 0 )
 364     {
 365         /*dprintf( "Unhandled instruction $%02X, pc = $%04X\n",
 366                 (int) CPU_read( r.pc ), (unsigned) r.pc ); */
 367
 368         return -1;
 369     }
 370
 371     /* Catch DSP up to present */
 372 #if 0
 373     ENTER_TIMER(cpu);
 374 #endif
 375     SPC_run_dsp( this, -EXTRA_CLOCKS );
 376 #if 0
 377     EXIT_TIMER(cpu);
 378 #endif
 379     assert( this->next_dsp == CLOCKS_PER_SAMPLE - EXTRA_CLOCKS );
 380     assert( this->sample_buf - out == count );
 381
 382     return 0;
 383 }