firmware/target/arm/rk27xx/sd-rk27xx.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  * Copyright (C) 2011 Marcin Bukat
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  20  * KIND, either express or implied.
  21  *
  22  ****************************************************************************/
  23
  24 #include "config.h" /* for HAVE_MULTIVOLUME */
  25 #include "fat.h"
  26 #include "thread.h"
  27 #include "gcc_extensions.h"
  28 #include "led.h"
  29 #include "sdmmc.h"
  30 #include "system.h"
  31 #include "kernel.h"
  32 #include "cpu.h"
  33 #include <stdio.h>
  34 #include <stdlib.h>
  35 #include <string.h>
  36 #include "panic.h"
  37 #include "stdbool.h"
  38 #include "ata_idle_notify.h"
  39 #include "sd.h"
  40 #include "usb.h"
  41
  42 #ifdef HAVE_HOTSWAP
  43 #include "disk.h"
  44 #endif
  45
  46 #include "lcd.h"
  47 #include <stdarg.h>
  48 #include "sysfont.h"
  49
  50 #define RES_NO (-1)
  51
  52 static tCardInfo card_info;
  53
  54 /* for compatibility */
  55 static long last_disk_activity = -1;
  56
  57 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
  58 static const char         sd_thread_name[] = "ata/sd";
  59 static struct mutex       sd_mtx SHAREDBSS_ATTR;
  60 static struct event_queue sd_queue;
  61 #ifndef BOOTLOADER
  62 bool sd_enabled = false;
  63 #endif
  64
  65 static struct semaphore transfer_completion_signal;
  66 static struct semaphore command_completion_signal;
  67 static volatile bool retry;
  68 static volatile int cmd_error;
  69
  70 /* interrupt handler for SD */
  71 void INT_SD(void)
  72 {
  73     const int status = SD_INT;
  74
  75     SD_INT = 0; /* disable sd interrupts, clear pending interrupts */
  76
  77     /* cmd and response status pending */
  78     if(status & CMD_RES_STAT)
  79     {
  80         /* get the status */
  81         cmd_error = SD_CMDRES;
  82         semaphore_release(&command_completion_signal);
  83     }
  84
  85     /* data transfer status pending */
  86     if(status & DATA_XFER_STAT)
  87     {
  88         cmd_error = SD_DATAT;
  89         if (cmd_error & DATA_XFER_ERR)
  90             retry = true;
  91
  92         semaphore_release(&transfer_completion_signal);
  93     }
  94
  95     SD_INT = CMD_RES_INT_EN | DATA_XFER_INT_EN;
  96 }
  97
  98 /* Exchange buffers - the one where SD module puts into/reads from
  99  * data and the one controlled by MCU. This allows some overlap
 100  * in transfer operations and should increase throuput.
 101  */
 102 static void mmu_switch_buff(void)
 103 {
 104     static unsigned int i = 0;
 105
 106     if (i++ & 0x01)
 107     {
 108         MMU_CTRL = MMU_MMU0_BUFII | MMU_CPU_BUFI | MMU_BUFII_RESET |
 109                    MMU_BUFII_BYTE | MMU_BUFI_RESET | MMU_BUFI_WORD;
 110     }
 111     else
 112     {
 113         MMU_CTRL = MMU_MMU0_BUFI | MMU_CPU_BUFII | MMU_BUFII_RESET |
 114                    MMU_BUFII_WORD | MMU_BUFI_RESET | MMU_BUFI_BYTE;
 115     }
 116 }
 117
 118 /* Reset internal pointers of the MMU submodule */
 119 static void mmu_buff_reset(void)
 120 {
 121     MMU_CTRL |= MMU_BUFII_RESET | MMU_BUFI_RESET;
 122 }
 123
 124 /* My generic device uses PC7 pin, active low */
 125 static inline bool card_detect_target(void)
 126 {
 127     return !(GPIO_PCDR & 0x80);
 128 }
 129
 130 /* Send command to the SD card. Command finish is signaled in ISR */
 131 static bool send_cmd(const int cmd, const int arg, const int res,
 132         unsigned long *response)
 133 {
 134     SD_CMD = arg;
 135
 136     if (res > 0)
 137        SD_CMDREST = CMD_XFER_START | RES_XFER_START | res | cmd;
 138     else
 139        SD_CMDREST = CMD_XFER_START | RES_XFER_END | RES_R1 | cmd;
 140
 141     semaphore_wait(&command_completion_signal, TIMEOUT_BLOCK);
 142
 143     /*  Handle command responses & errors */
 144     if(res != RES_NO)
 145     {
 146         if(cmd_error & STAT_CMD_RES_ERR)
 147             return false;
 148
 149         if(res == RES_R2)
 150         {
 151             response[0] = SD_RES3;
 152             response[1] = SD_RES2;
 153             response[2] = SD_RES1;
 154             response[3] = SD_RES0;
 155         }
 156         else
 157             response[0] = SD_RES3;
 158     }
 159     return true;
 160 }
 161
 162 #if 0
 163 /* for some misterious reason the card does not report itself as being in TRAN
 164  * but transfers are successful. Rockchip OF does not check the card state
 165  * after SELECT. I checked two different cards.
 166  */
 167 static void print_card_status(void)
 168 {
 169     unsigned long response;
 170     send_cmd(SD_SEND_STATUS, card_info.rca, RES_R1,
 171              &response);
 172
 173     printf("card status: 0x%0x, state: 0x%0x", response, (response>>9)&0xf);
 174 }
 175
 176 static int sd_wait_for_tran_state(void)
 177 {
 178     unsigned long response;
 179     unsigned int timeout = current_tick + 5*HZ;
 180     int cmd_retry = 10;
 181
 182     while (1)
 183     {
 184         while (!send_cmd(SD_SEND_STATUS, card_info.rca, RES_R1,
 185                          &response) && cmd_retry > 0)
 186         {
 187             cmd_retry--;
 188         }
 189
 190         if (cmd_retry <= 0)
 191         {
 192             return -1;
 193         }
 194
 195         if (((response >> 9) & 0xf) == SD_TRAN)
 196         {
 197             return 0;
 198         }
 199
 200         if(TIME_AFTER(current_tick, timeout))
 201         {
 202             return -10 * ((response >> 9) & 0xf);
 203         }
 204
 205         last_disk_activity = current_tick;
 206     }
 207 }
 208 #endif
 209
 210 static bool sd_wait_card_busy(void)
 211 {
 212     unsigned int timeout = current_tick + 5*HZ;
 213
 214     while (!(SD_CARD & SD_CARD_BSY))
 215     {
 216         if(TIME_AFTER(current_tick, timeout))
 217             return false;
 218     }
 219
 220     return true;
 221 }
 222
 223 static int sd_init_card(void)
 224 {
 225     unsigned long response;
 226     long init_timeout;
 227     bool sd_v2 = false;
 228
 229     card_info.rca = 0;
 230
 231     /*  assume 50 MHz APB freq / 125 = 400 kHz  */
 232     SD_CTRL = (SD_CTRL & ~(0x7FF)) | 0x7D;
 233
 234     /* 100 - 400kHz clock required for Identification Mode  */
 235     /*  Start of Card Identification Mode ************************************/
 236
 237     /* CMD0 Go Idle  */
 238     if(!send_cmd(SD_GO_IDLE_STATE, 0, RES_NO, NULL))
 239         return -1;
 240
 241     sleep(1);
 242
 243     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 244       Non v2 cards will not respond to this command*/
 245     if(send_cmd(SD_SEND_IF_COND, 0x1AA, RES_R6, &response))
 246         if((response & 0xFFF) == 0x1AA)
 247             sd_v2 = true;
 248
 249     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 250     init_timeout = current_tick + HZ;
 251
 252     do {
 253         /* this timeout is the only valid error for this loop*/
 254         if(TIME_AFTER(current_tick, init_timeout))
 255             return -2;
 256
 257         if(!send_cmd(SD_APP_CMD, card_info.rca, RES_R1, &response))
 258             return -3;
 259
 260         sleep(1); /* bus conflict otherwise */
 261
 262          /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 263         if(!send_cmd(SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 264                      RES_R3, &card_info.ocr))
 265             return -4;
 266     } while(!(card_info.ocr & (1<<31)) );
 267
 268     /* CMD2 send CID */
 269     if(!send_cmd(SD_ALL_SEND_CID, 0, RES_R2, card_info.cid))
 270         return -5;
 271
 272     /* CMD3 send RCA */
 273     if(!send_cmd(SD_SEND_RELATIVE_ADDR, 0, RES_R6, &card_info.rca))
 274         return -6;
 275
 276     /*  End of Card Identification Mode   ************************************/
 277
 278     /*  Card back to full speed  25MHz*/
 279     SD_CTRL = (SD_CTRL & ~0x7FF) | 1; /* FIXME check this divider - OF uses 0 here*/
 280
 281     /* CMD9 send CSD */
 282     if(!send_cmd(SD_SEND_CSD, card_info.rca, RES_R2, card_info.csd))
 283         return -11;
 284
 285     sd_parse_csd(&card_info);
 286
 287     if(!send_cmd(SD_SELECT_CARD, card_info.rca, RES_R1b, &response))
 288         return -20;
 289
 290     if (!sd_wait_card_busy())
 291         return -21;
 292
 293     card_info.initialized = 1;
 294
 295     return 0;
 296 }
 297
 298 static void sd_thread(void) NORETURN_ATTR;
 299 static void sd_thread(void)
 300 {
 301     struct queue_event ev;
 302     bool idle_notified = false;
 303
 304     while (1)
 305     {
 306         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 307
 308         switch ( ev.id )
 309         {
 310 #ifdef HAVE_HOTSWAP
 311         case SYS_HOTSWAP_INSERTED:
 312         case SYS_HOTSWAP_EXTRACTED:
 313         {
 314             int microsd_init = 1;
 315             fat_lock();          /* lock-out FAT activity first -
 316                                     prevent deadlocking via disk_mount that
 317                                     would cause a reverse-order attempt with
 318                                     another thread */
 319             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 320                                     into driver that bypass the fat cache */
 321
 322             /* We now have exclusive control of fat cache and ata */
 323
 324             disk_unmount(sd_first_drive);     /* release "by force", ensure file
 325                                     descriptors aren't leaked and any busy
 326                                     ones are invalid if mounting */
 327             /* Force card init for new card, re-init for re-inserted one or
 328              * clear if the last attempt to init failed with an error. */
 329             card_info.initialized = 0;
 330
 331             if (ev.id == SYS_HOTSWAP_INSERTED)
 332             {
 333                 sd_enable(true);
 334                 microsd_init = sd_init_card(sd_first_drive);
 335                 if (microsd_init < 0) /* initialisation failed */
 336                     panicf("microSD init failed : %d", microsd_init);
 337
 338                 microsd_init = disk_mount(sd_first_drive); /* 0 if fail */
 339             }
 340
 341             /*
 342              * Mount succeeded, or this was an EXTRACTED event,
 343              * in both cases notify the system about the changed filesystems
 344              */
 345             if (microsd_init)
 346                 queue_broadcast(SYS_FS_CHANGED, 0);
 347
 348             sd_enable(false);
 349
 350             /* Access is now safe */
 351             mutex_unlock(&sd_mtx);
 352             fat_unlock();
 353             }
 354             break;
 355 #endif
 356         case SYS_TIMEOUT:
 357             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 358             {
 359                 idle_notified = false;
 360             }
 361             else if (!idle_notified)
 362             {
 363                 call_storage_idle_notifys(false);
 364                 idle_notified = true;
 365             }
 366             break;
 367
 368         case SYS_USB_CONNECTED:
 369             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 370             /* Wait until the USB cable is extracted again */
 371             usb_wait_for_disconnect(&sd_queue);
 372
 373             break;
 374         }
 375     }
 376 }
 377
 378 static void init_controller(void)
 379 {
 380     /* reset SD module */
 381     SCU_RSTCFG |= (1<<9);
 382     sleep(1);
 383     SCU_RSTCFG &= ~(1<<9);
 384
 385     /* set pins functions as SD signals */
 386     SCU_IOMUXA_CON |= IOMUX_SD;
 387
 388     /* enable and unmask SD interrupts in interrupt controller */
 389     INTC_IMR |= (1<<10);
 390     INTC_IECR |= (1<<10);
 391
 392     SD_CTRL = SD_PWR_CPU | SD_DETECT_MECH | SD_CLOCK_EN | 0x7D;
 393     SD_INT = CMD_RES_INT_EN | DATA_XFER_INT_EN;
 394     SD_CARD = SD_CARD_SELECT | SD_CARD_PWR_EN;
 395
 396     /* setup mmu buffers */
 397     MMU_PNRI = 0x1ff;
 398     MMU_PNRII = 0x1ff;
 399     MMU_CTRL = MMU_MMU0_BUFII | MMU_CPU_BUFI | MMU_BUFII_RESET |
 400                MMU_BUFII_BYTE | MMU_BUFI_RESET | MMU_BUFI_WORD;
 401
 402 }
 403
 404 int sd_init(void)
 405 {
 406     int ret;
 407
 408     semaphore_init(&transfer_completion_signal, 1, 0);
 409     semaphore_init(&command_completion_signal, 1, 0);
 410
 411     init_controller();
 412
 413     ret = sd_init_card();
 414     if(ret < 0)
 415         return ret;
 416
 417     /* init mutex */
 418     mutex_init(&sd_mtx);
 419
 420     queue_init(&sd_queue, true);
 421     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 422             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 423
 424     return 0;
 425 }
 426
 427 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 428                     void* buf)
 429 {
 430 #ifdef HAVE_MULTIDRIVE
 431     (void)drive;
 432 #endif
 433     unsigned long response;
 434     unsigned int retry_cnt = 0;
 435     int cnt, ret = 0;
 436     unsigned char *dst;
 437
 438     mutex_lock(&sd_mtx);
 439     sd_enable(true);
 440
 441     if (count <= 0 || start + count > card_info.numblocks)
 442         return -1;
 443
 444     if(!(card_info.ocr & (1<<30)))
 445         start <<= 9; /* not SDHC */
 446
 447     /* setup A2A DMA CH0 */
 448     A2A_ISRC0 = (unsigned long)(&MMU_DATA);
 449     A2A_ICNT0 = 512;
 450     A2A_LCNT0 = 1;
 451     A2A_DOMAIN = 0;
 452
 453     while (retry_cnt++ < 20)
 454     {
 455         cnt = count;
 456         dst = (unsigned char *)buf;
 457
 458         ret = 0;
 459         retry = false;       /* reset retry flag */
 460         mmu_buff_reset();    /* reset recive buff state */
 461
 462         /* issue read command to the card */
 463         if (!send_cmd(SD_READ_MULTIPLE_BLOCK, start, RES_R1, &response))
 464         {
 465             ret = -4;
 466             continue;
 467         }
 468
 469         while (cnt > 0)
 470         {
 471             if (cnt == 1)
 472             {
 473                 /* last block to tranfer */
 474                 SD_DATAT = DATA_XFER_START | DATA_XFER_READ |
 475                            DATA_BUS_1LINE | DATA_XFER_DMA_DIS |
 476                            DATA_XFER_SINGLE;
 477             }
 478             else
 479             {
 480                 /* more than one block to transfer */
 481                 SD_DATAT = DATA_XFER_START | DATA_XFER_READ |
 482                            DATA_BUS_1LINE | DATA_XFER_DMA_DIS |
 483                            DATA_XFER_MULTI;
 484             }
 485
 486             /* wait for transfer completion */
 487             semaphore_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 488
 489             if (retry)
 490             {
 491                 /* data transfer error */
 492                 ret = -5;
 493                 break;
 494             }
 495
 496             /* exchange buffers */
 497             mmu_switch_buff();
 498
 499             last_disk_activity = current_tick;
 500
 501             /* transfer data from receive buffer to the dest
 502              * for (i=0; i<(512/4); i++)
 503              *    *dst++ = MMU_DATA;
 504              *
 505              * below is DMA version in software mode.
 506              * SD module provides DMAreq signals and all this
 507              * can be done in hardware in theory but I can't
 508              * figure this out. OF doesn't use DMA at all.
 509              */
 510             A2A_IDST0 = (unsigned long)dst;
 511             A2A_CON0  = (3<<9) | (1<<6) | (1<<3) | (2<<1) | (1<<0);
 512
 513             /* wait for DMA engine to finish transfer */
 514             while (A2A_DMA_STS & 1);
 515
 516             dst += 512;
 517             cnt--;
 518         } /* while (cnt > 0) */
 519
 520         if (!send_cmd(SD_STOP_TRANSMISSION, 0, RES_R1b, &response))
 521             ret = -6;
 522
 523         /* transfer successfull - leave retry loop */
 524         if (ret == 0)
 525             break;
 526     }
 527
 528     sd_enable(false);
 529     mutex_unlock(&sd_mtx);
 530
 531     return ret;
 532 }
 533
 534 /* Not tested */
 535 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 536                      const void* buf)
 537 {
 538 #ifdef HAVE_MULTIDRIVE
 539     (void) drive;
 540 #endif
 541 #if defined(BOOTLOADER) /* we don't need write support in bootloader */
 542     (void) start;
 543     (void) count;
 544     (void) buf;
 545     return -1;
 546 #else
 547     unsigned long response;
 548     unsigned int retry_cnt = 0;
 549     int cnt, ret = 0;
 550     unsigned char *src;
 551     bool card_selected = false;
 552
 553     mutex_lock(&sd_mtx);
 554     sd_enable(true);
 555
 556     if (count <= 0 || start + count > card_info.numblocks)
 557         return -1;
 558
 559     if(!(card_info.ocr & (1<<30)))
 560         start <<= 9; /* not SDHC */
 561
 562     /* setup A2A DMA CH0 */
 563     A2A_IDST0 = (unsigned long)(&MMU_DATA);
 564     A2A_ICNT0 = 512;
 565     A2A_LCNT0 = 1;
 566     A2A_DOMAIN = 0;
 567
 568     while (retry_cnt++ < 20)
 569     {
 570         cnt = count;
 571         src = (unsigned char *)buf;
 572
 573         ret = 0;
 574         retry = false;       /* reset retry flag */
 575         mmu_buff_reset();    /* reset recive buff state */
 576
 577         if (!send_cmd(SD_WRITE_MULTIPLE_BLOCK, start, RES_R1, &response))
 578         {
 579             ret = -3;
 580             continue;
 581         }
 582
 583         while (cnt > 0)
 584         {
 585             /* transfer data from receive buffer to the dest
 586              * for (i=0; i<(512/4); i++)
 587              *    MMU_DATA = *src++;
 588              *
 589              * Below is DMA version in software mode.
 590              */
 591
 592             A2A_ISRC0 = (unsigned long)src;
 593             A2A_CON0  = (3<<9) | (1<<5) | (1<<3) | (2<<1) | (1<<0);
 594
 595             while (A2A_DMA_STS & 1);
 596
 597             src += 512;
 598
 599             /* exchange buffers */
 600             mmu_switch_buff();
 601
 602             if (cnt == 1)
 603             {
 604                 /* last block to tranfer */
 605                 SD_DATAT = DATA_XFER_START | DATA_XFER_WRITE |
 606                            DATA_BUS_1LINE | DATA_XFER_DMA_DIS |
 607                            DATA_XFER_SINGLE;
 608
 609             }
 610             else
 611             {
 612                 /* more than one block to transfer */
 613                 SD_DATAT = DATA_XFER_START | DATA_XFER_WRITE |
 614                            DATA_BUS_1LINE | DATA_XFER_DMA_DIS |
 615                            DATA_XFER_MULTI;
 616
 617             }
 618
 619             /* wait for transfer completion */
 620             semaphore_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 621
 622             if (retry)
 623             {
 624                 /* data transfer error */
 625                 ret = -3;
 626                 break;
 627             }
 628
 629             cnt--;
 630         } /* while (cnt > 0) */
 631
 632         if (!send_cmd(SD_STOP_TRANSMISSION, 0, RES_R1b, &response))
 633             ret = -4;
 634
 635         if (!sd_wait_card_busy())
 636             ret = -5;
 637
 638         /* transfer successfull - leave retry loop */
 639         if (ret == 0)
 640             break;
 641     }
 642
 643     sd_enable(false);
 644     mutex_unlock(&sd_mtx);
 645
 646     return ret;
 647
 648 #endif /* defined(BOOTLOADER) */
 649 }
 650
 651 void sd_enable(bool on)
 652 {
 653     /* enable or disable clock signal for SD module */
 654     if (on)
 655     {
 656         SCU_CLKCFG &= ~(1<<22);
 657     }
 658     else
 659     {
 660         SCU_CLKCFG |= (1<<22);
 661     }
 662 }
 663
 664 #ifndef BOOTLOADER
 665 long sd_last_disk_activity(void)
 666 {
 667     return last_disk_activity;
 668 }
 669
 670 tCardInfo *card_get_info_target(int card_no)
 671 {
 672     (void)card_no;
 673     return &card_info;
 674 }
 675 #endif /* BOOTLOADER */
 676
 677 #ifdef HAVE_HOTSWAP
 678 /* Not complete and disabled in config */
 679 bool sd_removable(IF_MD_NONVOID(int drive))
 680 {
 681     (void)drive;
 682     return true;
 683 }
 684
 685 bool sd_present(IF_MD_NONVOID(int drive))
 686 {
 687     (void)drive;
 688     return card_detect_target();
 689 }
 690
 691 static int sd_oneshot_callback(struct timeout *tmo)
 692 {
 693     (void)tmo;
 694
 695     /* This is called only if the state was stable for 300ms - check state
 696      * and post appropriate event. */
 697     if (card_detect_target())
 698     {
 699         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 700     }
 701     else
 702         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 703
 704     return 0;
 705 }
 706
 707 /* interrupt handler for SD detect */
 708
 709 #endif /* HAVE_HOTSWAP */
 710
 711 #ifdef CONFIG_STORAGE_MULTI
 712 int sd_num_drives(int first_drive)
 713 {
 714     (void)first_drive;
 715
 716     /* we have only one SD drive */
 717     return 1;
 718 }
 719 #endif /* CONFIG_STORAGE_MULTI */