firmware/target/arm/as3525/sd-as3525v2.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h" /* for HAVE_MULTIVOLUME */
  24 #include "fat.h"
  25 #include "thread.h"
  26 #include "hotswap.h"
  27 #include "system.h"
  28 #include "kernel.h"
  29 #include "cpu.h"
  30 #include <stdio.h>
  31 #include <stdlib.h>
  32 #include <string.h>
  33 #include "as3525v2.h"
  34 #include "pl081.h"  /* DMA controller */
  35 #include "dma-target.h" /* DMA request lines */
  36 #include "clock-target.h"
  37 #include "panic.h"
  38 #include "stdbool.h"
  39 #include "ata_idle_notify.h"
  40 #include "sd.h"
  41
  42 #include "lcd.h"
  43 #include <stdarg.h>
  44 #include "sysfont.h"
  45
  46 /* command flags */
  47 #define MCI_NO_RESP     (0<<0)
  48 #define MCI_RESP        (1<<0)
  49 #define MCI_LONG_RESP   (1<<1)
  50
  51 /* controller registers */
  52 #define SD_BASE 0xC6070000
  53
  54 #define SD_REG(x)       (*(volatile unsigned long *) (SD_BASE+x))
  55
  56 #define MCI_CTRL        SD_REG(0x00)
  57
  58 /* control bits */
  59 #define CTRL_RESET      (1<<0)
  60 #define FIFO_RESET      (1<<1)
  61 #define DMA_RESET       (1<<2)
  62 #define INT_ENABLE      (1<<4)
  63 #define DMA_ENABLE      (1<<5)
  64 #define READ_WAIT       (1<<6)
  65 #define SEND_IRQ_RESP   (1<<7)
  66 #define ABRT_READ_DATA  (1<<8)
  67 #define SEND_CCSD       (1<<9)
  68 #define SEND_AS_CCSD    (1<<10)
  69 #define EN_OD_PULLUP    (1<<24)
  70
  71
  72 #define MCI_PWREN       SD_REG(0x04)    /* power enable */
  73 #define MCI_CLKDIV      SD_REG(0x08)    /* clock divider */
  74 #define MCI_CLKSRC      SD_REG(0x0C)    /* clock source */
  75 #define MCI_CLKENA      SD_REG(0x10)    /* clock enable */
  76 #define MCI_TMOUT       SD_REG(0x14)    /* timeout */
  77
  78 #define MCI_CTYPE       SD_REG(0x18)    /* card type */
  79                                         /* 1 bit per card, set = wide bus */
  80
  81 #define MCI_BLKSIZ      SD_REG(0x1C)    /* block size */
  82 #define MCI_BYTCNT      SD_REG(0x20)    /* byte count */
  83 #define MCI_MASK        SD_REG(0x24)    /* interrupt mask */
  84
  85 #define MCI_ARGUMENT    SD_REG(0x28)
  86 #define MCI_COMMAND     SD_REG(0x2C)
  87
  88 /* command bits (bits 5:0 are the command index) */
  89 #define CMD_RESP_EXP_BIT        (1<<6)
  90 #define CMD_RESP_LENGTH_BIT     (1<<7)
  91 #define CMD_CHECK_CRC_BIT       (1<<8)
  92 #define CMD_DATA_EXP_BIT        (1<<9)
  93 #define CMD_RW_BIT              (1<<10)
  94 #define CMD_TRANSMODE_BIT       (1<<11)
  95 #define CMD_SENT_AUTO_STOP_BIT  (1<<12)
  96 #define CMD_WAIT_PRV_DAT_BIT    (1<<13)
  97 #define CMD_ABRT_CMD_BIT        (1<<14)
  98 #define CMD_SEND_INIT_BIT       (1<<15)
  99 #define CMD_SEND_CLK_ONLY       (1<<21)
 100 #define CMD_READ_CEATA          (1<<22)
 101 #define CMD_CCS_EXPECTED        (1<<23)
 102 #define CMD_DONE_BIT            (1<<31)
 103
 104
 105 #define MCI_RESP0       SD_REG(0x30)
 106 #define MCI_RESP1       SD_REG(0x34)
 107 #define MCI_RESP2       SD_REG(0x38)
 108 #define MCI_RESP3       SD_REG(0x3C)
 109
 110 #define MCI_MASK_STATUS SD_REG(0x40)    /* masked interrupt status */
 111 #define MCI_RAW_STATUS  SD_REG(0x44)    /* raw interrupt status, also used as
 112                                          * status clear */
 113 #define MCI_STATUS      SD_REG(0x48)
 114
 115 /*
 116  *  STATUS register
 117  *  & 0xBA80    = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
 118  *                  MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
 119  *  & 8         = MCI_INT_DTO
 120  *  & 0x428     = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
 121  *  & 0x418     = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
 122  */
 123
 124 /* interrupt bits */
 125 #define MCI_INT_CRDDET  (1<<0)      /* card detect */
 126 #define MCI_INT_RE      (1<<1)      /* response error */
 127 #define MCI_INT_CD      (1<<2)      /* command done */
 128 #define MCI_INT_DTO     (1<<3)      /* data transfer over */
 129 #define MCI_INT_TXDR    (1<<4)      /* tx fifo data request */
 130 #define MCI_INT_RXDR    (1<<5)      /* rx fifo data request */
 131 #define MCI_INT_RCRC    (1<<6)      /* response crc error */
 132 #define MCI_INT_DCRC    (1<<7)      /* data crc error */
 133 #define MCI_INT_RTO     (1<<8)      /* response timeout */
 134 #define MCI_INT_DRTO    (1<<9)      /* data read timeout */
 135 #define MCI_INT_HTO     (1<<10)     /* data starv timeout */
 136 #define MCI_INT_FRUN    (1<<11)     /* fifo over/underrun */
 137 #define MCI_INT_HLE     (1<<12)     /* hw locked while error */
 138 #define MCI_INT_SBE     (1<<13)     /* start bit error */
 139 #define MCI_INT_ACD     (1<<14)     /* auto command done */
 140 #define MCI_INT_EBE     (1<<15)     /* end bit error */
 141 #define MCI_INT_SDIO    (0xf<<16)
 142
 143 #define MCI_ERROR   (MCI_INT_RE | MCI_INT_RCRC | MCI_INT_DCRC /*| MCI_INT_RTO*/ \
 144                    | MCI_INT_DRTO | MCI_INT_HTO | MCI_INT_FRUN | MCI_INT_HLE \
 145                    | MCI_INT_SBE | MCI_INT_EBE)
 146
 147 #define MCI_FIFOTH      SD_REG(0x4C)    /* FIFO threshold */
 148 /* TX watermark :    bits 11:0
 149  * RX watermark :    bits 27:16
 150  * DMA MTRANS SIZE : bits 30:28
 151  * bits 31, 15:12 : unused
 152  */
 153 #define MCI_FIFOTH_MASK 0x8000f000
 154
 155 #define MCI_CDETECT     SD_REG(0x50)    /* card detect */
 156 #define MCI_WRTPRT      SD_REG(0x54)    /* write protect */
 157 #define MCI_GPIO        SD_REG(0x58)
 158 #define MCI_TCBCNT      SD_REG(0x5C)    /* transferred CIU byte count */
 159 #define MCI_TBBCNT      SD_REG(0x60)    /* transferred host/DMA to/from bytes */
 160 #define MCI_DEBNCE      SD_REG(0x64)    /* card detect debounce */
 161 #define MCI_USRID       SD_REG(0x68)    /* user id */
 162 #define MCI_VERID       SD_REG(0x6C)    /* version id */
 163
 164 #define MCI_HCON        SD_REG(0x70)    /* hardware config */
 165 /* bit 0 : card type
 166  * bits 5:1 : maximum card index */
 167
 168 #define MCI_BMOD        SD_REG(0x80)    /* bus mode */
 169 #define MCI_PLDMND      SD_REG(0x84)    /* poll demand */
 170 #define MCI_DBADDR      SD_REG(0x88)    /* descriptor base address */
 171 #define MCI_IDSTS       SD_REG(0x8C)    /* internal DMAC status */
 172 #define MCI_IDINTEN     SD_REG(0x90)    /* internal DMAC interrupt enable */
 173 #define MCI_DSCADDR     SD_REG(0x94)    /* current host descriptor address */
 174 #define MCI_BUFADDR     SD_REG(0x98)    /* current host buffer address */
 175
 176 #define MCI_FIFO        ((unsigned long *) (SD_BASE+0x100))
 177
 178 #define UNALIGNED_NUM_SECTORS 10
 179 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 180 static unsigned char *uncached_buffer = UNCACHED_ADDR(&aligned_buffer[0]);
 181
 182 static int sd_init_card(void);
 183 static void init_controller(void);
 184
 185 static tCardInfo card_info;
 186
 187 /* for compatibility */
 188 static long last_disk_activity = -1;
 189
 190 #define MIN_YIELD_PERIOD 5  /* ticks */
 191 static long next_yield = 0;
 192
 193 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 194 static const char         sd_thread_name[] = "ata/sd";
 195 static struct mutex       sd_mtx SHAREDBSS_ATTR;
 196 static struct event_queue sd_queue;
 197 #ifndef BOOTLOADER
 198 bool sd_enabled = false;
 199 #endif
 200
 201 static struct wakeup transfer_completion_signal;
 202 static volatile bool retry;
 203 static volatile bool data_transfer = false;
 204
 205 static inline void mci_delay(void) { int i = 0xffff; while(i--) ; }
 206
 207 void INT_NAND(void)
 208 {
 209     MCI_CTRL &= ~INT_ENABLE;
 210     const int status = MCI_MASK_STATUS;
 211
 212     MCI_RAW_STATUS = status;    /* clear status */
 213
 214     if(status & MCI_ERROR)
 215         retry = true;
 216
 217     if(data_transfer && status & (MCI_INT_DTO|MCI_ERROR))
 218         wakeup_signal(&transfer_completion_signal);
 219
 220     MCI_CTRL |= INT_ENABLE;
 221 }
 222
 223 static bool send_cmd(const int cmd, const int arg, const int flags,
 224         unsigned long *response)
 225 {
 226     MCI_COMMAND = cmd;
 227
 228     if(flags & MCI_RESP)
 229     {
 230         MCI_COMMAND |= CMD_RESP_EXP_BIT;
 231         if(flags & MCI_LONG_RESP)
 232             MCI_COMMAND |= CMD_RESP_LENGTH_BIT;
 233     }
 234
 235     if(cmd == SD_READ_MULTIPLE_BLOCK || cmd == SD_WRITE_MULTIPLE_BLOCK)
 236     {
 237         MCI_COMMAND |= CMD_WAIT_PRV_DAT_BIT | CMD_DATA_EXP_BIT;
 238         if(cmd == SD_WRITE_MULTIPLE_BLOCK)
 239             MCI_COMMAND |= CMD_RW_BIT | CMD_CHECK_CRC_BIT;
 240     }
 241
 242     int clkena = MCI_CLKENA;
 243     MCI_CLKENA = 0;
 244
 245     MCI_ARGUMENT = arg;
 246     MCI_COMMAND |= CMD_DONE_BIT;
 247
 248     int max = 0x40000;
 249     while(MCI_COMMAND & CMD_DONE_BIT)
 250     {
 251         if(--max == 0)  /* timeout */
 252         {
 253             MCI_CLKENA = clkena;
 254             return false;
 255         }
 256     }
 257
 258     MCI_CLKENA = clkena;
 259
 260     if(flags & MCI_RESP)
 261     {
 262         if(flags & MCI_LONG_RESP)
 263         {
 264             /* store the response in little endian order for the words */
 265             response[0] = MCI_RESP3;
 266             response[1] = MCI_RESP2;
 267             response[2] = MCI_RESP1;
 268             response[3] = MCI_RESP0;
 269         }
 270         else
 271             response[0] = MCI_RESP0;
 272     }
 273     return true;
 274 }
 275
 276 static int sd_init_card(void)
 277 {
 278     unsigned long response;
 279     unsigned long temp_reg[4];
 280     int max_tries = 100; /* max acmd41 attemps */
 281     bool sd_v2;
 282     int i;
 283
 284     if(!send_cmd(SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 285         return -1;
 286
 287     mci_delay();
 288
 289     sd_v2 = false;
 290     if(send_cmd(SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 291         if((response & 0xFFF) == 0x1AA)
 292             sd_v2 = true;
 293
 294     do {
 295         /* some MicroSD cards seems to need more delays, so play safe */
 296         mci_delay();
 297         mci_delay();
 298         mci_delay();
 299
 300         /* app_cmd */
 301         if( !send_cmd(SD_APP_CMD, 0, MCI_RESP, &response) ||
 302             !(response & (1<<5)))
 303         {
 304             return -2;
 305         }
 306
 307         /* acmd41 */
 308         if(!send_cmd(SD_APP_OP_COND, (sd_v2 ? 0x40FF8000 : (1<<23)),
 309                         MCI_RESP, &card_info.ocr))
 310             return -3;
 311     } while(!(card_info.ocr & (1<<31)) && max_tries--);
 312
 313     if(max_tries < 0)
 314         return -4;
 315
 316     mci_delay();
 317     mci_delay();
 318     mci_delay();
 319
 320     /* send CID */
 321     if(!send_cmd(SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info.cid))
 322         return -5;
 323
 324     /* send RCA */
 325     if(!send_cmd(SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info.rca))
 326         return -6;
 327
 328     /* send CSD */
 329     if(!send_cmd(SD_SEND_CSD, card_info.rca,
 330                  MCI_RESP|MCI_LONG_RESP, temp_reg))
 331         return -7;
 332
 333     for(i=0; i<4; i++)
 334         card_info.csd[3-i] = temp_reg[i];
 335
 336     sd_parse_csd(&card_info);
 337
 338     if(!send_cmd(SD_APP_CMD, 0, MCI_RESP, &response) ||
 339        !send_cmd(42, 0, MCI_NO_RESP, NULL)) /* disconnect the 50 KOhm pull-up
 340                                                resistor on CD/DAT3 */
 341         return -13;
 342
 343     if(!send_cmd(SD_APP_CMD, card_info.rca, MCI_NO_RESP, NULL))
 344         return -10;
 345
 346     if(!send_cmd(SD_SET_BUS_WIDTH, card_info.rca | 2, MCI_NO_RESP, NULL))
 347         return -11;
 348
 349     if(!send_cmd(SD_SELECT_CARD, card_info.rca, MCI_NO_RESP, NULL))
 350         return -9;
 351
 352     /* not sent in init_card() by OF */
 353     if(!send_cmd(SD_SET_BLOCKLEN, card_info.blocksize, MCI_NO_RESP,
 354                  NULL))
 355         return -12;
 356
 357     card_info.initialized = 1;
 358
 359     return 0;
 360 }
 361
 362 static void sd_thread(void) __attribute__((noreturn));
 363 static void sd_thread(void)
 364 {
 365     struct queue_event ev;
 366     bool idle_notified = false;
 367
 368     while (1)
 369     {
 370         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 371
 372         switch ( ev.id )
 373         {
 374         case SYS_TIMEOUT:
 375             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 376             {
 377                 idle_notified = false;
 378             }
 379             else
 380             {
 381                 /* never let a timer wrap confuse us */
 382                 next_yield = current_tick;
 383
 384                 if (!idle_notified)
 385                 {
 386                     call_storage_idle_notifys(false);
 387                     idle_notified = true;
 388                 }
 389             }
 390             break;
 391 #if 0
 392         case SYS_USB_CONNECTED:
 393             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 394             /* Wait until the USB cable is extracted again */
 395             usb_wait_for_disconnect(&sd_queue);
 396
 397             break;
 398         case SYS_USB_DISCONNECTED:
 399             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 400             break;
 401 #endif
 402         }
 403     }
 404 }
 405
 406 static void init_controller(void)
 407 {
 408     int idx = (MCI_HCON >> 1) & 31;
 409     int idx_bits = (1 << idx) -1;
 410
 411     MCI_PWREN &= ~idx_bits;
 412     MCI_PWREN = idx_bits;
 413
 414     mci_delay();
 415
 416     MCI_CLKSRC = 0;
 417     MCI_CLKDIV = 0;
 418
 419     MCI_CTRL |= CTRL_RESET;
 420     while(MCI_CTRL & CTRL_RESET)
 421         ;
 422
 423     MCI_RAW_STATUS = 0xffffffff;
 424
 425     MCI_TMOUT = 0xffffffff;
 426
 427     MCI_CTYPE = 0;
 428
 429     MCI_CLKENA = idx_bits;
 430
 431     MCI_ARGUMENT = 0;
 432     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 433     while(MCI_COMMAND & CMD_DONE_BIT)
 434         ;
 435
 436     MCI_DEBNCE = 0xfffff;   /* default value */
 437
 438     MCI_FIFOTH &= MCI_FIFOTH_MASK;
 439     MCI_FIFOTH |= 0x503f0080;
 440
 441     MCI_MASK = 0xffffffff & ~(MCI_INT_ACD|MCI_INT_CRDDET);
 442
 443     MCI_CTRL |= INT_ENABLE;
 444 }
 445
 446 int sd_init(void)
 447 {
 448     int ret;
 449     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 450
 451     CGU_IDE =   (1<<7)  /* AHB interface enable */  |
 452                 (1<<6)  /* interface enable */      |
 453                 ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) << 2) |
 454                 1;       /* clock source = PLLA */
 455
 456     CGU_MEMSTICK = (1<<8) | (1<<7) |
 457         ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1) << 2) | 1;
 458
 459     /* FIXME: divider should be shifted by 2, but doing prevents card
 460      * initialisation */
 461     *(volatile int*)(CGU_BASE+0x3C) = (1<<7) |
 462         (CLK_DIV(AS3525_PLLA_FREQ, 24000000) -1) | 1;
 463
 464     wakeup_init(&transfer_completion_signal);
 465
 466     VIC_INT_ENABLE |= INTERRUPT_NAND;
 467
 468     init_controller();
 469     ret = sd_init_card();
 470     if(ret < 0)
 471         return ret;
 472
 473     /* init mutex */
 474     mutex_init(&sd_mtx);
 475
 476     queue_init(&sd_queue, true);
 477     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 478             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 479
 480 #ifndef BOOTLOADER
 481     sd_enabled = true;
 482     sd_enable(false);
 483 #endif
 484     return 0;
 485 }
 486
 487 #ifdef STORAGE_GET_INFO
 488 void sd_get_info(struct storage_info *info)
 489 {
 490     info->sector_size=card_info.blocksize;
 491     info->num_sectors=card_info.numblocks;
 492     info->vendor="Rockbox";
 493     info->product = "Internal Storage";
 494     info->revision="0.00";
 495 }
 496 #endif
 497
 498 static int sd_wait_for_state(unsigned int state)
 499 {
 500     unsigned long response;
 501     unsigned int timeout = 100; /* ticks */
 502     long t = current_tick;
 503
 504     while (1)
 505     {
 506         long tick;
 507
 508         if(!send_cmd(SD_SEND_STATUS, card_info.rca,
 509                     MCI_RESP, &response))
 510             return -1;
 511
 512         if (((response >> 9) & 0xf) == state)
 513             return 0;
 514
 515         if(TIME_AFTER(current_tick, t + timeout))
 516             return -10 * ((response >> 9) & 0xf);
 517
 518         if (TIME_AFTER((tick = current_tick), next_yield))
 519         {
 520             yield();
 521             timeout += current_tick - tick;
 522             next_yield = tick + MIN_YIELD_PERIOD;
 523         }
 524     }
 525 }
 526
 527 static int sd_transfer_sectors(unsigned long start, int count, void* buf, bool write)
 528 {
 529     int ret = 0;
 530
 531     /* skip SanDisk OF */
 532     start += 0xf000;
 533
 534     mutex_lock(&sd_mtx);
 535 #ifndef BOOTLOADER
 536     sd_enable(true);
 537 #endif
 538
 539     if (card_info.initialized <= 0)
 540     {
 541         ret = sd_init_card();
 542         if (!(card_info.initialized))
 543         {
 544             panicf("card not initialised (%d)", ret);
 545             goto sd_transfer_error;
 546         }
 547     }
 548
 549     last_disk_activity = current_tick;
 550     ret = sd_wait_for_state(SD_TRAN);
 551     if (ret < 0)
 552     {
 553         static const char *st[9] = {
 554             "IDLE", "RDY", "IDENT", "STBY", "TRAN", "DATA", "RCV", "PRG", "DIS"
 555         };
 556         if(ret <= -10)
 557             panicf("wait for state failed (%s)", st[(-ret / 10) % 9]);
 558         else
 559             panicf("wait for state failed");
 560         goto sd_transfer_error;
 561     }
 562
 563     dma_retain();
 564
 565     const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 566
 567     /* Interrupt handler might set this to true during transfer */
 568     do
 569     {
 570         void *dma_buf = aligned_buffer;
 571         unsigned int transfer = count;
 572         if(transfer > UNALIGNED_NUM_SECTORS)
 573             transfer = UNALIGNED_NUM_SECTORS;
 574
 575         if(write)
 576             memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 577
 578         retry = false;
 579
 580         MCI_BLKSIZ = SD_BLOCK_SIZE;
 581         MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
 582
 583         MCI_CTRL |= (FIFO_RESET|DMA_RESET);
 584         while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
 585             ;
 586
 587         MCI_CTRL |= DMA_ENABLE;
 588         MCI_MASK = MCI_INT_CD|MCI_INT_DTO|MCI_INT_DCRC|MCI_INT_DRTO| \
 589             MCI_INT_HTO|MCI_INT_FRUN|MCI_INT_HLE|MCI_INT_SBE|MCI_INT_EBE;
 590
 591         MCI_FIFOTH &= MCI_FIFOTH_MASK;
 592         MCI_FIFOTH |= 0x503f0080;
 593
 594
 595         if(card_info.ocr & (1<<30) ) /* SDHC */
 596             ret = send_cmd(cmd, start, MCI_NO_RESP, NULL);
 597         else
 598             ret = send_cmd(cmd, start * SD_BLOCK_SIZE,
 599                     MCI_NO_RESP, NULL);
 600
 601         if (ret < 0)
 602             panicf("transfer multiple blocks failed (%d)", ret);
 603
 604         if(write)
 605             dma_enable_channel(0, dma_buf, MCI_FIFO, DMA_PERI_SD,
 606                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 607         else
 608             dma_enable_channel(0, MCI_FIFO, dma_buf, DMA_PERI_SD,
 609                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 610
 611         data_transfer = true;
 612         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 613         data_transfer = false;
 614
 615         last_disk_activity = current_tick;
 616
 617         if(!send_cmd(SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
 618         {
 619             ret = -666;
 620             panicf("STOP TRANSMISSION failed");
 621             goto sd_transfer_error;
 622         }
 623
 624         ret = sd_wait_for_state(SD_TRAN);
 625         if (ret < 0)
 626         {
 627             panicf(" wait for state TRAN failed (%d)", ret);
 628             goto sd_transfer_error;
 629         }
 630
 631         if(!retry)
 632         {
 633             if(!write)
 634                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 635             buf += transfer * SD_BLOCK_SIZE;
 636             start += transfer;
 637             count -= transfer;
 638         }
 639     } while(retry || count);
 640
 641     dma_release();
 642
 643 #ifndef BOOTLOADER
 644     sd_enable(false);
 645 #endif
 646     mutex_unlock(&sd_mtx);
 647     return 0;
 648
 649 sd_transfer_error:
 650     panicf("transfer error : %d",ret);
 651     card_info.initialized = 0;
 652     return ret;
 653 }
 654
 655 int sd_read_sectors(unsigned long start, int count, void* buf)
 656 {
 657     return sd_transfer_sectors(start, count, buf, false);
 658 }
 659
 660 int sd_write_sectors(unsigned long start, int count, const void* buf)
 661 {
 662 #if 1 /* disabled until stable*/ \
 663     || defined(BOOTLOADER) /* we don't need write support in bootloader */
 664     (void) start;
 665     (void) count;
 666     (void) buf;
 667     return -1;
 668 #else
 669     return sd_transfer_sectors(start, count, (void*)buf, true);
 670 #endif
 671 }
 672
 673 #ifndef BOOTLOADER
 674 long sd_last_disk_activity(void)
 675 {
 676     return last_disk_activity;
 677 }
 678
 679 void sd_enable(bool on)
 680 {
 681     /* TODO */
 682     (void)on;
 683     return;
 684 }
 685
 686 tCardInfo *card_get_info_target(int card_no)
 687 {
 688     (void)card_no;
 689     return &card_info;
 690 }
 691
 692 #endif /* BOOTLOADER */