apps/codecs/libspc/spc_codec.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007-2008 Michael Sevakis (jhMikeS)
  11  * Copyright (C) 2006-2007 Adam Gashlin (hcs)
  12  * Copyright (C) 2004-2007 Shay Green (blargg)
  13  * Copyright (C) 2002 Brad Martin
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version 2
  18  * of the License, or (at your option) any later version.
  19  *
  20  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  21  * KIND, either express or implied.
  22  *
  23  ****************************************************************************/
  24
  25 /* lovingly ripped off from Game_Music_Emu 0.5.2. http://www.slack.net/~ant/ */
  26 /* DSP Based on Brad Martin's OpenSPC DSP emulator */
  27 /* tag reading from sexyspc by John Brawn (John_Brawn@yahoo.com) and others */
  28
  29 #ifndef _SPC_CODEC_H_
  30 #define _SPC_CODEC_H_
  31
  32 /* rather than comment out asserts, just define NDEBUG */
  33 #ifndef NDEBUG
  34 #define NDEBUG
  35 #endif
  36 #include <assert.h>
  37
  38 /** Basic configuration options **/
  39
  40 #ifndef ARM_ARCH
  41 #define ARM_ARCH 0
  42 #endif
  43
  44 #define SPC_DUAL_CORE 1
  45
  46 #if !defined(SPC_DUAL_CORE) || NUM_CORES == 1
  47 #undef  SPC_DUAL_CORE
  48 #define SPC_DUAL_CORE 0
  49 #endif
  50
  51 /* TGB is the only target fast enough for gaussian and realtime BRR decode */
  52 /* echo is almost fast enough but not quite */
  53 #if defined(TOSHIBA_GIGABEAT_F) || defined(TOSHIBA_GIGABEAT_S) ||\
  54     (CONFIG_PLATFORM & PLATFORM_HOSTED) || MEMORYSIZE <= 2
  55     /* Don't cache BRR waves */
  56     #define SPC_BRRCACHE 0
  57
  58     /* Allow gaussian interpolation */
  59     #define SPC_NOINTERP 0
  60
  61     /* Allow echo processing */
  62     #define SPC_NOECHO 0
  63 #elif defined(CPU_COLDFIRE)
  64     /* Cache BRR waves */
  65     #define SPC_BRRCACHE 1
  66
  67     /* Disable gaussian interpolation */
  68     #define SPC_NOINTERP 1
  69
  70     /* Allow echo processing */
  71     #define SPC_NOECHO 0
  72 #elif defined (CPU_PP) && SPC_DUAL_CORE
  73     /* Cache BRR waves */
  74     #define SPC_BRRCACHE 1
  75
  76     /* Disable gaussian interpolation */
  77     #define SPC_NOINTERP 1
  78
  79     /* Allow echo processing */
  80     #define SPC_NOECHO 0
  81 #else
  82     /* Cache BRR waves */
  83     #define SPC_BRRCACHE 1
  84
  85     /* Disable gaussian interpolation */
  86     #define SPC_NOINTERP 1
  87
  88     /* Disable echo processing */
  89     #define SPC_NOECHO 1
  90 #endif
  91
  92 #ifdef CPU_ARM
  93
  94 #if CONFIG_CPU != PP5002
  95     #undef  ICODE_ATTR
  96     #define ICODE_ATTR
  97
  98     #undef  IDATA_ATTR
  99     #define IDATA_ATTR
 100
 101     #undef  ICONST_ATTR
 102     #define ICONST_ATTR
 103
 104     #undef  IBSS_ATTR
 105     #define IBSS_ATTR
 106 #endif
 107
 108 #if SPC_DUAL_CORE
 109     #undef SHAREDBSS_ATTR
 110     #define SHAREDBSS_ATTR __attribute__ ((section(".ibss")))
 111     #undef SHAREDDATA_ATTR
 112     #define SHAREDDATA_ATTR __attribute__((section(".idata")))
 113 #endif
 114 #endif
 115
 116 /* Samples per channel per iteration */
 117 #if defined(CPU_PP) && NUM_CORES == 1
 118 #define WAV_CHUNK_SIZE 2048
 119 #else
 120 #define WAV_CHUNK_SIZE 1024
 121 #endif
 122
 123 /**************** Little-endian handling ****************/
 124
 125 static inline unsigned get_le16( void const* p )
 126 {
 127     return  ((unsigned char const*) p) [1] * 0x100u +
 128             ((unsigned char const*) p) [0];
 129 }
 130
 131 static inline int get_le16s( void const* p )
 132 {
 133     return  ((signed char const*) p) [1] * 0x100 +
 134             ((unsigned char const*) p) [0];
 135 }
 136
 137 static inline void set_le16( void* p, unsigned n )
 138 {
 139     ((unsigned char*) p) [1] = (unsigned char) (n >> 8);
 140     ((unsigned char*) p) [0] = (unsigned char) n;
 141 }
 142
 143 #define GET_LE16( addr )        get_le16( addr )
 144 #define GET_LE16A( addr )       get_le16( addr )
 145 #define SET_LE16( addr, data )  set_le16( addr, data )
 146 #define INT16A( addr ) (*(uint16_t*) (addr))
 147 #define INT16SA( addr ) (*(int16_t*) (addr))
 148
 149 #ifdef ROCKBOX_LITTLE_ENDIAN
 150     #define GET_LE16SA( addr )      (*( int16_t*) (addr))
 151     #define SET_LE16A( addr, data ) (void) (*(uint16_t*) (addr) = (data))
 152 #else
 153     #define GET_LE16SA( addr )      get_le16s( addr )
 154     #define SET_LE16A( addr, data ) set_le16 ( addr, data )
 155 #endif
 156
 157 struct Spc_Emu;
 158 #define THIS struct Spc_Emu* const this
 159
 160 /* The CPU portion (shock!) */
 161
 162 struct cpu_regs_t
 163 {
 164     long pc; /* more than 16 bits to allow overflow detection */
 165     uint8_t a;
 166     uint8_t x;
 167     uint8_t y;
 168     uint8_t status;
 169     uint8_t sp;
 170 };
 171
 172 struct src_dir
 173 {
 174     uint16_t start;
 175     uint16_t loop;
 176 };
 177
 178 struct cpu_ram_t
 179 {
 180     union {
 181         uint8_t padding1 [0x100];
 182         uint16_t align;
 183     } padding1 [1];
 184     union {
 185         uint8_t ram       [0x10000];
 186         struct src_dir sd [0x10000/sizeof(struct src_dir)];
 187     };
 188     uint8_t padding2 [0x100];
 189 };
 190
 191 #undef RAM
 192 #define RAM ram.ram
 193 extern struct cpu_ram_t ram;
 194
 195 long CPU_run( THIS, long start_time ) ICODE_ATTR;
 196 void CPU_Init( THIS );
 197
 198 /* The DSP portion (awe!) */
 199 enum { VOICE_COUNT = 8 };
 200 enum { REGISTER_COUNT = 128 };
 201
 202 struct raw_voice_t
 203 {
 204     int8_t  volume [2];
 205     uint8_t rate [2];
 206     uint8_t waveform;
 207     uint8_t adsr [2];   /* envelope rates for attack, decay, and sustain */
 208     uint8_t gain;       /* envelope gain (if not using ADSR) */
 209     int8_t  envx;       /* current envelope level */
 210     int8_t  outx;       /* current sample */
 211     int8_t  unused [6];
 212 };
 213
 214 struct globals_t
 215 {
 216     int8_t  unused1 [12];
 217     int8_t  volume_0;         /* 0C   Main Volume Left (-.7) */
 218     int8_t  echo_feedback;    /* 0D   Echo Feedback (-.7) */
 219     int8_t  unused2 [14];
 220     int8_t  volume_1;         /* 1C   Main Volume Right (-.7) */
 221     int8_t  unused3 [15];
 222     int8_t  echo_volume_0;    /* 2C   Echo Volume Left (-.7) */
 223     uint8_t pitch_mods;       /* 2D   Pitch Modulation on/off for each voice */
 224     int8_t  unused4 [14];
 225     int8_t  echo_volume_1;    /* 3C   Echo Volume Right (-.7) */
 226     uint8_t noise_enables;    /* 3D   Noise output on/off for each voice */
 227     int8_t  unused5 [14];
 228     uint8_t key_ons;          /* 4C   Key On for each voice */
 229     uint8_t echo_ons;         /* 4D   Echo on/off for each voice */
 230     int8_t  unused6 [14];
 231     uint8_t key_offs;         /* 5C   key off for each voice
 232                                       (instantiates release mode) */
 233     uint8_t wave_page;        /* 5D   source directory (wave table offsets) */
 234     int8_t  unused7 [14];
 235     uint8_t flags;            /* 6C   flags and noise freq */
 236     uint8_t echo_page;        /* 6D */
 237     int8_t  unused8 [14];
 238     uint8_t wave_ended;       /* 7C */
 239     uint8_t echo_delay;       /* 7D   ms >> 4 */
 240     char    unused9 [2];
 241 };
 242
 243 enum state_t
 244 {  /* -1, 0, +1 allows more efficient if statements */
 245     state_decay   = -1,
 246     state_sustain = 0,
 247     state_attack  = +1,
 248     state_release = 2
 249 };
 250
 251 struct cache_entry_t
 252 {
 253     int16_t const* samples;
 254     unsigned end; /* past-the-end position */
 255     unsigned loop; /* number of samples in loop */
 256     unsigned start_addr;
 257 };
 258
 259 enum { BRR_BLOCK_SIZE = 16 };
 260 enum { BRR_CACHE_SIZE = 0x20000 + 32} ;
 261
 262 struct voice_t
 263 {
 264 #if SPC_BRRCACHE
 265     int16_t const* samples;
 266     long wave_end;
 267     int wave_loop;
 268 #else
 269     int16_t samples [3 + BRR_BLOCK_SIZE + 1];
 270     int block_header; /* header byte from current block */
 271 #endif
 272     uint8_t const* addr;
 273     short volume [2];
 274     long position;/* position in samples buffer, with 12-bit fraction */
 275     short envx;
 276     short env_mode;
 277     short env_timer;
 278     short key_on_delay;
 279 };
 280
 281 #if SPC_BRRCACHE
 282 /* a little extra for samples that go past end */
 283 extern int16_t BRRcache [BRR_CACHE_SIZE];
 284 #endif
 285
 286 enum { FIR_BUF_HALF = 8 };
 287
 288 #if defined(CPU_COLDFIRE)
 289 /* global because of the large aligment requirement for hardware masking -
 290  * L-R interleaved 16-bit samples for easy loading and mac.w use.
 291  */
 292 enum
 293 {
 294     FIR_BUF_CNT   = FIR_BUF_HALF,
 295     FIR_BUF_SIZE  = FIR_BUF_CNT * sizeof ( int32_t ),
 296     FIR_BUF_ALIGN = FIR_BUF_SIZE * 2,
 297     FIR_BUF_MASK  = ~((FIR_BUF_ALIGN / 2) | (sizeof ( int32_t ) - 1))
 298 };
 299 #elif defined (CPU_ARM)
 300 #if ARM_ARCH >= 6
 301 enum
 302 {
 303     FIR_BUF_CNT   = FIR_BUF_HALF * 2,
 304     FIR_BUF_SIZE  = FIR_BUF_CNT * sizeof ( int32_t ),
 305     FIR_BUF_ALIGN = FIR_BUF_SIZE,
 306     FIR_BUF_MASK  = ~((FIR_BUF_ALIGN / 2) | (sizeof ( int32_t ) - 1))
 307 };
 308 #else
 309 enum
 310 {
 311     FIR_BUF_CNT   = FIR_BUF_HALF * 2 * 2,
 312     FIR_BUF_SIZE  = FIR_BUF_CNT * sizeof ( int32_t ),
 313     FIR_BUF_ALIGN = FIR_BUF_SIZE,
 314     FIR_BUF_MASK  = ~((FIR_BUF_ALIGN / 2) | (sizeof ( int32_t ) * 2 - 1))
 315 };
 316 #endif /* ARM_ARCH */
 317 #endif /* CPU_* */
 318
 319 struct Spc_Dsp
 320 {
 321     union
 322     {
 323         struct raw_voice_t voice [VOICE_COUNT];
 324         uint8_t reg [REGISTER_COUNT];
 325         struct globals_t g;
 326         int16_t align;
 327     } r;
 328
 329     unsigned echo_pos;
 330     int keys_down;
 331     int noise_count;
 332     uint16_t noise; /* also read as int16_t */
 333
 334 #if defined(CPU_COLDFIRE)
 335     /* FIR history is interleaved. Hardware handles wrapping by mask.
 336      * |LR|LR|LR|LR|LR|LR|LR|LR| */
 337     int32_t *fir_ptr;
 338     /* wrapped address just behind current position -
 339        allows mac.w to increment and mask fir_ptr */
 340     int32_t *last_fir_ptr;
 341     /* copy of echo FIR constants as int16_t for use with mac.w */
 342     int16_t fir_coeff [VOICE_COUNT];
 343 #elif defined (CPU_ARM)
 344    /* fir_buf [i + 8] == fir_buf [i], to avoid wrap checking in FIR code */
 345     int32_t *fir_ptr;
 346 #if ARM_ARCH >= 6
 347     /* FIR history is interleaved with guard to eliminate wrap checking
 348      * when convolving.
 349      * |LR|LR|LR|LR|LR|LR|LR|LR|--|--|--|--|--|--|--|--| */
 350     /* copy of echo FIR constants as int16_t, loaded as int32 for
 351      * halfword, packed multiples */
 352     int16_t fir_coeff [VOICE_COUNT];
 353 #else
 354     /* FIR history is interleaved with guard to eliminate wrap checking
 355      * when convolving.
 356      * |LL|RR|LL|RR|LL|RR|LL|RR|LL|RR|LL|RR|LL|RR|LL|RR|...
 357      * |--|--|--|--|--|--|--|--|--|--|--|--|--|--|--|--| */
 358     /* copy of echo FIR constants as int32_t, for faster access */
 359     int32_t fir_coeff [VOICE_COUNT];
 360 #endif /* ARM_ARCH */
 361 #else /* Unoptimized CPU */
 362     /* fir_buf [i + 8] == fir_buf [i], to avoid wrap checking in FIR code */
 363     int fir_pos; /* (0 to 7) */
 364     int fir_buf [FIR_BUF_HALF * 2] [2];
 365     /* copy of echo FIR constants as int, for faster access */
 366     int fir_coeff [VOICE_COUNT];
 367 #endif
 368
 369     struct voice_t voice_state [VOICE_COUNT];
 370
 371 #if SPC_BRRCACHE
 372     uint8_t oldsize;
 373     struct cache_entry_t wave_entry     [256];
 374     struct cache_entry_t wave_entry_old [256];
 375 #endif
 376 };
 377
 378 void DSP_run_( struct Spc_Dsp* this, long count, int32_t* out_buf ) ICODE_ATTR;
 379 void DSP_reset( struct Spc_Dsp* this );
 380
 381 static inline void DSP_run( struct Spc_Dsp* this, long count, int32_t* out )
 382 {
 383     /* Should we just fill the buffer with silence? Flags won't be cleared */
 384     /* during this run so it seems it should keep resetting every sample. */
 385     if ( this->r.g.flags & 0x80 )
 386         DSP_reset( this );
 387
 388     DSP_run_( this, count, out );
 389 }
 390
 391 /**************** SPC emulator ****************/
 392 /* 1.024 MHz clock / 32000 samples per second */
 393 enum { CLOCKS_PER_SAMPLE = 32 };
 394
 395 enum { EXTRA_CLOCKS = CLOCKS_PER_SAMPLE / 2 };
 396
 397 /* using this disables timer (since this will always be in the future) */
 398 enum { TIMER_DISABLED_TIME = 127 };
 399
 400 enum { ROM_SIZE = 64 };
 401 enum { ROM_ADDR = 0xFFC0 };
 402
 403 enum { TIMER_COUNT = 3 };
 404
 405 struct Timer
 406 {
 407     long next_tick;
 408     int period;
 409     int count;
 410     int shift;
 411     int enabled;
 412     int counter;
 413 };
 414
 415 void Timer_run_( struct Timer* t, long time ) ICODE_ATTR;
 416
 417 static inline void Timer_run( struct Timer* t, long time )
 418 {
 419     if ( time >= t->next_tick )
 420         Timer_run_( t, time );
 421 }
 422
 423 struct Spc_Emu
 424 {
 425     uint8_t cycle_table [0x100];
 426     struct cpu_regs_t r;
 427
 428     int32_t* sample_buf;
 429     long next_dsp;
 430     int rom_enabled;
 431     int extra_cycles;
 432
 433     struct Timer timer [TIMER_COUNT];
 434
 435     /* large objects at end */
 436     struct Spc_Dsp dsp;
 437     uint8_t extra_ram [ROM_SIZE];
 438     uint8_t boot_rom  [ROM_SIZE];
 439 };
 440
 441 enum { SPC_FILE_SIZE = 0x10180 };
 442
 443 struct spc_file_t
 444 {
 445     char    signature [27];
 446     char    unused [10];
 447     uint8_t pc [2];
 448     uint8_t a;
 449     uint8_t x;
 450     uint8_t y;
 451     uint8_t status;
 452     uint8_t sp;
 453     char    unused2 [212];
 454     uint8_t ram [0x10000];
 455     uint8_t dsp [128];
 456     uint8_t ipl_rom [128];
 457 };
 458
 459 void SPC_Init( THIS );
 460
 461 int SPC_load_spc( THIS, const void* data, long size );
 462
 463 /**************** DSP interaction ****************/
 464 void DSP_write( struct Spc_Dsp* this, int i, int data ) ICODE_ATTR;
 465
 466 static inline int DSP_read( struct Spc_Dsp* this, int i )
 467 {
 468     assert( (unsigned) i < REGISTER_COUNT );
 469     return this->r.reg [i];
 470 }
 471
 472 void SPC_run_dsp_( THIS, long time ) ICODE_ATTR;
 473
 474 static inline void SPC_run_dsp( THIS, long time )
 475 {
 476     if ( time >= this->next_dsp )
 477         SPC_run_dsp_( this, time );
 478 }
 479
 480 int SPC_read( THIS, unsigned addr, long const time ) ICODE_ATTR;
 481 void SPC_write( THIS, unsigned addr, int data, long const time ) ICODE_ATTR;
 482
 483 /**************** Sample generation ****************/
 484 int SPC_play( THIS, long count, int32_t* out ) ICODE_ATTR;
 485
 486 #endif /* _SPC_CODEC_H_ */