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[kdeedu.git] / kstars / kstars / indi / apogee / ApnCamera.cpp
blob4e8c1b00bf2d33db26bcf9a9afd260790ddfef75
1 // ApnCamera.cpp: implementation of the CApnCamera class.
2 //
3 // Copyright (c) 2003, 2004 Apogee Instruments, Inc.
4 //////////////////////////////////////////////////////////////////////
5
6 #include "stdafx.h"
7
8 #include "ApnCamera.h"
9 #include "ApnCamTable.h"
10
11
12 //////////////////////////////////////////////////////////////////////
13 // Construction/Destruction
14 //////////////////////////////////////////////////////////////////////
15
16 CApnCamera::CApnCamera()
17 {
18 m_ApnSensorInfo = NULL;
19 }
20
21 CApnCamera::~CApnCamera()
22 {
23 if ( m_ApnSensorInfo != NULL )
24 {
25 delete m_ApnSensorInfo;
26 m_ApnSensorInfo = NULL;
27 }
28 CloseDriver();
29 }
30
31 bool CApnCamera::Expose( double Duration, bool Light )
32 {
33 ULONG ExpTime;
34 unsigned short BitsPerPixel(0);
35 unsigned short UnbinnedRoiX;
36 unsigned short UnbinnedRoiY;
37 unsigned short PreRoiSkip, PostRoiSkip;
38 unsigned short PreRoiRows, PostRoiRows;
39 unsigned short PreRoiVBinning, PostRoiVBinning;
40
41 unsigned short RoiRegBuffer[12];
42 unsigned short RoiRegData[12];
43
44 unsigned short TotalHPixels;
45 unsigned short TotalVPixels;
46
47
48 while ( read_ImagingStatus() != Apn_Status_Flushing )
49 {
50 Sleep( 20 );
51 }
52
53 // Validate the "Duration" parameter
54 if ( Duration < APN_EXPOSURE_TIME_MIN )
55 Duration = APN_EXPOSURE_TIME_MIN;
56
57 // Validate the ROI params
58 UnbinnedRoiX = m_RoiPixelsH * m_RoiBinningH;
59
60 PreRoiSkip = m_RoiStartX;
61
62 PostRoiSkip = m_ApnSensorInfo->m_TotalColumns -
63 m_ApnSensorInfo->m_ClampColumns -
64 PreRoiSkip -
65 UnbinnedRoiX;
66
67 TotalHPixels = UnbinnedRoiX + PreRoiSkip + PostRoiSkip + m_ApnSensorInfo->m_ClampColumns;
68
69 if ( TotalHPixels != m_ApnSensorInfo->m_TotalColumns )
70 return false;
71
72 UnbinnedRoiY = m_RoiPixelsV * m_RoiBinningV;
73
74 PreRoiRows = m_ApnSensorInfo->m_UnderscanRows +
75 m_RoiStartY;
76
77 PostRoiRows = m_ApnSensorInfo->m_TotalRows -
78 PreRoiRows -
79 UnbinnedRoiY;
80
81 TotalVPixels = UnbinnedRoiY + PreRoiRows + PostRoiRows;
82
83 if ( TotalVPixels != m_ApnSensorInfo->m_TotalRows )
84 return false;
85
86 // Calculate the exposure time to program to the camera
87 ExpTime = ((unsigned long)(Duration / APN_TIMER_RESOLUTION)) + APN_TIMER_OFFSET_COUNT;
88
89 Write( FPGA_REG_TIMER_LOWER, (unsigned short)(ExpTime & 0xFFFF));
90 ExpTime = ExpTime >> 16;
91 Write( FPGA_REG_TIMER_UPPER, (unsigned short)(ExpTime & 0xFFFF));
92
93 m_pvtExposurePixelsV = m_RoiPixelsV;
94 m_pvtExposurePixelsH = m_RoiPixelsH;
95
96 if ( m_DataBits == Apn_Resolution_SixteenBit )
97 {
98 BitsPerPixel = 16;
99 }
100 else if ( m_DataBits == Apn_Resolution_TwelveBit )
101 {
102 BitsPerPixel = 12;
103 }
104
105 if ( PreStartExpose( BitsPerPixel ) != 0 )
106 {
107 return false;
108 }
109
110 // Calculate the vertical parameters
111 PreRoiVBinning = m_ApnSensorInfo->m_RowOffsetBinning;
112
113 PostRoiVBinning = 1;
114
115 // For interline CCDs, set "Fast Dump" mode if the particular array is NOT digitized
116 if ( m_ApnSensorInfo->m_InterlineCCD )
117 {
118 // use the fast dump feature to get rid of the data quickly.
119 // one row, binning to the original row count
120 // note that we only are not digitized in arrays 1 and 3
121 PreRoiVBinning = PreRoiRows;
122 PostRoiVBinning = PostRoiRows;
123
124 PreRoiVBinning |= FPGA_BIT_ARRAY_FASTDUMP;
125 PostRoiVBinning |= FPGA_BIT_ARRAY_FASTDUMP;
126
127 PreRoiRows = 1;
128 PostRoiRows = 1;
129 }
130
131 // Set up the geometry for a full frame device
132 if ( m_ApnSensorInfo->m_EnableSingleRowOffset )
133 {
134 PreRoiVBinning += PreRoiRows;
135 PostRoiVBinning = PostRoiRows;
136
137 PreRoiVBinning |= FPGA_BIT_ARRAY_FASTDUMP;
138 PostRoiVBinning |= FPGA_BIT_ARRAY_FASTDUMP;
139
140 PreRoiRows = 1;
141 PostRoiRows = 1;
142 }
143
144
145 // Issue the reset
146 RoiRegBuffer[0] = FPGA_REG_COMMAND_B;
147 RoiRegData[0] = FPGA_BIT_CMD_RESET;
148
149 // Program the horizontal settings
150 RoiRegBuffer[1] = FPGA_REG_PREROI_SKIP_COUNT;
151 RoiRegData[1] = PreRoiSkip;
152
153 RoiRegBuffer[2] = FPGA_REG_ROI_COUNT;
154 // Number of ROI pixels. Adjust the 12bit operation here to account for an extra
155 // 10 pixel shift as a result of the A/D conversion.
156 if ( m_DataBits == Apn_Resolution_SixteenBit )
157 {
158 RoiRegData[2] = m_pvtExposurePixelsH + 1;
159 }
160 else if ( m_DataBits == Apn_Resolution_TwelveBit )
161 {
162 RoiRegData[2] = m_pvtExposurePixelsH + 10;
163 }
164
165 RoiRegBuffer[3] = FPGA_REG_POSTROI_SKIP_COUNT;
166 RoiRegData[3] = PostRoiSkip;
167
168 // Program the vertical settings
169 RoiRegBuffer[4] = FPGA_REG_A1_ROW_COUNT;
170 RoiRegData[4] = PreRoiRows;
171 RoiRegBuffer[5] = FPGA_REG_A1_VBINNING;
172 RoiRegData[5] = PreRoiVBinning;
173
174 RoiRegBuffer[6] = FPGA_REG_A2_ROW_COUNT;
175 RoiRegData[6] = m_RoiPixelsV;
176 RoiRegBuffer[7] = FPGA_REG_A2_VBINNING;
177 RoiRegData[7] = (m_RoiBinningV | FPGA_BIT_ARRAY_DIGITIZE);
178
179 RoiRegBuffer[8] = FPGA_REG_A3_ROW_COUNT;
180 RoiRegData[8] = PostRoiRows;
181 RoiRegBuffer[9] = FPGA_REG_A3_VBINNING;
182 RoiRegData[9] = PostRoiVBinning;
183
184 // Issue the reset
185 RoiRegBuffer[10] = FPGA_REG_COMMAND_B;
186 RoiRegData[10] = FPGA_BIT_CMD_RESET;
187
188 switch ( m_pvtCameraMode )
189 {
190 case Apn_CameraMode_Normal:
191 if ( Light )
192 {
193 RoiRegBuffer[11] = FPGA_REG_COMMAND_A;
194 RoiRegData[11] = FPGA_BIT_CMD_EXPOSE;
195 }
196 else
197 {
198 RoiRegBuffer[11] = FPGA_REG_COMMAND_A;
199 RoiRegData[11] = FPGA_BIT_CMD_DARK;
200 }
201 break;
202 case Apn_CameraMode_TDI:
203 RoiRegBuffer[11] = FPGA_REG_COMMAND_A;
204 RoiRegData[11] = FPGA_BIT_CMD_TDI;
205 break;
206 case Apn_CameraMode_Test:
207 if ( Light )
208 {
209 RoiRegBuffer[11] = FPGA_REG_COMMAND_A;
210 RoiRegData[11] = FPGA_BIT_CMD_EXPOSE;
211 }
212 else
213 {
214 RoiRegBuffer[11] = FPGA_REG_COMMAND_A;
215 RoiRegData[11] = FPGA_BIT_CMD_DARK;
216 }
217 break;
218 case Apn_CameraMode_ExternalTrigger:
219 RoiRegBuffer[11] = FPGA_REG_COMMAND_A;
220 RoiRegData[11] = FPGA_BIT_CMD_TRIGGER_EXPOSE;
221 break;
222 case Apn_CameraMode_ExternalShutter:
223 break;
224 }
225
226 // Send the instruction sequence to the camera
227 WriteMultiMRMD( RoiRegBuffer, RoiRegData, 12 );
228
229 m_pvtImageInProgress = true;
230 m_pvtImageReady = false;
231
232 return true;
233 }
234
235 bool CApnCamera::ResetSystem()
236 {
237 // Reset the camera engine
238 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
239
240 // Start flushing
241 Write( FPGA_REG_COMMAND_A, FPGA_BIT_CMD_FLUSH );
242
243 return true;
244 }
245
246 bool CApnCamera::PauseTimer( bool PauseState )
247 {
248 unsigned short RegVal;
249 bool CurrentState;
250
251 Read( FPGA_REG_OP_A, RegVal );
252
253 CurrentState = ( RegVal & FPGA_BIT_PAUSE_TIMER ) == FPGA_BIT_PAUSE_TIMER;
254
255 if ( CurrentState != PauseState )
256 {
257 if ( PauseState )
258 {
259 RegVal |= FPGA_BIT_PAUSE_TIMER;
260 }
261 else
262 {
263 RegVal &= ~FPGA_BIT_PAUSE_TIMER;
264 }
265 Write ( FPGA_REG_OP_A, RegVal );
266 }
267
268 return true;
269 }
270
271 bool CApnCamera::StopExposure( bool DigitizeData )
272 {
273 if ( m_pvtImageInProgress )
274 {
275 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_END_EXPOSURE );
276
277 if ( PostStopExposure( DigitizeData ) != 0 )
278 {
279 return false;
280 }
281 }
282
283 return true;
284 }
285
286
287 unsigned short CApnCamera::GetExposurePixelsH()
288 {
289 return m_pvtExposurePixelsH;
290 }
291
292 unsigned short CApnCamera::GetExposurePixelsV()
293 {
294 return m_pvtExposurePixelsV;
295 }
296
297 double CApnCamera::read_InputVoltage()
298 {
299 UpdateGeneralStatus();
300
301 return m_pvtInputVoltage;
302 }
303
304 long CApnCamera::read_AvailableMemory()
305 {
306 long AvailableMemory(0);
307
308 switch( m_CameraInterface )
309 {
310 case Apn_Interface_NET:
311 AvailableMemory = 28 * 1024;
312 break;
313 case Apn_Interface_USB:
314 AvailableMemory = 32 * 1024;
315 break;
316 default:
317 break;
318 }
319
320 return AvailableMemory;
321 }
322
323 unsigned short CApnCamera::read_FirmwareVersion()
324 {
325 unsigned short FirmwareVersion;
326 Read( FPGA_REG_FIRMWARE_REV, FirmwareVersion );
327 return FirmwareVersion;
328 }
329
330 bool CApnCamera::read_ShutterState()
331 {
332 UpdateGeneralStatus();
333
334 return m_pvtShutterState;
335 }
336
337 bool CApnCamera::read_DisableShutter()
338 {
339 unsigned short RegVal;
340 Read( FPGA_REG_OP_A, RegVal );
341 return ( (RegVal & FPGA_BIT_DISABLE_SHUTTER) != 0 );
342 }
343
344 void CApnCamera::write_DisableShutter( bool DisableShutter )
345 {
346 unsigned short RegVal;
347 Read( FPGA_REG_OP_A, RegVal );
348
349 if ( DisableShutter )
350 RegVal |= FPGA_BIT_DISABLE_SHUTTER;
351 else
352 RegVal &= ~FPGA_BIT_DISABLE_SHUTTER;
353
354 Write( FPGA_REG_OP_A, RegVal );
355 }
356
357 bool CApnCamera::read_ForceShutterOpen()
358 {
359 unsigned short RegVal;
360 Read( FPGA_REG_OP_A, RegVal );
361 return ( (RegVal & FPGA_BIT_FORCE_SHUTTER) != 0 );
362 }
363
364 void CApnCamera::write_ForceShutterOpen( bool ForceShutterOpen )
365 {
366 unsigned short RegVal;
367 Read( FPGA_REG_OP_A, RegVal );
368
369 if ( ForceShutterOpen )
370 RegVal |= FPGA_BIT_FORCE_SHUTTER;
371 else
372 RegVal &= ~FPGA_BIT_FORCE_SHUTTER;
373
374 Write( FPGA_REG_OP_A, RegVal );
375 }
376
377 bool CApnCamera::read_ShutterAmpControl()
378 {
379 unsigned short RegVal;
380 Read( FPGA_REG_OP_A, RegVal );
381 return ( (RegVal & FPGA_BIT_SHUTTER_AMP_CONTROL ) != 0 );
382 }
383
384 void CApnCamera::write_ShutterAmpControl( bool ShutterAmpControl )
385 {
386 unsigned short RegVal;
387 Read( FPGA_REG_OP_A, RegVal );
388
389 if ( ShutterAmpControl )
390 RegVal |= FPGA_BIT_SHUTTER_AMP_CONTROL;
391 else
392 RegVal &= ~FPGA_BIT_SHUTTER_AMP_CONTROL;
393
394 Write( FPGA_REG_OP_A, RegVal );
395 }
396
397 bool CApnCamera::read_ExternalIoReadout()
398 {
399 unsigned short RegVal;
400 Read( FPGA_REG_OP_A, RegVal );
401 return ( (RegVal & FPGA_BIT_SHUTTER_MODE) != 0 );
402 }
403
404 void CApnCamera::write_ExternalIoReadout( bool ExternalIoReadout )
405 {
406 unsigned short RegVal;
407 Read( FPGA_REG_OP_A, RegVal );
408
409 if ( ExternalIoReadout )
410 RegVal |= FPGA_BIT_SHUTTER_MODE;
411 else
412 RegVal &= ~FPGA_BIT_SHUTTER_MODE;
413
414 Write( FPGA_REG_OP_A, RegVal );
415 }
416
417 bool CApnCamera::read_FastSequence()
418 {
419 if ( m_ApnSensorInfo->m_InterlineCCD == false )
420 return false;
421
422 unsigned short RegVal;
423 Read( FPGA_REG_OP_A, RegVal );
424 return ( (RegVal & FPGA_BIT_RATIO) != 0 );
425 }
426
427 void CApnCamera::write_FastSequence( bool FastSequence )
428 {
429 if ( m_ApnSensorInfo->m_InterlineCCD == false )
430 return;
431
432 unsigned short RegVal;
433 Read( FPGA_REG_OP_A, RegVal );
434
435 if ( FastSequence )
436 {
437 RegVal |= FPGA_BIT_RATIO;
438 Write( FPGA_REG_SHUTTER_CLOSE_DELAY, 0x0 );
439 }
440 else
441 {
442 RegVal &= ~FPGA_BIT_RATIO;
443 }
444
445 Write( FPGA_REG_OP_A, RegVal );
446 }
447
448 Apn_NetworkMode CApnCamera::read_NetworkTransferMode()
449 {
450 return m_pvtNetworkTransferMode;
451 }
452
453 void CApnCamera::write_NetworkTransferMode( Apn_NetworkMode TransferMode )
454 {
455 SetNetworkTransferMode( TransferMode );
456
457 m_pvtNetworkTransferMode = TransferMode;
458 }
459
460 Apn_CameraMode CApnCamera::read_CameraMode()
461 {
462 return m_pvtCameraMode;
463 }
464
465 void CApnCamera::write_CameraMode( Apn_CameraMode CameraMode )
466 {
467 unsigned short RegVal;
468
469
470 // If our state isn't going to change, do nothing
471 if ( m_pvtCameraMode == CameraMode )
472 return;
473
474 // If we didn't return already, then if we know our state is going to
475 // change. If we're in test mode, clear the appropriate FPGA bit(s).
476 switch( m_pvtCameraMode )
477 {
478 case Apn_CameraMode_Normal:
479 break;
480 case Apn_CameraMode_TDI:
481 break;
482 case Apn_CameraMode_Test:
483 Read( FPGA_REG_OP_B, RegVal );
484 RegVal &= ~FPGA_BIT_AD_SIMULATION;
485 Write( FPGA_REG_OP_B, RegVal );
486 break;
487 case Apn_CameraMode_ExternalTrigger:
488 break;
489 case Apn_CameraMode_ExternalShutter:
490 Read( FPGA_REG_OP_A, RegVal );
491 RegVal &= ~FPGA_BIT_SHUTTER_SOURCE;
492 Write( FPGA_REG_OP_A, RegVal );
493 break;
494 }
495
496 switch ( CameraMode )
497 {
498 case Apn_CameraMode_Normal:
499 break;
500 case Apn_CameraMode_TDI:
501 break;
502 case Apn_CameraMode_Test:
503 Read( FPGA_REG_OP_B, RegVal );
504 RegVal |= FPGA_BIT_AD_SIMULATION;
505 Write( FPGA_REG_OP_B, RegVal );
506 break;
507 case Apn_CameraMode_ExternalTrigger:
508 Read( FPGA_REG_IO_PORT_ASSIGNMENT, RegVal );
509 RegVal |= 0x01;
510 Write( FPGA_REG_IO_PORT_ASSIGNMENT, RegVal );
511 break;
512 case Apn_CameraMode_ExternalShutter:
513 Read( FPGA_REG_OP_A, RegVal );
514 RegVal |= FPGA_BIT_SHUTTER_SOURCE;
515 Write( FPGA_REG_OP_A, RegVal );
516 break;
517 }
518
519 m_pvtCameraMode = CameraMode;
520 }
521
522 void CApnCamera::write_DataBits( Apn_Resolution BitResolution )
523 {
524 unsigned short RegVal;
525
526 if ( m_CameraInterface == Apn_Interface_NET )
527 {
528 // The network interface is 16bpp only. Changing the resolution
529 // for network cameras has no effect.
530 return;
531 }
532
533 if ( m_DataBits != BitResolution )
534 {
535 // Reset the camera
536 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
537
538 // Change bit setting after the reset
539 Read( FPGA_REG_OP_A, RegVal );
540
541 if ( BitResolution == Apn_Resolution_TwelveBit )
542 RegVal |= FPGA_BIT_DIGITIZATION_RES;
543
544 if ( BitResolution == Apn_Resolution_SixteenBit )
545 RegVal &= ~FPGA_BIT_DIGITIZATION_RES;
546
547 Write( FPGA_REG_OP_A, RegVal );
548
549 m_DataBits = BitResolution;
550
551 LoadClampPattern();
552 LoadSkipPattern();
553 LoadRoiPattern( m_RoiBinningH );
554
555 // Reset the camera
556 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
557 // Start flushing
558 Write( FPGA_REG_COMMAND_A, FPGA_BIT_CMD_FLUSH );
559 }
560 }
561
562 Apn_Status CApnCamera::read_ImagingStatus()
563 {
564 bool Exposing, Active, Done, Flushing, WaitOnTrigger;
565 bool DataHalted, RamError;
566
567
568 UpdateGeneralStatus();
569
570 // Update the ImagingStatus
571 Exposing = false;
572 Active = false;
573 Done = false;
574 Flushing = false;
575 WaitOnTrigger = false;
576 DataHalted = false;
577 RamError = false;
578
579 if ( (m_pvtStatusReg & FPGA_BIT_STATUS_IMAGING_ACTIVE) != 0 )
580 Active = true;
581
582 if ( (m_pvtStatusReg & FPGA_BIT_STATUS_IMAGE_EXPOSING) != 0 )
583 Exposing = true;
584
585 if ( (m_pvtStatusReg & FPGA_BIT_STATUS_IMAGE_DONE) != 0 )
586 Done = true;
587
588 if ( (m_pvtStatusReg & FPGA_BIT_STATUS_FLUSHING) != 0 )
589 Flushing = true;
590
591 if ( (m_pvtStatusReg & FPGA_BIT_STATUS_WAITING_TRIGGER) != 0 )
592 WaitOnTrigger = true;
593
594 if ( (m_pvtStatusReg & FPGA_BIT_STATUS_DATA_HALTED) != 0 )
595 DataHalted = true;
596
597 if ( (m_pvtStatusReg & FPGA_BIT_STATUS_PATTERN_ERROR) != 0 )
598 RamError = true;
599
600 if ( RamError )
601 {
602 m_pvtImagingStatus = Apn_Status_PatternError;
603 }
604 else
605 {
606 if ( DataHalted )
607 {
608 m_pvtImagingStatus = Apn_Status_DataError;
609 }
610 else
611 {
612 if ( WaitOnTrigger )
613 {
614 m_pvtImagingStatus = Apn_Status_WaitingOnTrigger;
615 }
616 else
617 {
618 if ( Done && m_pvtImageInProgress )
619 {
620 m_pvtImageReady = true;
621 m_pvtImagingStatus = Apn_Status_ImageReady;
622 }
623 else
624 {
625 if ( Active )
626 {
627 if ( Exposing )
628 m_pvtImagingStatus = Apn_Status_Exposing;
629 else
630 m_pvtImagingStatus = Apn_Status_ImagingActive;
631 }
632 else
633 {
634 if ( Flushing )
635 m_pvtImagingStatus = Apn_Status_Flushing;
636 else
637 m_pvtImagingStatus = Apn_Status_Idle;
638 }
639 }
640 }
641 }
642 }
643
644 /*
645 switch( m_pvtImagingStatus )
646 {
647 case Apn_Status_DataError:
648 OutputDebugString( "ImagingStatus: Apn_Status_DataError" );
649 break;
650 case Apn_Status_PatternError:
651 OutputDebugString( "ImagingStatus: Apn_Status_PatternError" );
652 break;
653 case Apn_Status_Idle:
654 OutputDebugString( "ImagingStatus: Apn_Status_Idle" );
655 break;
656 case Apn_Status_Exposing:
657 OutputDebugString( "ImagingStatus: Apn_Status_Exposing" );
658 break;
659 case Apn_Status_ImagingActive:
660 OutputDebugString( "ImagingStatus: Apn_Status_ImagingActive" );
661 break;
662 case Apn_Status_ImageReady:
663 OutputDebugString( "ImagingStatus: Apn_Status_ImageReady" );
664 break;
665 case Apn_Status_Flushing:
666 OutputDebugString( "ImagingStatus: Apn_Status_Flushing" );
667 break;
668 case Apn_Status_WaitingOnTrigger:
669 OutputDebugString( "ImagingStatus: Apn_Status_WaitingOnTrigger" );
670 break;
671 default:
672 OutputDebugString( "ImagingStatus: UNDEFINED!!" );
673 break;
674 }
675 */
676
677 return m_pvtImagingStatus;
678 }
679
680 Apn_LedMode CApnCamera::read_LedMode()
681 {
682 return m_pvtLedMode;
683 }
684
685 void CApnCamera::write_LedMode( Apn_LedMode LedMode )
686 {
687 unsigned short RegVal;
688
689 Read( FPGA_REG_OP_A, RegVal );
690
691 switch ( LedMode )
692 {
693 case Apn_LedMode_DisableAll:
694 RegVal |= FPGA_BIT_LED_DISABLE;
695 break;
696 case Apn_LedMode_DisableWhileExpose:
697 RegVal &= ~FPGA_BIT_LED_DISABLE;
698 RegVal |= FPGA_BIT_LED_EXPOSE_DISABLE;
699 break;
700 case Apn_LedMode_EnableAll:
701 RegVal &= ~FPGA_BIT_LED_DISABLE;
702 RegVal &= ~FPGA_BIT_LED_EXPOSE_DISABLE;
703 break;
704 }
705
706 m_pvtLedMode = LedMode;
707
708 Write( FPGA_REG_OP_A, RegVal );
709 }
710
711 Apn_LedState CApnCamera::read_LedState( unsigned short LedId )
712 {
713 Apn_LedState RetVal(0);
714
715 if ( LedId == 0 ) // LED A
716 RetVal = m_pvtLedStateA;
717
718 if ( LedId == 1 ) // LED B
719 RetVal = m_pvtLedStateB;
720
721 return RetVal;
722 }
723
724 void CApnCamera::write_LedState( unsigned short LedId, Apn_LedState LedState )
725 {
726 unsigned short RegVal;
727
728
729 RegVal = 0x0;
730
731 if ( LedId == 0 ) // LED A
732 {
733 RegVal = (m_pvtLedStateB << 4); // keep the current settings for LED B
734 RegVal |= LedState; // program new settings
735 m_pvtLedStateA = LedState;
736 }
737 else if ( LedId == 1 ) // LED B
738 {
739 RegVal = m_pvtLedStateA; // keep the current settings for LED A
740 RegVal |= (LedState << 4); // program new settings
741 m_pvtLedStateB = LedState;
742 }
743
744 Write( FPGA_REG_LED_SELECT, RegVal );
745 }
746
747 bool CApnCamera::read_CoolerEnable()
748 {
749 return m_pvtCoolerEnable;
750 }
751
752 void CApnCamera::write_CoolerEnable( bool CoolerEnable )
753 {
754 if ( CoolerEnable )
755 {
756 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RAMP_TO_SETPOINT );
757 }
758 else
759 {
760 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RAMP_TO_AMBIENT );
761 }
762
763 m_pvtCoolerEnable = CoolerEnable;
764 }
765
766 Apn_CoolerStatus CApnCamera::read_CoolerStatus()
767 {
768 bool CoolerAtTemp;
769 bool CoolerActive;
770 bool CoolerTempRevised;
771
772
773 UpdateGeneralStatus();
774
775 // Update CoolerStatus
776 CoolerActive = false;
777 CoolerAtTemp = false;
778 CoolerTempRevised = false;
779
780 if ( (m_pvtStatusReg & FPGA_BIT_STATUS_TEMP_AT_TEMP) != 0 )
781 CoolerAtTemp = true;
782
783 if ( (m_pvtStatusReg & FPGA_BIT_STATUS_TEMP_ACTIVE) != 0 )
784 CoolerActive = true;
785
786 if ( (m_pvtStatusReg & FPGA_BIT_STATUS_TEMP_REVISION) != 0 )
787 CoolerTempRevised = true;
788
789 // Now derive our cooler state
790 if ( !CoolerActive )
791 {
792 m_pvtCoolerStatus = Apn_CoolerStatus_Off;
793 }
794 else
795 {
796 if ( CoolerTempRevised )
797 {
798 m_pvtCoolerStatus = Apn_CoolerStatus_Revision;
799 }
800 else
801 {
802 if ( CoolerAtTemp )
803 m_pvtCoolerStatus = Apn_CoolerStatus_AtSetPoint;
804 else
805 m_pvtCoolerStatus = Apn_CoolerStatus_RampingToSetPoint;
806
807 }
808 }
809
810 return m_pvtCoolerStatus;
811 }
812
813 double CApnCamera::read_CoolerSetPoint()
814 {
815 unsigned short RegVal;
816 double TempVal;
817
818 Read( FPGA_REG_TEMP_DESIRED, RegVal );
819
820 RegVal &= 0x0FFF;
821
822 TempVal = ( RegVal - APN_TEMP_SETPOINT_ZERO_POINT ) * APN_TEMP_DEGREES_PER_BIT;
823
824 return TempVal;
825 }
826
827 void CApnCamera::write_CoolerSetPoint( double SetPoint )
828 {
829 unsigned short RegVal;
830 double TempVal;
831
832
833 TempVal = SetPoint;
834
835 if ( SetPoint < (APN_TEMP_SETPOINT_MIN - APN_TEMP_KELVIN_SCALE_OFFSET) )
836 TempVal = APN_TEMP_SETPOINT_MIN;
837
838 if ( SetPoint > (APN_TEMP_SETPOINT_MAX - APN_TEMP_KELVIN_SCALE_OFFSET) )
839 TempVal = APN_TEMP_SETPOINT_MAX;
840
841 RegVal = (unsigned short)( (TempVal / APN_TEMP_DEGREES_PER_BIT) + APN_TEMP_SETPOINT_ZERO_POINT );
842
843 Write( FPGA_REG_TEMP_DESIRED, RegVal );
844 }
845
846 double CApnCamera::read_CoolerBackoffPoint()
847 {
848 return ( m_pvtCoolerBackoffPoint );
849 }
850
851 void CApnCamera::write_CoolerBackoffPoint( double BackoffPoint )
852 {
853 unsigned short RegVal;
854 double TempVal;
855
856 TempVal = BackoffPoint;
857
858 // BackoffPoint must be a positive number!
859 if ( BackoffPoint < 0.0 )
860 TempVal = 0.0;
861
862 if ( BackoffPoint < (APN_TEMP_SETPOINT_MIN - APN_TEMP_KELVIN_SCALE_OFFSET) )
863 TempVal = APN_TEMP_SETPOINT_MIN;
864
865 if ( BackoffPoint > (APN_TEMP_SETPOINT_MAX - APN_TEMP_KELVIN_SCALE_OFFSET) )
866 TempVal = APN_TEMP_SETPOINT_MAX;
867
868 m_pvtCoolerBackoffPoint = TempVal;
869
870 RegVal = (unsigned short)( TempVal / APN_TEMP_DEGREES_PER_BIT );
871
872 Write( FPGA_REG_TEMP_BACKOFF, RegVal );
873 }
874
875 double CApnCamera::read_CoolerDrive()
876 {
877 UpdateGeneralStatus();
878
879 return m_pvtCoolerDrive;
880 }
881
882 double CApnCamera::read_TempCCD()
883 {
884 // UpdateGeneralStatus();
885
886 unsigned short TempReg;
887 unsigned short TempAvg;
888 unsigned long TempTotal;
889 int don;
890
891 TempTotal = 0;
892 don = 8;
893 if ( m_CameraInterface == Apn_Interface_NET ) {
894 don = 1;
895 }
896
897 for ( int i=0; i<don; i++ )
898 {
899 Read( FPGA_REG_TEMP_CCD, TempReg );
900 TempTotal += TempReg;
901 }
902
903 TempAvg = (unsigned short)(TempTotal / don);
904
905 m_pvtCurrentCcdTemp = ( (TempAvg - APN_TEMP_SETPOINT_ZERO_POINT)
906 * APN_TEMP_DEGREES_PER_BIT );
907
908 return m_pvtCurrentCcdTemp;
909 }
910
911 double CApnCamera::read_TempHeatsink()
912 {
913 // UpdateGeneralStatus();
914
915 unsigned short TempReg;
916 unsigned short TempAvg;
917 unsigned long TempTotal;
918 int don;
919
920 TempTotal = 0;
921 don = 8;
922 if ( m_CameraInterface == Apn_Interface_NET ) {
923 don = 1;
924 }
925
926 for ( int i=0; i<don; i++ )
927 {
928 Read( FPGA_REG_TEMP_HEATSINK, TempReg );
929 TempTotal += TempReg;
930 }
931
932 TempAvg = (unsigned short)(TempTotal / don);
933
934 m_pvtCurrentHeatsinkTemp = ( (TempAvg - APN_TEMP_HEATSINK_ZERO_POINT)
935 * APN_TEMP_DEGREES_PER_BIT );
936
937 return m_pvtCurrentHeatsinkTemp;
938 }
939
940 Apn_FanMode CApnCamera::read_FanMode()
941 {
942 return m_pvtFanMode;
943 }
944
945 void CApnCamera::write_FanMode( Apn_FanMode FanMode )
946 {
947 unsigned short RegVal;
948 unsigned short OpRegA;
949
950
951 if ( m_pvtFanMode == FanMode )
952 return;
953
954 if ( m_pvtCoolerEnable )
955 {
956 Read( FPGA_REG_OP_A, OpRegA );
957 OpRegA |= FPGA_BIT_TEMP_SUSPEND;
958 Write( FPGA_REG_OP_A, OpRegA );
959
960 do
961 {
962 Read( FPGA_REG_GENERAL_STATUS, RegVal );
963 } while ( (RegVal & FPGA_BIT_STATUS_TEMP_SUSPEND_ACK) == 0 );
964
965 }
966
967 switch ( FanMode )
968 {
969 case Apn_FanMode_Off:
970 RegVal = APN_FAN_SPEED_OFF;
971 break;
972 case Apn_FanMode_Low:
973 RegVal = APN_FAN_SPEED_LOW;
974 break;
975 case Apn_FanMode_Medium:
976 RegVal = APN_FAN_SPEED_MEDIUM;
977 break;
978 case Apn_FanMode_High:
979 RegVal = APN_FAN_SPEED_HIGH;
980 break;
981 }
982
983 Write( FPGA_REG_FAN_SPEED_CONTROL, RegVal );
984
985 Read( FPGA_REG_OP_B, RegVal );
986 RegVal |= FPGA_BIT_DAC_SELECT_ZERO;
987 RegVal &= ~FPGA_BIT_DAC_SELECT_ONE;
988 Write( FPGA_REG_OP_B, RegVal );
989
990 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_DAC_LOAD );
991
992 m_pvtFanMode = FanMode;
993
994 if ( m_pvtCoolerEnable )
995 {
996 OpRegA &= ~FPGA_BIT_TEMP_SUSPEND;
997 Write( FPGA_REG_OP_A, OpRegA );
998 }
999 }
1000
1001 double CApnCamera::read_ShutterStrobePosition()
1002 {
1003 return m_pvtShutterStrobePosition;
1004 }
1005
1006 void CApnCamera::write_ShutterStrobePosition( double Position )
1007 {
1008 unsigned short RegVal;
1009
1010 if ( Position < APN_STROBE_POSITION_MIN )
1011 Position = APN_STROBE_POSITION_MIN;
1012
1013 RegVal = (unsigned short)((Position - APN_STROBE_POSITION_MIN) / APN_TIMER_RESOLUTION);
1014
1015 Write( FPGA_REG_SHUTTER_STROBE_POSITION, RegVal );
1016
1017 m_pvtShutterStrobePosition = Position;
1018 }
1019
1020 double CApnCamera::read_ShutterStrobePeriod()
1021 {
1022 return m_pvtShutterStrobePeriod;
1023 }
1024
1025 void CApnCamera::write_ShutterStrobePeriod( double Period )
1026 {
1027 unsigned short RegVal;
1028
1029 if ( Period < APN_STROBE_PERIOD_MIN )
1030 Period = APN_STROBE_PERIOD_MIN;
1031
1032 RegVal = (unsigned short)((Period - APN_STROBE_PERIOD_MIN) / APN_PERIOD_TIMER_RESOLUTION);
1033
1034 Write( FPGA_REG_SHUTTER_STROBE_PERIOD, RegVal );
1035
1036 m_pvtShutterStrobePeriod = Period;
1037 }
1038
1039 double CApnCamera::read_SequenceDelay()
1040 {
1041 return m_pvtSequenceDelay;
1042 }
1043
1044 void CApnCamera::write_SequenceDelay( double Delay )
1045 {
1046 unsigned short RegVal;
1047
1048 if ( Delay > APN_SEQUENCE_DELAY_LIMIT )
1049 Delay = APN_SEQUENCE_DELAY_LIMIT;
1050
1051 m_pvtSequenceDelay = Delay;
1052
1053 RegVal = (unsigned short)(Delay / APN_SEQUENCE_DELAY_RESOLUTION);
1054
1055 Write( FPGA_REG_SEQUENCE_DELAY, RegVal );
1056 }
1057
1058 bool CApnCamera::read_VariableSequenceDelay()
1059 {
1060 unsigned short RegVal;
1061 Read( FPGA_REG_OP_A, RegVal );
1062 // variable delay occurs when the bit is 0
1063 return ( (RegVal & FPGA_BIT_DELAY_MODE) == 0 );
1064 }
1065
1066 void CApnCamera::write_VariableSequenceDelay( bool VariableSequenceDelay )
1067 {
1068 unsigned short RegVal;
1069
1070 Read( FPGA_REG_OP_A, RegVal );
1071
1072 if ( VariableSequenceDelay )
1073 RegVal &= ~FPGA_BIT_DELAY_MODE; // variable when zero
1074 else
1075 RegVal |= FPGA_BIT_DELAY_MODE; // constant when one
1076
1077 Write( FPGA_REG_OP_A, RegVal );
1078 }
1079
1080 unsigned short CApnCamera::read_ImageCount()
1081 {
1082 return m_pvtImageCount;
1083 }
1084
1085 void CApnCamera::write_ImageCount( unsigned short Count )
1086 {
1087 if ( Count == 0 )
1088 Count = 1;
1089
1090 Write( FPGA_REG_IMAGE_COUNT, Count );
1091
1092 m_pvtImageCount = Count;
1093 }
1094
1095 void CApnCamera::write_RoiBinningH( unsigned short BinningH )
1096 {
1097 // Check to see if we actually need to update the binning
1098 if ( BinningH != m_RoiBinningH )
1099 {
1100 // Reset the camera
1101 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
1102
1103 LoadRoiPattern( BinningH );
1104 m_RoiBinningH = BinningH;
1105
1106 // Reset the camera
1107 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
1108
1109 // Start flushing
1110 Write( FPGA_REG_COMMAND_A, FPGA_BIT_CMD_FLUSH );
1111 }
1112 }
1113
1114 void CApnCamera::write_RoiBinningV( unsigned short BinningV )
1115 {
1116 // Check to see if we actually need to update the binning
1117 if ( BinningV != m_RoiBinningV )
1118 {
1119 m_RoiBinningV = BinningV;
1120 }
1121 }
1122
1123 void CApnCamera::write_RoiPixelsV( unsigned short PixelsV )
1124 {
1125 m_RoiPixelsV = PixelsV;
1126 }
1127
1128 void CApnCamera::write_RoiStartY( unsigned short StartY )
1129 {
1130 m_RoiStartY = StartY;
1131 }
1132
1133 unsigned short CApnCamera::read_OverscanColumns()
1134 {
1135 return m_ApnSensorInfo->m_OverscanColumns;
1136 }
1137
1138 unsigned short CApnCamera::read_MaxBinningV()
1139 {
1140 if ( m_ApnSensorInfo->m_ImagingRows < APN_VBINNING_MAX )
1141 return m_ApnSensorInfo->m_ImagingRows;
1142 else
1143 return APN_VBINNING_MAX;
1144 }
1145
1146 unsigned short CApnCamera::read_SequenceCounter()
1147 {
1148 unsigned short RegVal;
1149 Read( FPGA_REG_SEQUENCE_COUNTER, RegVal );
1150 return RegVal;
1151 }
1152
1153 unsigned short CApnCamera::read_TDICounter()
1154 {
1155 unsigned short RegVal;
1156 Read( FPGA_REG_TDI_COUNTER, RegVal );
1157 return RegVal;
1158 }
1159
1160 unsigned short CApnCamera::read_TDIRows()
1161 {
1162 return m_pvtTDIRows;
1163 }
1164
1165 void CApnCamera::write_TDIRows( unsigned short TdiRows )
1166 {
1167 if ( TdiRows == 0 ) // Make sure the TDI row count is at least 1
1168 TdiRows = 1;
1169
1170 Write( FPGA_REG_TDI_COUNT, TdiRows );
1171 m_pvtTDIRows = TdiRows;
1172 }
1173
1174 double CApnCamera::read_TDIRate()
1175 {
1176 return m_pvtTDIRate;
1177 }
1178
1179 void CApnCamera::write_TDIRate( double TdiRate )
1180 {
1181 unsigned short RegVal;
1182
1183 if ( TdiRate < APN_TDI_RATE_MIN )
1184 TdiRate = APN_TDI_RATE_MIN;
1185
1186 if ( TdiRate > APN_TDI_RATE_MAX )
1187 TdiRate = APN_TDI_RATE_MAX;
1188
1189 RegVal = (unsigned short)( TdiRate / APN_TDI_RATE_RESOLUTION );
1190
1191 Write( FPGA_REG_TDI_RATE, RegVal );
1192
1193 m_pvtTDIRate = TdiRate;
1194 }
1195
1196 unsigned short CApnCamera::read_IoPortAssignment()
1197 {
1198 unsigned short RegVal;
1199 Read( FPGA_REG_IO_PORT_ASSIGNMENT, RegVal );
1200 RegVal &= FPGA_MASK_IO_PORT_ASSIGNMENT;
1201 return RegVal;
1202 }
1203
1204 void CApnCamera::write_IoPortAssignment( unsigned short IoPortAssignment )
1205 {
1206 IoPortAssignment &= FPGA_MASK_IO_PORT_ASSIGNMENT;
1207 Write( FPGA_REG_IO_PORT_ASSIGNMENT, IoPortAssignment );
1208 }
1209
1210 unsigned short CApnCamera::read_IoPortDirection()
1211 {
1212 unsigned short RegVal;
1213 Read( FPGA_REG_IO_PORT_DIRECTION, RegVal );
1214 RegVal &= FPGA_MASK_IO_PORT_DIRECTION;
1215 return RegVal;
1216 }
1217
1218 void CApnCamera::write_IoPortDirection( unsigned short IoPortDirection )
1219 {
1220 IoPortDirection &= FPGA_MASK_IO_PORT_DIRECTION;
1221 Write( FPGA_REG_IO_PORT_DIRECTION, IoPortDirection );
1222 }
1223
1224 unsigned short CApnCamera::read_IoPortData()
1225 {
1226 unsigned short RegVal;
1227 Read( FPGA_REG_IO_PORT_READ, RegVal );
1228 RegVal &= FPGA_MASK_IO_PORT_DATA;
1229 return RegVal;
1230 }
1231
1232 void CApnCamera::write_IoPortData( unsigned short IoPortData )
1233 {
1234 IoPortData &= FPGA_MASK_IO_PORT_DATA;
1235 Write( FPGA_REG_IO_PORT_WRITE, IoPortData );
1236 }
1237
1238 unsigned short CApnCamera::read_TwelveBitGain()
1239 {
1240 return m_pvtTwelveBitGain;
1241 }
1242
1243 void CApnCamera::write_TwelveBitGain( unsigned short TwelveBitGain )
1244 {
1245 unsigned short NewVal;
1246 unsigned short StartVal;
1247 unsigned short FirstBit;
1248
1249 NewVal = 0x0;
1250 StartVal = TwelveBitGain & 0x3FF;
1251
1252 for ( int i=0; i<10; i++ )
1253 {
1254 FirstBit = ( StartVal & 0x0001 );
1255 NewVal |= ( FirstBit << (10-i) );
1256 StartVal = StartVal >> 1;
1257 }
1258
1259 NewVal |= 0x4000;
1260
1261 Write( FPGA_REG_AD_CONFIG_DATA, NewVal );
1262 Write( FPGA_REG_COMMAND_B, 0x8000 );
1263
1264 m_pvtTwelveBitGain = TwelveBitGain & 0x3FF;
1265 }
1266
1267 double CApnCamera::read_MaxExposureTime()
1268 {
1269 return APN_EXPOSURE_TIME_MAX;
1270 }
1271
1272 double CApnCamera::read_TestLedBrightness()
1273 {
1274 return m_pvtTestLedBrightness;
1275 }
1276
1277 void CApnCamera::write_TestLedBrightness( double TestLedBrightness )
1278 {
1279 unsigned short RegVal;
1280 unsigned short OpRegA;
1281
1282
1283 if ( TestLedBrightness == m_pvtTestLedBrightness )
1284 return;
1285
1286 if ( m_pvtCoolerEnable )
1287 {
1288 Read( FPGA_REG_OP_A, OpRegA );
1289 OpRegA |= FPGA_BIT_TEMP_SUSPEND;
1290 Write( FPGA_REG_OP_A, OpRegA );
1291
1292 do
1293 {
1294 Read( FPGA_REG_GENERAL_STATUS, RegVal );
1295 } while ( (RegVal & FPGA_BIT_STATUS_TEMP_SUSPEND_ACK) == 0 );
1296
1297 }
1298
1299 RegVal = (unsigned short)( (double)FPGA_MASK_LED_ILLUMINATION * (TestLedBrightness/100.0) );
1300
1301 Write( FPGA_REG_LED_DRIVE, RegVal );
1302
1303 Read( FPGA_REG_OP_B, RegVal );
1304 RegVal &= ~FPGA_BIT_DAC_SELECT_ZERO;
1305 RegVal |= FPGA_BIT_DAC_SELECT_ONE;
1306 Write( FPGA_REG_OP_B, RegVal );
1307
1308 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_DAC_LOAD );
1309
1310 m_pvtTestLedBrightness = TestLedBrightness;
1311
1312 if ( m_pvtCoolerEnable )
1313 {
1314 OpRegA &= ~FPGA_BIT_TEMP_SUSPEND;
1315 Write( FPGA_REG_OP_A, OpRegA );
1316 }
1317 }
1318
1319
1320
1321
1322
1323
1324
1325
1326 long CApnCamera::LoadVerticalPattern()
1327 {
1328 unsigned short RegData;
1329
1330 // Prime the RAM (Enable)
1331 Read( FPGA_REG_OP_B, RegData );
1332 RegData |= FPGA_BIT_VRAM_ENABLE;
1333 Write( FPGA_REG_OP_B, RegData );
1334
1335 WriteMultiSRMD( FPGA_REG_VRAM_INPUT,
1336 m_ApnSensorInfo->m_VerticalPattern.PatternData,
1337 m_ApnSensorInfo->m_VerticalPattern.NumElements );
1338
1339 // RAM is now loaded (Disable)
1340 Read( FPGA_REG_OP_B, RegData );
1341 RegData &= ~FPGA_BIT_VRAM_ENABLE;
1342 Write( FPGA_REG_OP_B, RegData );
1343
1344 return 0;
1345 }
1346
1347
1348 long CApnCamera::LoadClampPattern()
1349 {
1350 unsigned short RegData;
1351
1352 // Prime the RAM (Enable)
1353 Read( FPGA_REG_OP_B, RegData );
1354 RegData |= FPGA_BIT_HCLAMP_ENABLE;
1355 Write( FPGA_REG_OP_B, RegData );
1356
1357 if ( m_DataBits == Apn_Resolution_SixteenBit )
1358 {
1359 WriteHorizontalPattern( &m_ApnSensorInfo->m_ClampPatternSixteen,
1360 FPGA_REG_HCLAMP_INPUT,
1361 1 );
1362 }
1363 else if ( m_DataBits == Apn_Resolution_TwelveBit )
1364 {
1365 WriteHorizontalPattern( &m_ApnSensorInfo->m_ClampPatternTwelve,
1366 FPGA_REG_HCLAMP_INPUT,
1367 1 );
1368 }
1369
1370 // RAM is now loaded (Disable)
1371 Read( FPGA_REG_OP_B, RegData );
1372 RegData &= ~FPGA_BIT_HCLAMP_ENABLE;
1373 Write( FPGA_REG_OP_B, RegData );
1374
1375 return 0;
1376 }
1377
1378
1379 long CApnCamera::LoadSkipPattern()
1380 {
1381 unsigned short RegData;
1382
1383 // Prime the RAM (Enable)
1384 Read( FPGA_REG_OP_B, RegData );
1385 RegData |= FPGA_BIT_HSKIP_ENABLE;
1386 Write( FPGA_REG_OP_B, RegData );
1387
1388 if ( m_DataBits == Apn_Resolution_SixteenBit )
1389 {
1390 WriteHorizontalPattern( &m_ApnSensorInfo->m_SkipPatternSixteen,
1391 FPGA_REG_HSKIP_INPUT,
1392 1 );
1393 }
1394 else if ( m_DataBits == Apn_Resolution_TwelveBit )
1395 {
1396 WriteHorizontalPattern( &m_ApnSensorInfo->m_SkipPatternTwelve,
1397 FPGA_REG_HSKIP_INPUT,
1398 1 );
1399 }
1400
1401 // RAM is now loaded (Disable)
1402 Read( FPGA_REG_OP_B, RegData );
1403 RegData &= ~FPGA_BIT_HSKIP_ENABLE;
1404 Write( FPGA_REG_OP_B, RegData );
1405
1406 return 0;
1407 }
1408
1409
1410 long CApnCamera::LoadRoiPattern( unsigned short binning )
1411 {
1412 unsigned short RegData;
1413
1414 // Prime the RAM (Enable)
1415 Read( FPGA_REG_OP_B, RegData );
1416 RegData |= FPGA_BIT_HRAM_ENABLE;
1417 Write( FPGA_REG_OP_B, RegData );
1418
1419 if ( m_DataBits == Apn_Resolution_SixteenBit )
1420 {
1421 WriteHorizontalPattern( &m_ApnSensorInfo->m_RoiPatternSixteen,
1422 FPGA_REG_HRAM_INPUT,
1423 binning );
1424 }
1425 else if ( m_DataBits == Apn_Resolution_TwelveBit )
1426 {
1427 WriteHorizontalPattern( &m_ApnSensorInfo->m_RoiPatternTwelve,
1428 FPGA_REG_HRAM_INPUT,
1429 binning );
1430 }
1431
1432 // RAM is now loaded (Disable)
1433 Read( FPGA_REG_OP_B, RegData );
1434 RegData &= ~FPGA_BIT_HRAM_ENABLE;
1435 Write( FPGA_REG_OP_B, RegData );
1436
1437 return 0;
1438 }
1439
1440
1441 long CApnCamera::WriteHorizontalPattern( APN_HPATTERN_FILE *Pattern,
1442 unsigned short RamReg,
1443 unsigned short Binning )
1444 {
1445 unsigned short i;
1446 unsigned short DataCount;
1447 unsigned short *DataArray;
1448 unsigned short Index;
1449 unsigned short BinNumber;
1450
1451
1452 Index = 0;
1453 BinNumber = Binning - 1; // arrays are zero-based
1454
1455 DataCount = Pattern->RefNumElements +
1456 Pattern->BinNumElements[BinNumber] +
1457 Pattern->SigNumElements;
1458
1459 DataArray = (unsigned short *)malloc(DataCount * sizeof(unsigned short));
1460
1461 for ( i=0; i<Pattern->RefNumElements; i++ )
1462 {
1463 DataArray[Index] = Pattern->RefPatternData[i];
1464 Index++;
1465 }
1466
1467 for ( i=0; i<Pattern->BinNumElements[BinNumber]; i++ )
1468 {
1469 DataArray[Index] = Pattern->BinPatternData[BinNumber][i];
1470 Index++;
1471 }
1472
1473 for ( i=0; i<Pattern->SigNumElements; i++ )
1474 {
1475 DataArray[Index] = Pattern->SigPatternData[i];
1476 Index++;
1477 }
1478
1479 WriteMultiSRMD( RamReg, DataArray, DataCount );
1480
1481 // cleanup
1482 free( DataArray );
1483
1484 return 0;
1485 }
1486
1487
1488 long CApnCamera::InitDefaults()
1489 {
1490 unsigned short RegVal;
1491 unsigned short CameraID;
1492 unsigned short ShutterDelay;
1493
1494 unsigned short PreRoiRows, PostRoiRows;
1495 unsigned short PreRoiVBinning, PostRoiVBinning;
1496 unsigned short UnbinnedRoiY; // Vertical ROI pixels
1497
1498
1499 // Read the Camera ID register
1500 Read( FPGA_REG_CAMERA_ID, CameraID );
1501 CameraID &= FPGA_MASK_CAMERA_ID;
1502
1503 // Look up the ID and dynamically create the m_ApnSensorInfo object
1504 switch ( CameraID )
1505 {
1506 case APN_ALTA_KAF0401E_CAM_ID:
1507 m_ApnSensorInfo = new CApnCamData_KAF0401E;
1508 break;
1509 case APN_ALTA_KAF1602E_CAM_ID:
1510 m_ApnSensorInfo = new CApnCamData_KAF1602E;
1511 break;
1512 case APN_ALTA_KAF0261E_CAM_ID:
1513 m_ApnSensorInfo = new CApnCamData_KAF0261E;
1514 break;
1515 case APN_ALTA_KAF1301E_CAM_ID:
1516 m_ApnSensorInfo = new CApnCamData_KAF1301E;
1517 break;
1518 case APN_ALTA_KAF1401E_CAM_ID:
1519 m_ApnSensorInfo = new CApnCamData_KAF1401E;
1520 break;
1521 case APN_ALTA_KAF1001E_CAM_ID:
1522 m_ApnSensorInfo = new CApnCamData_KAF1001E;
1523 break;
1524 case APN_ALTA_KAF3200E_CAM_ID:
1525 m_ApnSensorInfo = new CApnCamData_KAF3200E;
1526 break;
1527 case APN_ALTA_KAF4202_CAM_ID:
1528 m_ApnSensorInfo = new CApnCamData_KAF4202;
1529 break;
1530 case APN_ALTA_KAF6303E_CAM_ID:
1531 m_ApnSensorInfo = new CApnCamData_KAF6303E;
1532 break;
1533 case APN_ALTA_KAF16801E_CAM_ID:
1534 m_ApnSensorInfo = new CApnCamData_KAF16801E;
1535 break;
1536 case APN_ALTA_TH7899_CAM_ID:
1537 m_ApnSensorInfo = new CApnCamData_TH7899;
1538 break;
1539 case APN_ALTA_CCD4710LS_CAM_ID:
1540 m_ApnSensorInfo = new CApnCamData_CCD4710LS;
1541 break;
1542 case APN_ALTA_CCD4710HS_CAM_ID:
1543 m_ApnSensorInfo = new CApnCamData_CCD4710HS;
1544 break;
1545 case APN_ALTA_CCD4240LS_CAM_ID:
1546 m_ApnSensorInfo = new CApnCamData_CCD4240LS;
1547 break;
1548 case APN_ALTA_CCD4240HS_CAM_ID:
1549 m_ApnSensorInfo = new CApnCamData_CCD4240HS;
1550 break;
1551 case APN_ALTA_CCD5710LS_CAM_ID:
1552 m_ApnSensorInfo = new CApnCamData_CCD5710LS;
1553 break;
1554 case APN_ALTA_CCD5710HS_CAM_ID:
1555 m_ApnSensorInfo = new CApnCamData_CCD5710HS;
1556 break;
1557 case APN_ALTA_CCD3011LS_CAM_ID:
1558 m_ApnSensorInfo = new CApnCamData_CCD3011LS;
1559 break;
1560 case APN_ALTA_CCD3011HS_CAM_ID:
1561 m_ApnSensorInfo = new CApnCamData_CCD3011HS;
1562 break;
1563 case APN_ALTA_CCD5520LS_CAM_ID:
1564 m_ApnSensorInfo = new CApnCamData_CCD5520LS;
1565 break;
1566 case APN_ALTA_CCD5520HS_CAM_ID:
1567 m_ApnSensorInfo = new CApnCamData_CCD5520HS;
1568 break;
1569 case APN_ALTA_CCD4720LS_CAM_ID:
1570 m_ApnSensorInfo = new CApnCamData_CCD4720LS;
1571 break;
1572 case APN_ALTA_CCD4720HS_CAM_ID:
1573 m_ApnSensorInfo = new CApnCamData_CCD4720HS;
1574 break;
1575 case APN_ALTA_CCD7700LS_CAM_ID:
1576 m_ApnSensorInfo = new CApnCamData_CCD7700LS;
1577 break;
1578 case APN_ALTA_CCD7700HS_CAM_ID:
1579 m_ApnSensorInfo = new CApnCamData_CCD7700HS;
1580 break;
1581 case APN_ALTA_CCD4710LS2_CAM_ID:
1582 m_ApnSensorInfo = new CApnCamData_CCD4710LS2;
1583 break;
1584 case APN_ALTA_CCD4710LS3_CAM_ID:
1585 m_ApnSensorInfo = new CApnCamData_CCD4710LS3;
1586 break;
1587 case APN_ALTA_CCD4710LS4_CAM_ID:
1588 m_ApnSensorInfo = new CApnCamData_CCD4710LS4;
1589 break;
1590 case APN_ALTA_CCD4710LS5_CAM_ID:
1591 m_ApnSensorInfo = new CApnCamData_CCD4710LS5;
1592 break;
1593 default:
1594 return 1;
1595 break;
1596 }
1597
1598 // we created the object, now set everything
1599 m_ApnSensorInfo->Initialize();
1600
1601 // Initialize public variables
1602 m_DigitizeOverscan = false;
1603 m_DataBits = Apn_Resolution_SixteenBit;
1604
1605 // Initialize private variables
1606 m_pvtCameraMode = Apn_CameraMode_Normal;
1607 m_pvtNetworkTransferMode = Apn_NetworkMode_Tcp;
1608
1609 // Initialize variables used for imaging
1610 m_RoiStartX = 0;
1611 m_RoiStartY = 0;
1612 m_RoiPixelsH = m_ApnSensorInfo->m_ImagingColumns;
1613 m_RoiPixelsV = m_ApnSensorInfo->m_ImagingRows;
1614
1615 m_RoiBinningH = 1;
1616 m_RoiBinningV = 1;
1617 printf ("Camera ID is %u\n",CameraID);
1618 printf("sensor = %s\n", m_ApnSensorInfo->m_Sensor);
1619 printf("model = %s\n",m_ApnSensorInfo->m_CameraModel);
1620 printf("interline = %u\n",m_ApnSensorInfo->m_InterlineCCD);
1621 printf("serialA = %u\n",m_ApnSensorInfo->m_SupportsSerialA);
1622 printf("serialB = %u\n",m_ApnSensorInfo->m_SupportsSerialB);
1623 printf("ccdtype = %u\n",m_ApnSensorInfo->m_SensorTypeCCD);
1624 printf("Tcolumns = %u\n",m_ApnSensorInfo->m_TotalColumns);
1625 printf("ImgColumns = %u\n",m_ApnSensorInfo->m_ImagingColumns);
1626 printf("ClampColumns = %u\n",m_ApnSensorInfo->m_ClampColumns);
1627 printf("PreRoiSColumns = %u\n",m_ApnSensorInfo->m_PreRoiSkipColumns);
1628 printf("PostRoiSColumns = %u\n",m_ApnSensorInfo->m_PostRoiSkipColumns);
1629 printf("OverscanColumns = %u\n",m_ApnSensorInfo->m_OverscanColumns);
1630 printf("TRows = %u\n",m_ApnSensorInfo->m_TotalRows);
1631 printf("ImgRows = %u\n",m_ApnSensorInfo->m_ImagingRows);
1632 printf("UnderscanRows = %u\n",m_ApnSensorInfo->m_UnderscanRows);
1633 printf("OverscanRows = %u\n",m_ApnSensorInfo->m_OverscanRows);
1634 printf("VFlushBinning = %u\n",m_ApnSensorInfo->m_VFlushBinning);
1635 printf("HFlushDisable = %u\n",m_ApnSensorInfo->m_HFlushDisable);
1636 printf("ShutterCloseDelay = %u\n",m_ApnSensorInfo->m_ShutterCloseDelay);
1637 printf("PixelSizeX = %lf\n",m_ApnSensorInfo->m_PixelSizeX);
1638 printf("PixelSizeY = %lf\n",m_ApnSensorInfo->m_PixelSizeY);
1639 printf("Color = %u\n",m_ApnSensorInfo->m_Color);
1640 // printf("ReportedGainTwelveBit = %lf\n",m_ApnSensorInfo->m_ReportedGainTwelveBit);
1641 printf("ReportedGainSixteenBit = %lf\n",m_ApnSensorInfo->m_ReportedGainSixteenBit);
1642 printf("MinSuggestedExpTime = %lf\n",m_ApnSensorInfo->m_MinSuggestedExpTime);
1643 printf("CoolingSupported = %u\n",m_ApnSensorInfo->m_CoolingSupported);
1644 printf("RegulatedCoolingSupported = %u\n",m_ApnSensorInfo->m_RegulatedCoolingSupported);
1645 printf("TempSetPoint = %lf\n",m_ApnSensorInfo->m_TempSetPoint);
1646 // printf("TempRegRate = %u\n",m_ApnSensorInfo->m_TempRegRate);
1647 printf("TempRampRateOne = %u\n",m_ApnSensorInfo->m_TempRampRateOne);
1648 printf("TempRampRateTwo = %u\n",m_ApnSensorInfo->m_TempRampRateTwo);
1649 printf("TempBackoffPoint = %lf\n",m_ApnSensorInfo->m_TempBackoffPoint);
1650 printf("DefaultGainTwelveBit = %u\n",m_ApnSensorInfo->m_DefaultGainTwelveBit);
1651 printf("DefaultOffsetTwelveBit = %u\n",m_ApnSensorInfo->m_DefaultOffsetTwelveBit);
1652 printf("DefaultRVoltage = %u\n",m_ApnSensorInfo->m_DefaultRVoltage);
1653
1654
1655
1656 printf ("RoiPixelsH is %u\n",m_RoiPixelsH);
1657 printf ("RoiPixelsV is %u\n",m_RoiPixelsV);
1658
1659
1660 // Issue a clear command, so the registers are zeroed out
1661 // This will put the camera in a known state for us.
1662 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_CLEAR_ALL );
1663
1664 // Reset the camera
1665 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
1666
1667 // Load Inversion Masks
1668 Write( FPGA_REG_VRAM_INV_MASK, m_ApnSensorInfo->m_VerticalPattern.Mask );
1669 Write( FPGA_REG_HRAM_INV_MASK, m_ApnSensorInfo->m_RoiPatternSixteen.Mask );
1670
1671 // Load Pattern Files
1672 LoadVerticalPattern();
1673 LoadClampPattern();
1674 LoadSkipPattern();
1675 LoadRoiPattern( m_RoiBinningH );
1676
1677 // Program default camera settings
1678 Write( FPGA_REG_CLAMP_COUNT, m_ApnSensorInfo->m_ClampColumns );
1679 Write( FPGA_REG_PREROI_SKIP_COUNT, m_ApnSensorInfo->m_PreRoiSkipColumns );
1680 Write( FPGA_REG_ROI_COUNT, m_ApnSensorInfo->m_ImagingColumns );
1681 Write( FPGA_REG_POSTROI_SKIP_COUNT, m_ApnSensorInfo->m_PostRoiSkipColumns +
1682 m_ApnSensorInfo->m_OverscanColumns );
1683
1684 // Since the default state of m_DigitizeOverscan is false, set the count to zero.
1685 Write( FPGA_REG_OVERSCAN_COUNT, 0x0 );
1686
1687 // Now calculate the vertical settings
1688 UnbinnedRoiY = m_RoiPixelsV * m_RoiBinningV;
1689
1690 PreRoiRows = m_ApnSensorInfo->m_UnderscanRows +
1691 m_RoiStartY;
1692
1693 PostRoiRows = m_ApnSensorInfo->m_TotalRows -
1694 PreRoiRows -
1695 UnbinnedRoiY;
1696
1697 PreRoiVBinning = 1;
1698 PostRoiVBinning = 1;
1699
1700 // For interline CCDs, set "Fast Dump" mode if the particular array is NOT digitized
1701 if ( m_ApnSensorInfo->m_InterlineCCD )
1702 {
1703 // use the fast dump feature to get rid of the data quickly.
1704 // one row, binning to the original row count
1705 // note that we only are not digitized in arrays 1 and 3
1706 PreRoiVBinning = PreRoiRows;
1707 PostRoiVBinning = PostRoiRows;
1708
1709 PreRoiVBinning |= FPGA_BIT_ARRAY_FASTDUMP;
1710 PostRoiVBinning |= FPGA_BIT_ARRAY_FASTDUMP;
1711
1712 PreRoiRows = 1;
1713 PostRoiRows = 1;
1714 }
1715
1716 // Program the vertical settings
1717 Write( FPGA_REG_A1_ROW_COUNT, PreRoiRows );
1718 Write( FPGA_REG_A1_VBINNING, PreRoiVBinning );
1719
1720 Write( FPGA_REG_A2_ROW_COUNT, m_RoiPixelsV );
1721 Write( FPGA_REG_A2_VBINNING, (m_RoiBinningV | FPGA_BIT_ARRAY_DIGITIZE) );
1722
1723 Write( FPGA_REG_A3_ROW_COUNT, PostRoiRows );
1724 Write( FPGA_REG_A3_VBINNING, PostRoiVBinning );
1725
1726 Write( FPGA_REG_VFLUSH_BINNING, m_ApnSensorInfo->m_VFlushBinning );
1727
1728 double CloseDelay = (double)m_ApnSensorInfo->m_ShutterCloseDelay / 1000;
1729 ShutterDelay = (unsigned short)
1730 ( (CloseDelay - APN_SHUTTER_CLOSE_DIFF) / APN_TIMER_RESOLUTION );
1731
1732 Write( FPGA_REG_SHUTTER_CLOSE_DELAY, ShutterDelay );
1733
1734 Write( FPGA_REG_IMAGE_COUNT, 1 );
1735 Write( FPGA_REG_SEQUENCE_DELAY, 0 );
1736
1737 if ( m_ApnSensorInfo->m_HFlushDisable )
1738 {
1739 Read( FPGA_REG_OP_A, RegVal );
1740
1741 RegVal |= FPGA_BIT_DISABLE_H_CLK;
1742
1743 Write( FPGA_REG_OP_A, RegVal );
1744 }
1745
1746 // Reset the camera again
1747 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
1748
1749 // Start flushing
1750 Write( FPGA_REG_COMMAND_A, FPGA_BIT_CMD_FLUSH );
1751
1752 // If we are a USB2 camera, set all the 12bit variables for the 12bit
1753 // A/D processor
1754 if ( m_CameraInterface == Apn_Interface_USB )
1755 {
1756 InitTwelveBitAD();
1757 write_TwelveBitGain( m_ApnSensorInfo->m_DefaultGainTwelveBit );
1758 WriteTwelveBitOffset();
1759 }
1760
1761 // Set the Fan State. Setting the private var first to make sure the write_FanMode
1762 // call thinks we're doing a state transition.
1763 // On write_FanMode return, our state will be Apn_FanMode_Medium
1764 m_pvtFanMode = Apn_FanMode_Off; // we're going to set this
1765 write_FanMode( Apn_FanMode_Medium );
1766
1767 // Initialize the LED states and the LED mode. There is nothing to output
1768 // to the device since we issued our CLEAR early in the init() process, and
1769 // we are now in a known state.
1770 m_pvtLedStateA = Apn_LedState_Expose;
1771 m_pvtLedStateB = Apn_LedState_Expose;
1772 m_pvtLedMode = Apn_LedMode_EnableAll;
1773
1774 // Default value for test LED is 0%
1775 m_pvtTestLedBrightness = 0.0;
1776
1777 // Program our initial cooler values. The only cooler value that we reset
1778 // at init time is the backoff point. Everything else is left untouched, and
1779 // state information is determined from the camera controller.
1780 m_pvtCoolerBackoffPoint = m_ApnSensorInfo->m_TempBackoffPoint;
1781 write_CoolerBackoffPoint( m_pvtCoolerBackoffPoint );
1782 Write( FPGA_REG_TEMP_RAMP_DOWN_A, m_ApnSensorInfo->m_TempRampRateOne );
1783 Write( FPGA_REG_TEMP_RAMP_DOWN_B, m_ApnSensorInfo->m_TempRampRateTwo );
1784 // the collor code not only determines the m_pvtCoolerEnable state, but
1785 // also implicitly calls UpdateGeneralStatus() as part of read_CoolerStatus()
1786 if ( read_CoolerStatus() == Apn_CoolerStatus_Off )
1787 m_pvtCoolerEnable = false;
1788 else
1789 m_pvtCoolerEnable = true;
1790
1791 m_pvtImageInProgress = false;
1792 m_pvtImageReady = false;
1793
1794 return 0;
1795 }
1796
1797 long CApnCamera::InitTwelveBitAD()
1798 {
1799 Write( FPGA_REG_AD_CONFIG_DATA, 0x0028 );
1800 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_AD_CONFIG );
1801
1802 return 0;
1803 }
1804
1805 long CApnCamera::WriteTwelveBitOffset()
1806 {
1807 unsigned short NewVal;
1808 unsigned short StartVal;
1809 unsigned short FirstBit;
1810
1811
1812 NewVal = 0x0;
1813 StartVal = m_ApnSensorInfo->m_DefaultOffsetTwelveBit & 0xFF;
1814
1815 for ( int i=0; i<8; i++ )
1816 {
1817 FirstBit = ( StartVal & 0x0001 );
1818 NewVal |= ( FirstBit << (10-i) );
1819 StartVal = StartVal >> 1;
1820 }
1821
1822 NewVal |= 0x2000;
1823
1824 Write( FPGA_REG_AD_CONFIG_DATA, NewVal );
1825 Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_AD_CONFIG );
1826
1827 return 0;
1828 }
1829
1830 void CApnCamera::UpdateGeneralStatus()
1831 {
1832 unsigned short StatusReg;
1833 unsigned short HeatsinkTempReg;
1834 unsigned short CcdTempReg;
1835 unsigned short CoolerDriveReg;
1836 unsigned short VoltageReg;
1837 unsigned short TdiCounterReg;
1838 unsigned short SequenceCounterReg;
1839
1840
1841
1842 // Read the general status register of the device
1843 QueryStatusRegs( StatusReg,
1844 HeatsinkTempReg,
1845 CcdTempReg,
1846 CoolerDriveReg,
1847 VoltageReg,
1848 TdiCounterReg,
1849 SequenceCounterReg );
1850
1851 m_pvtStatusReg = StatusReg;
1852
1853 HeatsinkTempReg &= FPGA_MASK_TEMP_PARAMS;
1854 CcdTempReg &= FPGA_MASK_TEMP_PARAMS;
1855 CoolerDriveReg &= FPGA_MASK_TEMP_PARAMS;
1856 VoltageReg &= FPGA_MASK_INPUT_VOLTAGE;
1857
1858 if ( CoolerDriveReg > 3200 )
1859 m_pvtCoolerDrive = 100.0;
1860 else
1861 m_pvtCoolerDrive = ( (double)(CoolerDriveReg - 600) / 2600.0 ) * 100.0;
1862
1863 m_pvtCurrentCcdTemp = ( (CcdTempReg - APN_TEMP_SETPOINT_ZERO_POINT)
1864 * APN_TEMP_DEGREES_PER_BIT );
1865
1866 m_pvtCurrentHeatsinkTemp = ( (HeatsinkTempReg - APN_TEMP_HEATSINK_ZERO_POINT)
1867 * APN_TEMP_DEGREES_PER_BIT );
1868
1869 m_pvtInputVoltage = VoltageReg * APN_VOLTAGE_RESOLUTION;
1870
1871 // Update ShutterState
1872 m_pvtShutterState = ( (m_pvtStatusReg & FPGA_BIT_STATUS_SHUTTER_OPEN) != 0 );
1873 }
1874
1875
1876 bool CApnCamera::ImageReady()
1877 {
1878 return m_pvtImageReady;
1879 }
1880
1881
1882 void CApnCamera::SignalImagingDone()
1883 {
1884 m_pvtImageInProgress = false;
1885 }
1886
1887
1888
1889
1890
Experimental kdeedu stuff