2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
30 #include <asm/div64.h>
32 #include <mach/sdrc.h>
36 #include "prm-regbits-24xx.h"
38 #include "cm-regbits-24xx.h"
39 #include "cm-regbits-34xx.h"
41 #define MAX_CLOCK_ENABLE_WAIT 100000
43 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
44 #define DPLL_MIN_MULTIPLIER 1
45 #define DPLL_MIN_DIVIDER 1
47 /* Possible error results from _dpll_test_mult */
48 #define DPLL_MULT_UNDERFLOW -1
51 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
52 * The higher the scale factor, the greater the risk of arithmetic overflow,
53 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
54 * must be a power of DPLL_SCALE_BASE.
56 #define DPLL_SCALE_FACTOR 64
57 #define DPLL_SCALE_BASE 2
58 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
59 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
61 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
62 #define DPLL_FINT_BAND1_MIN 750000
63 #define DPLL_FINT_BAND1_MAX 2100000
64 #define DPLL_FINT_BAND2_MIN 7500000
65 #define DPLL_FINT_BAND2_MAX 21000000
67 /* _dpll_test_fint() return codes */
68 #define DPLL_FINT_UNDERFLOW -1
69 #define DPLL_FINT_INVALID -2
73 /*-------------------------------------------------------------------------
74 * OMAP2/3 specific clock functions
75 *-------------------------------------------------------------------------*/
78 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
79 * @clk: DPLL struct clk to test
80 * @n: divider value (N) to test
82 * Tests whether a particular divider @n will result in a valid DPLL
83 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
84 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
85 * (assuming that it is counting N upwards), or -2 if the enclosing loop
86 * should skip to the next iteration (again assuming N is increasing).
88 static int _dpll_test_fint(struct clk
*clk
, u8 n
)
96 /* DPLL divider must result in a valid jitter correction val */
97 fint
= clk
->parent
->rate
/ (n
+ 1);
98 if (fint
< DPLL_FINT_BAND1_MIN
) {
100 pr_debug("rejecting n=%d due to Fint failure, "
101 "lowering max_divider\n", n
);
103 ret
= DPLL_FINT_UNDERFLOW
;
105 } else if (fint
> DPLL_FINT_BAND1_MAX
&&
106 fint
< DPLL_FINT_BAND2_MIN
) {
108 pr_debug("rejecting n=%d due to Fint failure\n", n
);
109 ret
= DPLL_FINT_INVALID
;
111 } else if (fint
> DPLL_FINT_BAND2_MAX
) {
113 pr_debug("rejecting n=%d due to Fint failure, "
114 "boosting min_divider\n", n
);
116 ret
= DPLL_FINT_INVALID
;
124 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
125 * @clk: OMAP clock struct ptr to use
127 * Convert a clockdomain name stored in a struct clk 'clk' into a
128 * clockdomain pointer, and save it into the struct clk. Intended to be
129 * called during clk_register(). No return value.
131 void omap2_init_clk_clkdm(struct clk
*clk
)
133 struct clockdomain
*clkdm
;
135 if (!clk
->clkdm_name
)
138 clkdm
= clkdm_lookup(clk
->clkdm_name
);
140 pr_debug("clock: associated clk %s to clkdm %s\n",
141 clk
->name
, clk
->clkdm_name
);
144 pr_debug("clock: could not associate clk %s to "
145 "clkdm %s\n", clk
->name
, clk
->clkdm_name
);
150 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
151 * @clk: OMAP clock struct ptr to use
153 * Given a pointer to a source-selectable struct clk, read the hardware
154 * register and determine what its parent is currently set to. Update the
155 * clk->parent field with the appropriate clk ptr.
157 void omap2_init_clksel_parent(struct clk
*clk
)
159 const struct clksel
*clks
;
160 const struct clksel_rate
*clkr
;
166 r
= __raw_readl(clk
->clksel_reg
) & clk
->clksel_mask
;
167 r
>>= __ffs(clk
->clksel_mask
);
169 for (clks
= clk
->clksel
; clks
->parent
&& !found
; clks
++) {
170 for (clkr
= clks
->rates
; clkr
->div
&& !found
; clkr
++) {
171 if ((clkr
->flags
& cpu_mask
) && (clkr
->val
== r
)) {
172 if (clk
->parent
!= clks
->parent
) {
173 pr_debug("clock: inited %s parent "
175 clk
->name
, clks
->parent
->name
,
177 clk
->parent
->name
: "NULL"));
178 clk_reparent(clk
, clks
->parent
);
186 printk(KERN_ERR
"clock: init parent: could not find "
187 "regval %0x for clock %s\n", r
, clk
->name
);
192 /* Returns the DPLL rate */
193 u32
omap2_get_dpll_rate(struct clk
*clk
)
196 u32 dpll_mult
, dpll_div
, dpll
;
197 struct dpll_data
*dd
;
200 /* REVISIT: What do we return on error? */
204 dpll
= __raw_readl(dd
->mult_div1_reg
);
205 dpll_mult
= dpll
& dd
->mult_mask
;
206 dpll_mult
>>= __ffs(dd
->mult_mask
);
207 dpll_div
= dpll
& dd
->div1_mask
;
208 dpll_div
>>= __ffs(dd
->div1_mask
);
210 dpll_clk
= (long long)clk
->parent
->rate
* dpll_mult
;
211 do_div(dpll_clk
, dpll_div
+ 1);
217 * Used for clocks that have the same value as the parent clock,
218 * divided by some factor
220 void omap2_fixed_divisor_recalc(struct clk
*clk
)
222 WARN_ON(!clk
->fixed_div
);
224 clk
->rate
= clk
->parent
->rate
/ clk
->fixed_div
;
228 * omap2_wait_clock_ready - wait for clock to enable
229 * @reg: physical address of clock IDLEST register
230 * @mask: value to mask against to determine if the clock is active
231 * @name: name of the clock (for printk)
233 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
234 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
236 int omap2_wait_clock_ready(void __iomem
*reg
, u32 mask
, const char *name
)
242 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
243 * 34xx reverses this, just to keep us on our toes
245 if (cpu_mask
& (RATE_IN_242X
| RATE_IN_243X
))
247 else if (cpu_mask
& RATE_IN_343X
)
251 while (((__raw_readl(reg
) & mask
) != ena
) &&
252 (i
++ < MAX_CLOCK_ENABLE_WAIT
)) {
256 if (i
< MAX_CLOCK_ENABLE_WAIT
)
257 pr_debug("Clock %s stable after %d loops\n", name
, i
);
259 printk(KERN_ERR
"Clock %s didn't enable in %d tries\n",
260 name
, MAX_CLOCK_ENABLE_WAIT
);
263 return (i
< MAX_CLOCK_ENABLE_WAIT
) ? 1 : 0;
268 * Note: We don't need special code here for INVERT_ENABLE
269 * for the time being since INVERT_ENABLE only applies to clocks enabled by
272 static void omap2_clk_wait_ready(struct clk
*clk
)
274 void __iomem
*reg
, *other_reg
, *st_reg
;
278 * REVISIT: This code is pretty ugly. It would be nice to generalize
279 * it and pull it into struct clk itself somehow.
281 reg
= clk
->enable_reg
;
284 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
285 * it's just a matter of XORing the bits.
287 other_reg
= (void __iomem
*)((u32
)reg
^ (CM_FCLKEN
^ CM_ICLKEN
));
289 /* Check if both functional and interface clocks
291 bit
= 1 << clk
->enable_bit
;
292 if (!(__raw_readl(other_reg
) & bit
))
294 st_reg
= (void __iomem
*)(((u32
)other_reg
& ~0xf0) | 0x20); /* CM_IDLEST* */
296 omap2_wait_clock_ready(st_reg
, bit
, clk
->name
);
299 static int omap2_dflt_clk_enable(struct clk
*clk
)
303 if (unlikely(clk
->enable_reg
== NULL
)) {
304 printk(KERN_ERR
"clock.c: Enable for %s without enable code\n",
306 return 0; /* REVISIT: -EINVAL */
309 v
= __raw_readl(clk
->enable_reg
);
310 if (clk
->flags
& INVERT_ENABLE
)
311 v
&= ~(1 << clk
->enable_bit
);
313 v
|= (1 << clk
->enable_bit
);
314 __raw_writel(v
, clk
->enable_reg
);
320 static int omap2_dflt_clk_enable_wait(struct clk
*clk
)
324 if (!clk
->enable_reg
) {
325 printk(KERN_ERR
"clock.c: Enable for %s without enable code\n",
327 return 0; /* REVISIT: -EINVAL */
330 ret
= omap2_dflt_clk_enable(clk
);
332 omap2_clk_wait_ready(clk
);
336 static void omap2_dflt_clk_disable(struct clk
*clk
)
340 if (!clk
->enable_reg
) {
342 * 'Independent' here refers to a clock which is not
343 * controlled by its parent.
345 printk(KERN_ERR
"clock: clk_disable called on independent "
346 "clock %s which has no enable_reg\n", clk
->name
);
350 v
= __raw_readl(clk
->enable_reg
);
351 if (clk
->flags
& INVERT_ENABLE
)
352 v
|= (1 << clk
->enable_bit
);
354 v
&= ~(1 << clk
->enable_bit
);
355 __raw_writel(v
, clk
->enable_reg
);
356 /* No OCP barrier needed here since it is a disable operation */
359 const struct clkops clkops_omap2_dflt_wait
= {
360 .enable
= omap2_dflt_clk_enable_wait
,
361 .disable
= omap2_dflt_clk_disable
,
364 const struct clkops clkops_omap2_dflt
= {
365 .enable
= omap2_dflt_clk_enable
,
366 .disable
= omap2_dflt_clk_disable
,
369 /* Enables clock without considering parent dependencies or use count
370 * REVISIT: Maybe change this to use clk->enable like on omap1?
372 static int _omap2_clk_enable(struct clk
*clk
)
374 return clk
->ops
->enable(clk
);
377 /* Disables clock without considering parent dependencies or use count */
378 static void _omap2_clk_disable(struct clk
*clk
)
380 clk
->ops
->disable(clk
);
383 void omap2_clk_disable(struct clk
*clk
)
385 if (clk
->usecount
> 0 && !(--clk
->usecount
)) {
386 _omap2_clk_disable(clk
);
388 omap2_clk_disable(clk
->parent
);
390 omap2_clkdm_clk_disable(clk
->clkdm
, clk
);
395 int omap2_clk_enable(struct clk
*clk
)
399 if (clk
->usecount
++ == 0) {
401 ret
= omap2_clk_enable(clk
->parent
);
409 omap2_clkdm_clk_enable(clk
->clkdm
, clk
);
411 ret
= _omap2_clk_enable(clk
);
415 omap2_clkdm_clk_disable(clk
->clkdm
, clk
);
418 omap2_clk_disable(clk
->parent
);
428 * Used for clocks that are part of CLKSEL_xyz governed clocks.
429 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
431 void omap2_clksel_recalc(struct clk
*clk
)
435 pr_debug("clock: recalc'ing clksel clk %s\n", clk
->name
);
437 div
= omap2_clksel_get_divisor(clk
);
441 if (clk
->rate
== (clk
->parent
->rate
/ div
))
443 clk
->rate
= clk
->parent
->rate
/ div
;
445 pr_debug("clock: new clock rate is %ld (div %d)\n", clk
->rate
, div
);
449 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
450 * @clk: OMAP struct clk ptr to inspect
451 * @src_clk: OMAP struct clk ptr of the parent clk to search for
453 * Scan the struct clksel array associated with the clock to find
454 * the element associated with the supplied parent clock address.
455 * Returns a pointer to the struct clksel on success or NULL on error.
457 static const struct clksel
*omap2_get_clksel_by_parent(struct clk
*clk
,
460 const struct clksel
*clks
;
465 for (clks
= clk
->clksel
; clks
->parent
; clks
++) {
466 if (clks
->parent
== src_clk
)
467 break; /* Found the requested parent */
471 printk(KERN_ERR
"clock: Could not find parent clock %s in "
472 "clksel array of clock %s\n", src_clk
->name
,
481 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
482 * @clk: OMAP struct clk to use
483 * @target_rate: desired clock rate
484 * @new_div: ptr to where we should store the divisor
486 * Finds 'best' divider value in an array based on the source and target
487 * rates. The divider array must be sorted with smallest divider first.
488 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
489 * they are only settable as part of virtual_prcm set.
491 * Returns the rounded clock rate or returns 0xffffffff on error.
493 u32
omap2_clksel_round_rate_div(struct clk
*clk
, unsigned long target_rate
,
496 unsigned long test_rate
;
497 const struct clksel
*clks
;
498 const struct clksel_rate
*clkr
;
501 printk(KERN_INFO
"clock: clksel_round_rate_div: %s target_rate %ld\n",
502 clk
->name
, target_rate
);
506 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
510 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
511 if (!(clkr
->flags
& cpu_mask
))
515 if (clkr
->div
<= last_div
)
516 printk(KERN_ERR
"clock: clksel_rate table not sorted "
517 "for clock %s", clk
->name
);
519 last_div
= clkr
->div
;
521 test_rate
= clk
->parent
->rate
/ clkr
->div
;
523 if (test_rate
<= target_rate
)
524 break; /* found it */
528 printk(KERN_ERR
"clock: Could not find divisor for target "
529 "rate %ld for clock %s parent %s\n", target_rate
,
530 clk
->name
, clk
->parent
->name
);
534 *new_div
= clkr
->div
;
536 printk(KERN_INFO
"clock: new_div = %d, new_rate = %ld\n", *new_div
,
537 (clk
->parent
->rate
/ clkr
->div
));
539 return (clk
->parent
->rate
/ clkr
->div
);
543 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
544 * @clk: OMAP struct clk to use
545 * @target_rate: desired clock rate
547 * Compatibility wrapper for OMAP clock framework
548 * Finds best target rate based on the source clock and possible dividers.
549 * rates. The divider array must be sorted with smallest divider first.
550 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
551 * they are only settable as part of virtual_prcm set.
553 * Returns the rounded clock rate or returns 0xffffffff on error.
555 long omap2_clksel_round_rate(struct clk
*clk
, unsigned long target_rate
)
559 return omap2_clksel_round_rate_div(clk
, target_rate
, &new_div
);
563 /* Given a clock and a rate apply a clock specific rounding function */
564 long omap2_clk_round_rate(struct clk
*clk
, unsigned long rate
)
567 return clk
->round_rate(clk
, rate
);
569 if (clk
->flags
& RATE_FIXED
)
570 printk(KERN_ERR
"clock: generic omap2_clk_round_rate called "
571 "on fixed-rate clock %s\n", clk
->name
);
577 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
578 * @clk: OMAP struct clk to use
579 * @field_val: register field value to find
581 * Given a struct clk of a rate-selectable clksel clock, and a register field
582 * value to search for, find the corresponding clock divisor. The register
583 * field value should be pre-masked and shifted down so the LSB is at bit 0
584 * before calling. Returns 0 on error
586 u32
omap2_clksel_to_divisor(struct clk
*clk
, u32 field_val
)
588 const struct clksel
*clks
;
589 const struct clksel_rate
*clkr
;
591 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
595 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
596 if ((clkr
->flags
& cpu_mask
) && (clkr
->val
== field_val
))
601 printk(KERN_ERR
"clock: Could not find fieldval %d for "
602 "clock %s parent %s\n", field_val
, clk
->name
,
611 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
612 * @clk: OMAP struct clk to use
613 * @div: integer divisor to search for
615 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
616 * find the corresponding register field value. The return register value is
617 * the value before left-shifting. Returns 0xffffffff on error
619 u32
omap2_divisor_to_clksel(struct clk
*clk
, u32 div
)
621 const struct clksel
*clks
;
622 const struct clksel_rate
*clkr
;
624 /* should never happen */
627 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
631 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
632 if ((clkr
->flags
& cpu_mask
) && (clkr
->div
== div
))
637 printk(KERN_ERR
"clock: Could not find divisor %d for "
638 "clock %s parent %s\n", div
, clk
->name
,
647 * omap2_clksel_get_divisor - get current divider applied to parent clock.
648 * @clk: OMAP struct clk to use.
650 * Returns the integer divisor upon success or 0 on error.
652 u32
omap2_clksel_get_divisor(struct clk
*clk
)
656 if (!clk
->clksel_mask
)
659 v
= __raw_readl(clk
->clksel_reg
) & clk
->clksel_mask
;
660 v
>>= __ffs(clk
->clksel_mask
);
662 return omap2_clksel_to_divisor(clk
, v
);
665 int omap2_clksel_set_rate(struct clk
*clk
, unsigned long rate
)
667 u32 v
, field_val
, validrate
, new_div
= 0;
669 if (!clk
->clksel_mask
)
672 validrate
= omap2_clksel_round_rate_div(clk
, rate
, &new_div
);
673 if (validrate
!= rate
)
676 field_val
= omap2_divisor_to_clksel(clk
, new_div
);
680 v
= __raw_readl(clk
->clksel_reg
);
681 v
&= ~clk
->clksel_mask
;
682 v
|= field_val
<< __ffs(clk
->clksel_mask
);
683 __raw_writel(v
, clk
->clksel_reg
);
686 clk
->rate
= clk
->parent
->rate
/ new_div
;
688 if (clk
->flags
& DELAYED_APP
&& cpu_is_omap24xx()) {
689 prm_write_mod_reg(OMAP24XX_VALID_CONFIG
,
690 OMAP24XX_GR_MOD
, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET
);
698 /* Set the clock rate for a clock source */
699 int omap2_clk_set_rate(struct clk
*clk
, unsigned long rate
)
703 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk
->name
, rate
);
705 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
706 rate table mechanism, driven by mpu_speed */
707 if (clk
->flags
& CONFIG_PARTICIPANT
)
710 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
712 ret
= clk
->set_rate(clk
, rate
);
718 * Converts encoded control register address into a full address
719 * On error, the return value (parent_div) will be 0.
721 static u32
_omap2_clksel_get_src_field(struct clk
*src_clk
, struct clk
*clk
,
724 const struct clksel
*clks
;
725 const struct clksel_rate
*clkr
;
727 clks
= omap2_get_clksel_by_parent(clk
, src_clk
);
731 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
732 if (clkr
->flags
& (cpu_mask
| DEFAULT_RATE
))
733 break; /* Found the default rate for this platform */
737 printk(KERN_ERR
"clock: Could not find default rate for "
738 "clock %s parent %s\n", clk
->name
,
739 src_clk
->parent
->name
);
743 /* Should never happen. Add a clksel mask to the struct clk. */
744 WARN_ON(clk
->clksel_mask
== 0);
746 *field_val
= clkr
->val
;
751 int omap2_clk_set_parent(struct clk
*clk
, struct clk
*new_parent
)
753 u32 field_val
, v
, parent_div
;
755 if (clk
->flags
& CONFIG_PARTICIPANT
)
761 parent_div
= _omap2_clksel_get_src_field(new_parent
, clk
, &field_val
);
765 if (clk
->usecount
> 0)
766 _omap2_clk_disable(clk
);
768 /* Set new source value (previous dividers if any in effect) */
769 v
= __raw_readl(clk
->clksel_reg
);
770 v
&= ~clk
->clksel_mask
;
771 v
|= field_val
<< __ffs(clk
->clksel_mask
);
772 __raw_writel(v
, clk
->clksel_reg
);
775 if (clk
->flags
& DELAYED_APP
&& cpu_is_omap24xx()) {
776 __raw_writel(OMAP24XX_VALID_CONFIG
, OMAP24XX_PRCM_CLKCFG_CTRL
);
780 if (clk
->usecount
> 0)
781 _omap2_clk_enable(clk
);
783 clk_reparent(clk
, new_parent
);
785 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
786 clk
->rate
= new_parent
->rate
;
789 clk
->rate
/= parent_div
;
791 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
792 clk
->name
, clk
->parent
->name
, clk
->rate
);
797 /* DPLL rate rounding code */
800 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
801 * @clk: struct clk * of the DPLL
802 * @tolerance: maximum rate error tolerance
804 * Set the maximum DPLL rate error tolerance for the rate rounding
805 * algorithm. The rate tolerance is an attempt to balance DPLL power
806 * saving (the least divider value "n") vs. rate fidelity (the least
807 * difference between the desired DPLL target rate and the rounded
808 * rate out of the algorithm). So, increasing the tolerance is likely
809 * to decrease DPLL power consumption and increase DPLL rate error.
810 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
811 * DPLL; or 0 upon success.
813 int omap2_dpll_set_rate_tolerance(struct clk
*clk
, unsigned int tolerance
)
815 if (!clk
|| !clk
->dpll_data
)
818 clk
->dpll_data
->rate_tolerance
= tolerance
;
823 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate
,
824 unsigned int m
, unsigned int n
)
826 unsigned long long num
;
828 num
= (unsigned long long)parent_rate
* m
;
834 * _dpll_test_mult - test a DPLL multiplier value
835 * @m: pointer to the DPLL m (multiplier) value under test
836 * @n: current DPLL n (divider) value under test
837 * @new_rate: pointer to storage for the resulting rounded rate
838 * @target_rate: the desired DPLL rate
839 * @parent_rate: the DPLL's parent clock rate
841 * This code tests a DPLL multiplier value, ensuring that the
842 * resulting rate will not be higher than the target_rate, and that
843 * the multiplier value itself is valid for the DPLL. Initially, the
844 * integer pointed to by the m argument should be prescaled by
845 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
846 * a non-scaled m upon return. This non-scaled m will result in a
847 * new_rate as close as possible to target_rate (but not greater than
848 * target_rate) given the current (parent_rate, n, prescaled m)
849 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
850 * non-scaled m attempted to underflow, which can allow the calling
851 * function to bail out early; or 0 upon success.
853 static int _dpll_test_mult(int *m
, int n
, unsigned long *new_rate
,
854 unsigned long target_rate
,
855 unsigned long parent_rate
)
857 int r
= 0, carry
= 0;
859 /* Unscale m and round if necessary */
860 if (*m
% DPLL_SCALE_FACTOR
>= DPLL_ROUNDING_VAL
)
862 *m
= (*m
/ DPLL_SCALE_FACTOR
) + carry
;
865 * The new rate must be <= the target rate to avoid programming
866 * a rate that is impossible for the hardware to handle
868 *new_rate
= _dpll_compute_new_rate(parent_rate
, *m
, n
);
869 if (*new_rate
> target_rate
) {
874 /* Guard against m underflow */
875 if (*m
< DPLL_MIN_MULTIPLIER
) {
876 *m
= DPLL_MIN_MULTIPLIER
;
878 r
= DPLL_MULT_UNDERFLOW
;
882 *new_rate
= _dpll_compute_new_rate(parent_rate
, *m
, n
);
888 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
889 * @clk: struct clk * for a DPLL
890 * @target_rate: desired DPLL clock rate
892 * Given a DPLL, a desired target rate, and a rate tolerance, round
893 * the target rate to a possible, programmable rate for this DPLL.
894 * Rate tolerance is assumed to be set by the caller before this
895 * function is called. Attempts to select the minimum possible n
896 * within the tolerance to reduce power consumption. Stores the
897 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
898 * will not need to call this (expensive) function again. Returns ~0
899 * if the target rate cannot be rounded, either because the rate is
900 * too low or because the rate tolerance is set too tightly; or the
901 * rounded rate upon success.
903 long omap2_dpll_round_rate(struct clk
*clk
, unsigned long target_rate
)
905 int m
, n
, r
, e
, scaled_max_m
;
906 unsigned long scaled_rt_rp
, new_rate
;
907 int min_e
= -1, min_e_m
= -1, min_e_n
= -1;
908 struct dpll_data
*dd
;
910 if (!clk
|| !clk
->dpll_data
)
915 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
916 "%ld\n", clk
->name
, target_rate
);
918 scaled_rt_rp
= target_rate
/ (clk
->parent
->rate
/ DPLL_SCALE_FACTOR
);
919 scaled_max_m
= dd
->max_multiplier
* DPLL_SCALE_FACTOR
;
921 dd
->last_rounded_rate
= 0;
923 for (n
= dd
->min_divider
; n
<= dd
->max_divider
; n
++) {
925 /* Is the (input clk, divider) pair valid for the DPLL? */
926 r
= _dpll_test_fint(clk
, n
);
927 if (r
== DPLL_FINT_UNDERFLOW
)
929 else if (r
== DPLL_FINT_INVALID
)
932 /* Compute the scaled DPLL multiplier, based on the divider */
933 m
= scaled_rt_rp
* n
;
936 * Since we're counting n up, a m overflow means we
937 * can bail out completely (since as n increases in
938 * the next iteration, there's no way that m can
939 * increase beyond the current m)
941 if (m
> scaled_max_m
)
944 r
= _dpll_test_mult(&m
, n
, &new_rate
, target_rate
,
947 /* m can't be set low enough for this n - try with a larger n */
948 if (r
== DPLL_MULT_UNDERFLOW
)
951 e
= target_rate
- new_rate
;
952 pr_debug("clock: n = %d: m = %d: rate error is %d "
953 "(new_rate = %ld)\n", n
, m
, e
, new_rate
);
956 min_e
>= (int)(abs(e
) - dd
->rate_tolerance
)) {
961 pr_debug("clock: found new least error %d\n", min_e
);
963 /* We found good settings -- bail out now */
964 if (min_e
<= dd
->rate_tolerance
)
970 pr_debug("clock: error: target rate or tolerance too low\n");
974 dd
->last_rounded_m
= min_e_m
;
975 dd
->last_rounded_n
= min_e_n
;
976 dd
->last_rounded_rate
= _dpll_compute_new_rate(clk
->parent
->rate
,
979 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
980 min_e
, min_e_m
, min_e_n
);
981 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
982 dd
->last_rounded_rate
, target_rate
);
984 return dd
->last_rounded_rate
;
987 /*-------------------------------------------------------------------------
988 * Omap2 clock reset and init functions
989 *-------------------------------------------------------------------------*/
991 #ifdef CONFIG_OMAP_RESET_CLOCKS
992 void omap2_clk_disable_unused(struct clk
*clk
)
996 v
= (clk
->flags
& INVERT_ENABLE
) ? (1 << clk
->enable_bit
) : 0;
998 regval32
= __raw_readl(clk
->enable_reg
);
999 if ((regval32
& (1 << clk
->enable_bit
)) == v
)
1002 printk(KERN_INFO
"Disabling unused clock \"%s\"\n", clk
->name
);
1003 if (cpu_is_omap34xx()) {
1004 omap2_clk_enable(clk
);
1005 omap2_clk_disable(clk
);
1007 _omap2_clk_disable(clk
);