2.9
[glibc/nacl-glibc.git] / sysdeps / x86_64 / fpu / feenablxcpt.c
blob7bbc368d27088a15dc4da41f31f2f407c241f456
1 /* Enable floating-point exceptions.
2 Copyright (C) 2001, 2007 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
4 Contributed by Andreas Jaeger <aj@suse.de>, 2001.
6 The GNU C Library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 The GNU C Library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with the GNU C Library; if not, write to the Free
18 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
19 02111-1307 USA. */
21 #include <fenv.h>
23 int
24 feenableexcept (int excepts)
26 unsigned short int new_exc, old_exc;
27 unsigned int new;
29 excepts &= FE_ALL_EXCEPT;
31 /* Get the current control word of the x87 FPU. */
32 __asm__ ("fstcw %0" : "=m" (*&new_exc));
34 old_exc = (~new_exc) & FE_ALL_EXCEPT;
36 new_exc &= ~excepts;
37 __asm__ ("fldcw %0" : : "m" (*&new_exc));
39 /* And now the same for the SSE MXCSR register. */
40 __asm__ ("stmxcsr %0" : "=m" (*&new));
42 /* The SSE exception masks are shifted by 7 bits. */
43 new &= ~(excepts << 7);
44 __asm__ ("ldmxcsr %0" : : "m" (*&new));
46 return old_exc;