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2.9
[glibc/nacl-glibc.git]
/
sysdeps
/
unix
/
sysv
/
linux
/
sh
/
sh4
/
sysdep.h
blob
852f8eed7f3f117a44986a933db1aebb6c206ca0
1
/* 4 instruction cycles not accessing cache and TLB are needed after
2
trapa instruction to avoid an SH-4 silicon bug. */
3
#define NEED_SYSCALL_INST_PAD
4
#include <sysdeps/unix/sysv/linux/sh/sysdep.h>