sysdeps/unix/sysv/linux/i386/sysconf.c

   1 /* Get file-specific information about a file.  Linux version.
   2    Copyright (C) 2003, 2004, 2006, 2007 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, write to the Free
  17    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  18    02111-1307 USA.  */
  19
  20 #include <assert.h>
  21 #include <stdbool.h>
  22 #include <stdlib.h>
  23 #include <unistd.h>
  24 #include <hp-timing.h>
  25
  26 static long int linux_sysconf (int name);
  27
  28
  29 static long int __attribute__ ((noinline))
  30 handle_i486 (int name)
  31 {
  32   /* The processor only has a unified level 1 cache of 8k.  */
  33   switch (name)
  34     {
  35     case _SC_LEVEL1_ICACHE_SIZE:
  36     case _SC_LEVEL1_DCACHE_SIZE:
  37       return 8 * 1024;
  38
  39     case _SC_LEVEL1_ICACHE_ASSOC:
  40     case _SC_LEVEL1_DCACHE_ASSOC:
  41       // XXX Anybody know this?
  42       return 0;
  43
  44     case _SC_LEVEL1_ICACHE_LINESIZE:
  45     case _SC_LEVEL1_DCACHE_LINESIZE:
  46       // XXX Anybody know for sure?
  47       return 16;
  48
  49     case _SC_LEVEL2_CACHE_SIZE:
  50     case _SC_LEVEL2_CACHE_ASSOC:
  51     case _SC_LEVEL2_CACHE_LINESIZE:
  52     case _SC_LEVEL3_CACHE_SIZE:
  53     case _SC_LEVEL3_CACHE_ASSOC:
  54     case _SC_LEVEL3_CACHE_LINESIZE:
  55     case _SC_LEVEL4_CACHE_SIZE:
  56     case _SC_LEVEL4_CACHE_ASSOC:
  57       /* Not available.  */
  58       break;
  59
  60     default:
  61       assert (! "cannot happen");
  62     }
  63
  64   return -1;
  65 }
  66
  67
  68 static const struct intel_02_cache_info
  69 {
  70   unsigned int idx;
  71   int name;
  72   long int size;
  73   long int assoc;
  74   long int linesize;
  75 } intel_02_known[] =
  76   {
  77     { 0x06, _SC_LEVEL1_ICACHE_SIZE, 8192, 4, 32 },
  78     { 0x08, _SC_LEVEL1_ICACHE_SIZE, 16384, 4, 32 },
  79     { 0x0a, _SC_LEVEL1_DCACHE_SIZE, 8192, 2, 32 },
  80     { 0x0c, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 32 },
  81     { 0x22, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 },
  82     { 0x23, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 },
  83     { 0x25, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 },
  84     { 0x29, _SC_LEVEL3_CACHE_SIZE, 4194304, 8, 64 },
  85     { 0x2c, _SC_LEVEL1_DCACHE_SIZE, 32768, 8, 64 },
  86     { 0x30, _SC_LEVEL1_ICACHE_SIZE, 32768, 8, 64 },
  87     { 0x39, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 64 },
  88     { 0x3a, _SC_LEVEL2_CACHE_SIZE, 196608, 6, 64 },
  89     { 0x3b, _SC_LEVEL2_CACHE_SIZE, 131072, 2, 64 },
  90     { 0x3c, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 64 },
  91     { 0x3d, _SC_LEVEL2_CACHE_SIZE, 393216, 6, 64 },
  92     { 0x3e, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
  93     { 0x3f, _SC_LEVEL2_CACHE_SIZE, 262144, 2, 64 },
  94     { 0x41, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 32 },
  95     { 0x42, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 32 },
  96     { 0x43, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 32 },
  97     { 0x44, _SC_LEVEL2_CACHE_SIZE, 1048576, 4, 32 },
  98     { 0x45, _SC_LEVEL2_CACHE_SIZE, 2097152, 4, 32 },
  99     { 0x46, _SC_LEVEL3_CACHE_SIZE, 4194304, 4, 64 },
 100     { 0x47, _SC_LEVEL3_CACHE_SIZE, 8388608, 8, 64 },
 101     { 0x48, _SC_LEVEL2_CACHE_SIZE, 3145728, 12, 64 },
 102     { 0x49, _SC_LEVEL2_CACHE_SIZE, 4194304, 16, 64 },
 103     { 0x4a, _SC_LEVEL3_CACHE_SIZE, 6291456, 12, 64 },
 104     { 0x4b, _SC_LEVEL3_CACHE_SIZE, 8388608, 16, 64 },
 105     { 0x4c, _SC_LEVEL3_CACHE_SIZE, 12582912, 12, 64 },
 106     { 0x4d, _SC_LEVEL3_CACHE_SIZE, 16777216, 16, 64 },
 107     { 0x4e, _SC_LEVEL2_CACHE_SIZE, 6291456, 24, 64 },
 108     { 0x60, _SC_LEVEL1_DCACHE_SIZE, 16384, 8, 64 },
 109     { 0x66, _SC_LEVEL1_DCACHE_SIZE, 8192, 4, 64 },
 110     { 0x67, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 },
 111     { 0x68, _SC_LEVEL1_DCACHE_SIZE, 32768, 4, 64 },
 112     { 0x78, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
 113     { 0x79, _SC_LEVEL2_CACHE_SIZE, 131072, 8, 64 },
 114     { 0x7a, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 },
 115     { 0x7b, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 64 },
 116     { 0x7c, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
 117     { 0x7d, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 64 },
 118     { 0x7f, _SC_LEVEL2_CACHE_SIZE, 524288, 2, 64 },
 119     { 0x82, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 32 },
 120     { 0x83, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 32 },
 121     { 0x84, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 32 },
 122     { 0x85, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 32 },
 123     { 0x86, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
 124     { 0x87, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
 125   };
 126 #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
 127
 128
 129 static int
 130 intel_02_known_compare (const void *p1, const void *p2)
 131 {
 132   const struct intel_02_cache_info *i1;
 133   const struct intel_02_cache_info *i2;
 134
 135   i1 = (const struct intel_02_cache_info *) p1;
 136   i2 = (const struct intel_02_cache_info *) p2;
 137
 138   if (i1->idx == i2->idx)
 139     return 0;
 140
 141   return i1->idx < i2->idx ? -1 : 1;
 142 }
 143
 144
 145 static long int
 146 __attribute__ ((noinline))
 147 intel_check_word (int name, unsigned int value, bool *has_level_2,
 148                   bool *no_level_2_or_3)
 149 {
 150   if ((value & 0x80000000) != 0)
 151     /* The register value is reserved.  */
 152     return 0;
 153
 154   /* Fold the name.  The _SC_ constants are always in the order SIZE,
 155      ASSOC, LINESIZE.  */
 156   int folded_name = (_SC_LEVEL1_ICACHE_SIZE
 157                      + ((name - _SC_LEVEL1_ICACHE_SIZE) / 3) * 3);
 158
 159   while (value != 0)
 160     {
 161       unsigned int byte = value & 0xff;
 162
 163       if (byte == 0x40)
 164         {
 165           *no_level_2_or_3 = true;
 166
 167           if (folded_name == _SC_LEVEL3_CACHE_SIZE)
 168             /* No need to look further.  */
 169             break;
 170         }
 171       else
 172         {
 173           if (byte == 0x49 && folded_name == _SC_LEVEL3_CACHE_SIZE)
 174             {
 175               /* Intel reused this value.  For family 15, model 6 it
 176                  specifies the 3rd level cache.  Otherwise the 2nd
 177                  level cache.  */
 178               unsigned int eax;
 179               unsigned int ebx;
 180               unsigned int ecx;
 181               unsigned int edx;
 182               asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 183                             : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 184                             : "0" (1));
 185
 186               unsigned int family = ((eax >> 20) & 0xff) + ((eax >> 8) & 0xf);
 187               unsigned int model = ((((eax >>16) & 0xf) << 4)
 188                                     + ((eax >> 4) & 0xf));
 189               if (family == 15 && model == 6)
 190                 {
 191                   /* The level 3 cache is encoded for this model like
 192                      the level 2 cache is for other models.  Pretend
 193                      the caller asked for the level 2 cache.  */
 194                   name = (_SC_LEVEL2_CACHE_SIZE
 195                           + (name - _SC_LEVEL3_CACHE_SIZE));
 196                   folded_name = _SC_LEVEL3_CACHE_SIZE;
 197                 }
 198             }
 199
 200           struct intel_02_cache_info *found;
 201           struct intel_02_cache_info search;
 202
 203           search.idx = byte;
 204           found = bsearch (&search, intel_02_known, nintel_02_known,
 205                            sizeof (intel_02_known[0]), intel_02_known_compare);
 206           if (found != NULL)
 207             {
 208               if (found->name == folded_name)
 209                 {
 210                   unsigned int offset = name - folded_name;
 211
 212                   if (offset == 0)
 213                     /* Cache size.  */
 214                     return found->size;
 215                   if (offset == 1)
 216                     return found->assoc;
 217
 218                   assert (offset == 2);
 219                   return found->linesize;
 220                 }
 221
 222               if (found->name == _SC_LEVEL2_CACHE_SIZE)
 223                 *has_level_2 = true;
 224             }
 225         }
 226
 227       /* Next byte for the next round.  */
 228       value >>= 8;
 229     }
 230
 231   /* Nothing found.  */
 232   return 0;
 233 }
 234
 235
 236 static long int  __attribute__ ((noinline))
 237 handle_intel (int name, unsigned int maxidx)
 238 {
 239   if (maxidx < 2)
 240     {
 241       // XXX Do such processors exist?  When we know we can fill in some
 242       // values.
 243       return 0;
 244     }
 245
 246   /* OK, we can use the CPUID instruction to get all info about the
 247      caches.  */
 248   unsigned int cnt = 0;
 249   unsigned int max = 1;
 250   long int result = 0;
 251   bool no_level_2_or_3 = false;
 252   bool has_level_2 = false;
 253   while (cnt++ < max)
 254     {
 255       unsigned int eax;
 256       unsigned int ebx;
 257       unsigned int ecx;
 258       unsigned int edx;
 259       asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 260                     : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 261                     : "0" (2));
 262
 263       /* The low byte of EAX in the first round contain the number of
 264          rounds we have to make.  At least one, the one we are already
 265          doing.  */
 266       if (cnt == 1)
 267         {
 268           max = eax & 0xff;
 269           eax &= 0xffffff00;
 270         }
 271
 272       /* Process the individual registers' value.  */
 273       result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
 274       if (result != 0)
 275         return result;
 276
 277       result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
 278       if (result != 0)
 279         return result;
 280
 281       result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
 282       if (result != 0)
 283         return result;
 284
 285       result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
 286       if (result != 0)
 287         return result;
 288     }
 289
 290   if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
 291       && no_level_2_or_3)
 292     return -1;
 293
 294   return 0;
 295 }
 296
 297
 298 static long int __attribute__ ((noinline))
 299 handle_amd (int name)
 300 {
 301   unsigned int eax;
 302   unsigned int ebx;
 303   unsigned int ecx;
 304   unsigned int edx;
 305   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 306                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 307                 : "0" (0x80000000));
 308
 309   if (name >= _SC_LEVEL3_CACHE_SIZE)
 310     return 0;
 311
 312   unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
 313   if (eax < fn)
 314     return 0;
 315
 316   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 317                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 318                 : "0" (fn));
 319
 320   if (name < _SC_LEVEL1_DCACHE_SIZE)
 321     {
 322       name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
 323       ecx = edx;
 324     }
 325
 326   switch (name)
 327     {
 328     case _SC_LEVEL1_DCACHE_SIZE:
 329       return (ecx >> 14) & 0x3fc00;
 330     case _SC_LEVEL1_DCACHE_ASSOC:
 331       ecx >>= 16;
 332       if ((ecx & 0xff) == 0xff)
 333         /* Fully associative.  */
 334         return (ecx << 2) & 0x3fc00;
 335       return ecx & 0xff;
 336     case _SC_LEVEL1_DCACHE_LINESIZE:
 337       return ecx & 0xff;
 338     case _SC_LEVEL2_CACHE_SIZE:
 339       return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
 340     case _SC_LEVEL2_CACHE_ASSOC:
 341       ecx >>= 12;
 342       switch (ecx & 0xf)
 343         {
 344         case 0:
 345         case 1:
 346         case 2:
 347         case 4:
 348           return ecx & 0xf;
 349         case 6:
 350           return 8;
 351         case 8:
 352           return 16;
 353         case 0xf:
 354           return (ecx << 6) & 0x3fffc00;
 355         default:
 356           return 0;
 357         }
 358     case _SC_LEVEL2_CACHE_LINESIZE:
 359       return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
 360     default:
 361       assert (! "cannot happen");
 362     }
 363   return -1;
 364 }
 365
 366
 367 static int
 368 i386_i486_test (void)
 369 {
 370   int eflags;
 371   int ac;
 372   asm volatile ("pushfl;\n\t"
 373                 "popl %0;\n\t"
 374                 "movl $0x240000, %1;\n\t"
 375                 "xorl %0, %1;\n\t"
 376                 "pushl %1;\n\t"
 377                 "popfl;\n\t"
 378                 "pushfl;\n\t"
 379                 "popl %1;\n\t"
 380                 "xorl %0, %1;\n\t"
 381                 "pushl %0;\n\t"
 382                 "popfl"
 383                 : "=r" (eflags), "=r" (ac));
 384
 385   return ac;
 386 }
 387
 388
 389 /* Get the value of the system variable NAME.  */
 390 long int
 391 __sysconf (int name)
 392 {
 393   /* All the remainder, except the cache information, is handled in
 394      the generic code.  */
 395   if (name < _SC_LEVEL1_ICACHE_SIZE || name > _SC_LEVEL4_CACHE_LINESIZE)
 396     return linux_sysconf (name);
 397
 398   /* Recognize i386 and compatible.  These don't have any cache on
 399      board.  */
 400   int ac = i386_i486_test ();
 401
 402   if (ac == 0)
 403     /* This is an i386.  */
 404     // XXX Is this true for all brands?
 405     return -1;
 406
 407   /* Detect i486, the last Intel processor without CPUID.  */
 408   if ((ac & (1 << 21)) == 0)
 409     {
 410       /* No CPUID.  */
 411       // XXX Fill in info about other brands.  For now only Intel.
 412       return handle_i486 (name);
 413     }
 414
 415   /* Find out what brand of processor.  */
 416   unsigned int eax;
 417   unsigned int ebx;
 418   unsigned int ecx;
 419   unsigned int edx;
 420   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 421                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 422                 : "0" (0));
 423
 424   /* This spells out "GenuineIntel".  */
 425   if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
 426     return handle_intel (name, eax);
 427
 428   /* This spells out "AuthenticAMD".  */
 429   if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
 430     return handle_amd (name);
 431
 432   // XXX Fill in more vendors.
 433
 434   /* CPU not known, we have no information.  */
 435   return 0;
 436 }
 437
 438 /* Now the generic Linux version.  */
 439 #undef __sysconf
 440 #define __sysconf static linux_sysconf
 441 #include "../sysconf.c"